Computer technology forecast study for general aviation

COMPUTER TECHNOLOGY FORECAST STUDY FOR GENERAL AVIATION SECTION 1 SUMMARY A survey/study to define the type of computer hardware that will be available and suitable for use in general-aviation aircraft avionics during the 1980's has been made. The purposes of this study are: • To assess the current state of the art in computer technology to define what is suitable for use in low-cost avionics.

• To identify those industrial and commercial uses of computer hard- ware that would tend to provide sources of low-cost computers.

• To assess the direction and extent of future computer technology developments that would aid the application of electronic computing to low-.cost avionics.

• To evaluate the risk associated with the applicable computer tech- nologies and make recommendations for future NASA effort that would aid the development of more effective avionics for general aviation aircraft.

The study was based on data available in early 1976. Much of the infor- mation presented, in particular that concerning semiconductor logic and memory devices, was gathered from sources within Honeywell Inc, Additional information on specialized devices and recent developments was obtained from visits to semiconductor integrated circuit manufacturers, a survey of recent technical publications and applicable manufacturer's device specifications. The results are summarized in this report,- which contains condensed examples of the characteristics of the various types of computer hardware. More detailed information on the various technologies is pre- sented in accompanying appendices, :;' From the study, the following conclusions have been made.

Current, and probable future, LSIC (large-scale integrated circuit) • semiconductor devices will satisfy all general-aviation avionics computing requirements. The most promising bipolar forms for future applications are integrated injected logic (I 2 L) and direct coupled transistor-transistor logic (DCT 2 L). A number of alternate structures have been postulated to further improve the characteris- tics of MOS; of these, VMOS and CMOS/SOS appear the most likely technologies for 1980's applications..

• The advantages of LSIC technology, namely, low cost and large volume, are gainfully exploited by two important features of the microprocessor. The microprocessor can be used as a universal standard component for many general-aviation avionics applications and permits the easy formation of multiprocessor networks. The increasing capability and decreasing cost of microprocessors is slowing the application of data bus techniques and encouraging the use of dedicated computers. In addition, low computer costs will t f 11 1 ^d d d t if h h promo e use o para e un ancy an ex ensive se c eck to suc re an extent that the failure probability of the computer function will become negligible in relation to that for the complete system.

Among all the memory technologies core, semiconductor, plated wire, disk, drum and more recent exotic memory types — only semiconductors are projected to show significant improvements in application to general- ?

aviation avionics.

It appears probable that the cost of computing equipment per se (logic and memory) will represent a relatively small portion of a total general-aviation .j avionics system cost. Conversely, input/output (1/0) devices (for example, inertial sensors, displays, and control servos) are currently, and will con- tinue to be, costly items due to the lack of nonaviation large-volume users of j such devices and their need for tailoring to a specific system design.

I It is recommended that NASA: • Consider sponsoring programs to develop more cost - effective 1/0 devices (particularly inertial sensors, and command and situation displays) designed specifically for general-aviation application.

• Pursue work to define the functional requirements for future gener- al-aviation avionic systems and the system configuration(s) that will meet the improved requirements.

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SECTION 2 INTRODUCTION BACKGROUND NASA has underway a multi-year, multi-faceted program to investigate and develop potential improvements in airframes, engines, and avionics for general-aviation aircraft. Reference 1 contains a summary of past work in this area. As part of this overall program, a general-aviation avionics research and techology program has been initiated. It is the basic premise of this program that by using 1980 electronics technology, many significant improvements can be made in general-aviation avionics system design; for example, the use of digital computers to assist the pilot in performing the functions involved in general aviation, such as navigation, guidance, control, fuel management, and communications. Studies have been initiated to define the advanced electronics technology available in the late 1970's and early 1980's upon which an advanced general-aviation avionics system design could be based. The objective of this study was to assemble information that will allow the Government to assess the trends in computer and computer/ operator interface technology that may have application to general aviation in the 1980's and beyond, PURPOSE The study assesses the current, state of the art of computer hardware, predicts technical developments in computer hardware through the 1980's, identifies nonaviation large-volume users of computer hardware that might provide a source of low-cost components, and males recommendations for i } r a further NASA work that would accelerate technical development and/or sup- port high-risk developments.

CONDITIONS AND SCOPE OF STUDY The survey / study as conducted b the Aircraft Flight Systems g rou p Yl Y Y g Y g P of the Government and Aeronautical Products Division of Honeywell, Inc.

with the participation of the Computer Technology Group of the Systems and.

Research Division of Honeywell. Both these groups are actively engaged in the development of advanced computers for aviation use, and much of the data in this report has been taken from various on-going programs. In addition, surveys were made of recent technical and r ';ommercial data on all elements of computer-based systems, and leading manufacturers of appli cable hardware were contacted on current and future technology, k t In projecting future avionic requirements, considerable dependence was placed on interviews with active pilots and reviews of current general- aviation publications. In logic, memory, and display the range of tech- nologies covered by the study is wide, covering several areas that currently appear to have little application to avionics , rbut are included because they, may have application in the future.

Specifically, all types of semiconductor logic and memory devices that are beyond the basic research stage and appear to have some practical g , i applications are included_ In the memory area, all feasible magnetic devices . and schemes and several optical readout/plastic medium arrangements were reviewed. In the case- of display elements, several concepts in addition to the familiar cathode ray tube (CRT), light-emitting diodes (LED), liquid crystal display (LCD) and incandescents are covered.

The application of various approaches to generating computer software machine and assembly language, compilers for higher-order (e, g., j languages) has been considi -red in light of the peculiar requirements of the general-aviation avionics industry, and the manner in which the required computing capability is deployed in a total avionic system has been reviewed, particularly in regard to potential improvements in overall system integrity and ease of maintenance. Factors considered in this regard are busing, distributed versus central arithmetic and memory units, and the use of various self-check or fault-isolation techniques.

Because of the large volume of background material collected in the this report has a number of appendices which contain pertinent back- study, ground information that may not be generally available as reference material.

It should be noted that mucli of the data presented in the appendices concern- ing logic and memory elements has been taken directly from other projects or studies. Development work in this field is proceeding rapidly and there are advances being made continually. In general, the approach in projecting the future status of the various technologies has been conservative. Any quantitative study and specific system designs should be based on the latest information rather than that contained in the appendices to this report.

SIGNIFICANCE OF THIS STUD' This study does not provide quantitative design data nor does it predict the configuration of future general-aviation avionic systems; the intent was to evaluate' in a qualitative manner (backed up by quantitative data) the applicability of current and future computer technology to general -aviation, avionics. It is belie -n ed that the conclusions reached are valid and rather obvious in regard to logic and memory devices; however, in the cases of sensors and displays, the direction of growth is uncertain. Even so, the data presented can be used as a basis for formulating succeeding studies and/or development work toward the ultimate objective, }

j SECTION 3 LIST OF ABBREVIATIONS AND ACRONYMS Abbreviations: A ampere cd candela ft-L foot-lambert hp horsepower hr hour Hz hertz K knots lm lumen m meter mil 1 mil = 0.001 in.

microsecond μ sec millisecond msec nautical mile n. mi.

nsec nanosecond sr steradian V volts W watt Acronyms: analog to digital A / D ASC H American standard code for information exchange ATC air traffic control ATCRBS air traffic control radar beam system - beam addressed metal oxide semiconductor wiring BEAMOS BOBAM block oriented random access memory CAS collision avoidance system charge-coupled device CCD CHL current-hogging logc(sarrie as I2 L) C3 complementary current logic (same as I2 L) i \Yj CML current mode logic CMOs complementary metal oxide semiconductor CRT cathode ray tube 3D triple diffusion device structure D/A digital to analog DABS discrete address beacon system DCT2 L direct coupled transistor - transistor logic DIMOS dielectric isolated metal oxide semiconductor DME distance :measuring equipment DMOS double diffused metal oxide semiconductor DTL diode transistor logic electrically alterable read only memory EAROM electrochromatic display ECD emitter-coupled logic ECL EFL emitter follower logic ELD eloctroluminescent device epitaxial collector structure EPI EPID electrophoretic display FAR federal aviation regulations field effect transistor FET gas plasma device GPD Group I, classification of airports in regard to landing II and III restrictions terminals high-order language HOL integrated circuit IC IFR instrument flight rules I2L integrated injection logic { ILS instrument landing system i INS _ inertial navigation system input/output I/O a Josephson tunneling logic JTL KOPS thousand operations per second LCD liquid crystal display LED light-emitting diode L ?

I LSIC large-scale integrated circuit MECL Motorola emitter coupled logic microwave landing system MLS j metal nitride oxide semiconductor MNOS MOS metal oxide semiconductor MOSFET metal oxide semiconductor field effect transistor MSIC medium-scale integrate circuit MTL merged transistor, logic (same as I 2 L) nondestructive read out NDRO NMOS N-channel metal oxide semiconductor lead, lanthanum, zirconium, and titanium ceramics PLZT P-channel metal oxide semiconductor PMOS radio frequency RF area navigation R-NA V resistor transistor logic RTL SBTTL Schottky barrier transistor-transistor logic SFL substrate fed logic (same as I 2 L) SOS silicon on substrate TFT thin-film transistor -transistor logic T 2 transistor transistor-transistor-transistor logic TTL with PNP T 3 L emitter follow input T 2 LS transistor-transistor logic (Schottky) transistor-resistor logic TRL transistor-transistor logic TTL V / F voltage to frequency VFR visual flight rules V-groove metal oxide semiconductor VMOS VHF omni-directional radio range VCR i

SECTION 4 ASSESSMENT OF FUTURE GENERAL-AVIATION REQUIREMENTS GENERA L-A VIAT102N REQUIREMENTS Airframe/Avionics Classification Currently available general-aviation aircraft form a continuous pro- gression from single-place pure sport planes to multi-engine fan jets with transoceanic capability. Any grouping of all these types of aircraft is bound to be arbitrary, but grouping into subsets. is necessary because the air- planes and the avionic equipment obviously differ greatly. The approach used in this study is to start with those airplanes that have the minimum capability to contribute to the national transport capability and work up to the business jet class. There are, of course, a number of actual commercial transport airplanes used as general-aviation aircraft by large companies or wealthy individuals, but these are ususally flown, equipped, and serviced not considered in the same manner as commercial transports and are in this study. Between the minimum capability aircraft (Class C) and the multi-engine turbine-powered aircraft (Class A aircraft, which in many cases carry avionics suites very similar to those of commercial aircraft), j the twin-engine piston aircraft (Class B) have been lumped as comprising a group with requirements for more than minimum avionics capability, but still not justifying the cost of more sophisticated avionics. The criterion for the :lowest class (i.'e, 200 horsepower or greater) may seem to be restrictive in that many lower powered aircraft having cross-country transportation capability are excluded. The reasoning here is that the func- tion of the airplane (cross-country transportation) will probably require that these lower powered airplanes carry avionics approximately equal to the higher powered aircraft, and thus a separate class of aircraft/avionics is not

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needed. Types of aircraft specifically excluded from any of these groups, even though some of them have more than 200 horsepower, are trainers, sport and acrobatic planes, agricultural aircraft, and helicopters, Table 1 presents a summary chart showing airplane characteristics, type of use, air traffic control (ATC) environment, and weather capability for each of the three classes of aircraft, as well as an indication of where com- puter technology may be effectively applied. Table 2 gives more detailed data on each of the three classes of aircraft in the form of maximum, mini- mum, and average values of airframe cost, cruise speed, cruise range, and cruise endurance. Table 3 lists the avionics associated with each type of aircraft, and Table 4 lists the specific aircraft which make up each class.

As noted, this classification is arbitrary and obviously different group- ings could be made. However, the current study is concerned with the appli- cation of computer technology to future general-aviation avionics rather than with the details of the aircraft and avionics themselves, Also it is felt that a the future application of computer technology to the various levels of avionics will differ in degree rather than principle. Therefore, three classes of air- craft and accompanying avionics were chosen as sufficient to characterize the entire range, In the process of classifying the aircraft and avionics, considerable use was made of the data presented in Reference 2, which gives detailed statistics on general-aviation aircraft and avionics.

In an effort to substantiate the recommendations for future research (discussed in Section 8), a cursory analysis of the cost of typical general aviation subsystems was made. The object was to assess the influence of the cost of various types of hardware (e, g. , RF receivers, computers and mem- ory, inertial sensors) on the cost of the complete subsystem. The relative costs were estimated from manufacturers' parts lists where available or from design data and typical parts costs where the actual pr.:es were not available. The figures presented in Table 5 are typical rather than exact TABLE 1. - CHARACTERISTICS OF TYPICAL CURRENT GENERAL-AVIATION AIRCRAFT Averages Cruise Aircraft No, of

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Mission Range, Speed, Endurance, class Airframe Avionics pilots cost, $ cost, n, mi. K hr 1 270 000 1 592 345 4.7 2 • Business, company crew A ) Multi-engine 159 720 turbine 0 Third-level airline • Charter • Air freight B) Twin-engine 145 000 17 235 1 127 208 5.4 1-2 • Pleasure piston • Business Small-business, owner operated Corporate, contract pilot Air taxi, passenger and freight C) Single-engine 42 790 7 287 832 154 5.4 1 • Pleasure piston ^! 200 hp • Business Small business, owner operated Air taxi, passenger and freight Charter, passenger and freight TABLE 1. — CHARACTERISTICS OF TYPICAL CURRENT GENERAL-AVIATION AIRCRAFT (Concluded) Aircraft I ATC ( Weather I Computer applications environment class • VFR Flight stabilization, area navigation, A) Multi-engine r 'Controlled air space turbine Enroute flight management, fuel management • IFR Terminal groups I, 11, III computations, flight progress com- Known icing, putations.

Tower thunderstorms; cate- Uncontrolled air space gory I and II approaches • Seldom used Controlled air space • VFR Flight stabilization, area navigation, B) Twin-engine • piston Enroute flight management, fuel management • IFR Terminal groups I, II, III computations, flight progress com- Light icing, scattered Tower putations.

thunderstorms; cloud • Uncontrolled air speed ceilings and visibilities Occasional user down to category I minimums Controlled air space • VFR Flight stabilization, area navigation, flight C) Single-engine • piston Z 200 hp Enroute • IFR progress computations Terminal groups I, II, III to known icing, or Tower

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thunderstorms; ceilings Uncontrolled and visibility down to • category I minimulr s

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A I Y ^ TABLE 2. — AIRCRAFT CLASS STATISTICS Class A — Multi-engine turbine units surveyed: 32 Airframe Cruise Speed, cost, Range, Endurance, $ K n. mi. hr Minimum 385 000 170 828 2.4 Maximum 4 000 000 495 3 642 8.3 Average 1 270 000 345 1 592 4.7 Class B - Twin engine — piston units surveyed: 24 Airframe Cruise cost, Speed, Range, Endurance, $ K n, mi. hr Minimum 63 000 760 4.0 Maximum 241 000 260 1 440 6.5 Average 145 000 208 1 127 5.4 Class C — Single engine >_ 200 hp units surveyed: 32 Airframe Range, cost, Speed, Endurance, $ K n. mi. hr 25 000 Minimum 130 466 3.4 Maximum 85 000 1 485 7.8 Average 42 790 154 832 5.4 TABLE 3. - AVIONICS Class C Single engine, > 200 hp, avionics cost as percent of airplane cost = 17% Use in Cost in Average cost Quantity TUnit percent dollars in dollars 1 #1 Nav/communication 100 2 000 2 000 1 #2 Nav/communication 70 1 000 700 Automatic direction finder 80 1 000 800 Transponder 100 600 600 Distance measuring equipment (DME) 50 000 500 1 1 Audio/marker 100 270 270 Emergency location transmitter 100 125 125 1 Autopilot 50 2 000 1 000 10 2 000 200 1 Radar altimeter Radio telephone 2 1 600 32 2 000 60 1 R Nav 3 7 287 Total Class B Twin engine — piston, avionics cost as percent of airplane cost = 12% Use in Cost in Average cost Quantity Unit percent dollars in dollars #1 Nav/communication 100 2 600 2 600 2 000 800 1 #2 Nav/communication 90 1 90 1 500 1 350 1 Glidesiope 1 400 1 400 1 Automatic direction finder 100 100 600 600 1 Transponder Distance measuring equipment (DME) 60 2 500 1 100 270 270 1 Audio marker Emergency location transmitter 100 150 150 75 5 000 3 750 1 Autopilot Radar altimeter 25 2 000 500 25 7 500 1 875 1 Radar weather Radio telephone 15 1 600 240 2 000 200 1 R-Nav 10 Integrated display 25 2 000 500 1 lot Adapters, interface units, converters optional display 25 2 000 Total 17 235 TABLE 3. — AVIONICS (Concluded) Class A Multi-engine turbine, avionics cost as percent of airplane cost = 12. 510 Use in Cost in verage cost Unit Quantity in dollars percent dollars F 3 000 6 000 2 Communication 100 100 1 600 1 600 1 Navigator 1 500 3 000 2 Glideslope marker beacon 100 3 370 6 740 2 Automatic direction finder 2 300 4 600 2 Remote magnetic indicator 100 100 2 190 4 380 2 Transponder 100 3 900 7 800 2 Distance measuring equipment (DME) 1 800 100 1 800 1 Audio 100 10 000 10 000 1 Autopilot 100 24 300 48 600 2 Flight directors 12 000 12 000 1 R-Nav 100 100 5 360 10 720 2 Encoding altimeter 100 18 000 18 000 Weather radar " " 100 4 700 9 400 2 Radar altimeter 2 800 2 800 Radio telephone 100 100 280 1 Emergency location transmitter 12 000 12 000 1 lot Control heads 100 Adaptors Interface units Converters Optional displays Intercoms, etc.

Total 159 720 f TABLE 4, — AIRCRFT USED IN SURVEY Class C Single engine > 200 hp Cost in Manufacturer Model ( llars do Skywagon 180 25 700 Cessna Skywagon 182 26 700 Cessna Skylane 27 950 Cessna Cessna Skywagon 185 30 175 Cessna Stationair 375 37 250 Cessna Skywagon 207 Turbo Stationair 41 625 Cessna Turbo Skywagon 207 42 725 Cessna Cardinal RG 30 950 Cessna Centurian 47 950 Cessna Turbo Centurion 53 150 Cessna Cherokee Pathfinder 235 27 070 Piper 32 170 Cherokee Six 260 Piper Cherokee Six 300 35 740 Piper Arrow II 27 690 Piper Sierra 200 B24R 30 250 Beech Bonanza F33A 55 400 Beech Bonanza V35B 55 400 Beech Bonanza A36 59 000 Beech 28 500 Chaparral M20E Mooney 30 500 Executive M20F Mooney 38 990 Super Viking 17-30A Bellanca 41 110 Bellanca Super Viking 17-31A 48 545 Bellanca Turbo Viking 300A 80 000 Bellanca Skyrocket_H 19-25 Commander 112A 33 500 Rockwell- Rallye 220 GT 33 000 Aerospatiale - Super Courier H-295 '81 740 Helio 85 869 Tri-gear Courier HT-.295 Helio 46 250 Navion Range Master H i Tri Gull 320 59 500- y Trident Buccaneer 37 950 Lake TABLE 4. — AIRCRAFT USED IN SURVEY (Continued) Class B Twin engine — piston Cost in Manufacturer Model dollars Skymaster 63 300 Cessna 310 89 950 Cessna Cessna Pressurized Skymaster 94 100 Cessna Turbo 310 107 500 Cessna 402B 138 500 Cessna 340 143 950 414 174 950 Cessna 421B 229 950 Cessna Seneca II 63 995 Piper Piper Aztec E $8 200 Piper Turbo Aztec E 99 095 Turbo Navajo B 139 100 Piper Piper . Navajo Cheftain 167 995 Piper Pressurized Navajo 241 400 Beech Baron B55 89 000 Beech Baron E55 109 500 Beech Baron 58 128 000 Beech Duke B60 219 450 Beech Queen Air B80 240 925 Rockwell Shrike Commander 128 150 Commander 685 229 440 Rockwell Aerostar 600 138 800 Ted Smith Aerostar 601 156 200 Ted Smith Ted Smith Aerostar 601P 198 900 1^ TABLE 4. — AIRCRAFT USED IN SURVEY (Concluded) Class A Turbine — multi-engine Cost in Manufacturer Model dollar s Cessna Citation 795 000 Piper Navajo Cheyenne 459 000 Beech King Air C90 476 500 Beech King Air E90 593 000 Beech Airliner B99 691 500 Beech King Air A100 733 750 Beech Super King Air 806 000 Beech BH-125-600 1 886 000 Rockwell Turbo Commander 690A 473 000 deHavilland Twin Otter 595 000 Mitsubishi MU-2M 669 625 MU-2L Mitsubishi 767 625 Swearinger Merlin IIIA 725 000 Swearinger Merlin IVA 815 000 Swearinger Metro II 815 000 Shorts SD3-30 1 400 000 Learjet 24D 941 Gates 500 Learjet 25B 1 071 500 Gates Learjet 25C 1 138 000 Gates Learjet 35 1 395 000 Gates Gates Learjet 36 1 445 000 Aerospatiale SN601 Corvette 1 300 000 IAI 1124 Westwind 1 550 000 Dassault Falcon 10 1 575 000 Dassault Falcon 20E Cargo 2 200 000 2 225 Dassault Falcon 20E 000 Dassault Falcon 20F 475 000 Sabre 60 - 690 000 Rockwell 1 Sabre 75A 2 195 000 Rockwell Jet Star II 3 750 000 Lockheed _ Grumann Gulfstream II 3 900 000 Shorts Harland Sky Van 3 750 000 C) TABLE 5, RELATIVE COSTS OF SUBSYSTEM ELEMENTS (GIVEN IN PERCENT OF TOTAL SYSTEM COST)a Major assemblies Subsystem Computer Inertial Controls Receivers Display Servos sensors and memory 25 25 10 R-NAV 40 Autopilot /stability augmentation system, 20 10 35 35 3 axis ' 25 30 40 Flight director 25 5 65 I-NAV ILS and 10 15 communication 75 a Each system is assumed independent, as flight directors and autopilots must be independent for Category II operation, for any specific model of subsystem; the totals would not be changed much by t5 percent variations in any of the subassembly costs. The results indi- cate that while computer and memory costs are significant, they are by no means dominant, comprising no more than 35 percent of any of the system costs. RF receivers, inertial sensors, and displays all have approximately an equal overall. cost effect on a complete avionics system. Therefore, while the computation function per se is an important part of avionics sub- system costs, there are also other elements that must receive equal or greate.- emphasis in the effort to reduce total avionics costs, Air Traffic Control Environments The ATC environments given in Table 1 for each of the classes of air- craft differ very little in absolute requirements, but differ considerably in requirements. Class C aircraft are expected to the emphasis on the various be used a significant amount of time in uncontrolled air space and infrequent- They are not expected to use Group I terminals ly in controlled air space.

except in unusual circumstances, The ATC environments for Classes A and B are essentially the same with only a minor difference in the expected use Essentially all three categories must be able to of uncontrolled air space.

Probably the biggest difference in operate in all types of ATC environment.

the functional requirements of the avionics comes from the airframe charac- teristics themselves, i. e, , the higher speed, altitude, and fuel consumption of the higher-level aircraft. The obvious trend for the future will be for more positive controlled air space, probably requiring user aircraft to be equipped will be that most useful for ATCRBS and ultimately DABS. The end result cross-country missions will encounter positive controlled air space, and all general aviation will have to be equipped with the proper ATC equipment.

I Weather Conditions se will have "little effect on avionics beyond the Weather conditions per i sort of weather creates the need _obvious fact that poor visibility due to any c for instrument flight rules (IFR) and their associated equipment. Two other weather characteristics which affect aviation are turbulence and icing; however, the capability of operating in these conditions is far more dependent the avionics. No amount of avionics will prevent ice on on the airplane than from forming on an airplane that does not have adequate deicing features.

only part that avionics could play in combatting icing would be in the regard In reporting of icing conditions by ground stations or other aircraft.

to turbulence, there can be considerable improvement in handling qualities in mild turbulence by use of stability augmentation. Flight in turbulence that approaches the structural capability of general-aviation aircraft (FAR, part 23), would be intolerable to the aircraft occupants; again, the role, of avionics would be in providing information to enable the pilot to avoid turbulent areas of severe turbulence.

a VARIATIONS OF APPLICABLE/REQUIRED CLASS COMPUTER TECHNOLOGY FOR EACH General Considerations , There are reasons to think that the level of technology would be the same for all classes of aircraft. For example, all classes must operate in the same controlled air space, must at sometime encounter similar weather, and must use the same ground navigation facilities. However, the differences in the areas of pilot qualification/work load and the criticality of the avionics functions and the mission itself require different capabilities. Class A (turbojet) aircraft and the missions for which they are intended definitely require more highly trained pilots and impose a higher work load on the pilot than do Class C aircraft. Further, because of low altitude fuel consumption and airstrip requirements, it is far more critical for a business jet to fly -a direct course to the intended airport than for a single-engine propeller air- plane. Therefore, avionics for high-performance aircraft require greater mission reliability, automaticity, precision (particularly in flight-control g q equipment), and unfortunately complexity. These differing requirements affect the level of avionics technology required for the various aircraft classes.

Variations in Required Technology Levels The relationship of technology to aircraft class can best be illustrated use of the following breakdown; y b • Logic, memory, and I/O devices { •_ Input' and display devices • RF electronics Inertial sensors and servos • • Computer architecture and software • Overall avionic system configuration Logic and memory. -- Logic and memory types will differ little from one Several studies (e. g, 3 and 4) and recent industry expe- class to the other, rience have shown that 1.6-bit-word digital processors are necessary and sufficient for most navigation and flight control functions. Twelve-bit pro- cessors could be used for flight control for low-performance aircraft (Class C), but this is a comparatively minor application and thus far the tendency 16 bits in terms of the digital electronics if more is to move from Q ?fits to There may well be several types of actual semiconduc- precision is needed, tor techniques in use because, as shown in Section 5, no one technique has clear and overriding advantages over the others. These are significant dif-- ferences in inherent gate speed and power consumption, but current devices I T demonstrate' that at least metal oxide semiconductor (MOS), transistor- transistor logic (TTL), and emitter-coupled logic (ECL) devices are suitable and available for avionics use, On the other hand there will be significant differences in the amount of throughput or memory that is needed. For example, there is on the market today a low-cost (10 way point) R-Nav that uses a microprocessor with about ^Y t a .

5 KOPS (thousands of operation per second) throughput and 1024 bits of mem- ory. In contrast, a sophisticated airline-quality R -Nav may have a throughput of 50 KOPS and 192, 000 bits of program, scratchpad, and data memory, Also the amount of logic and memory required for flight control will vary with the type of aircraft. A light plane could probably get by with 60-KOPS throughput and a 64, 000-bit memory for a complete three-axis autopilot, while a redun- dant autopilot for Category II landing in a business jet would need 96, 000 bits of memory and 150 KOPS in both channels. Probably the greatest computing capacity demand envisioned would be in the use of an integrated navigation/ autopilot system using strapdown inertial sensors; 300-KOPS throughput and 256, 000 bits of memory would be required. As the data in Section 5 show, both the basic computing logic and memory devices to meet these requirements in suitably small and potentially inexpensive units are now available. The final choice of hardware will probably be dictated by dollars /function rather than the level of technology itself.

with devices, -- Here the simpler airplane, equipped Input and display display devices less avionics, will need fewer and less complex input and C, the first computers having pilot Class than the high-level turbojet, For or perhaps, an engine con- and displays may well be in an R-Nav set inputs trol /fuel /status monitoring system. In either case, a simple keyboard input These re- plus warning light display would suffice.

and an alpha.-numeric quirements could be met satisfactorily with current keyboards and LED, LCD or incandescent displays. An added refinement might be a map display CRT display or one of the newer matrix for the R-Nav this would require a panels discussed later.

Class A turbojets have an instrument panel similar to a commercial air- recognized. In the 1980's improved displays is well liner, and the need for complex input devices.

these aircraft will have several computers requiring There are already space, power, and readability problems with inputs and with multi multi -use inputs coupled displays on sophisticated aircraft,_, and format displays will be welcome solutions, particularly since the high-level aircraft will not be so sensitive to the cost likely to accompany the first use of advanced input and display devices, RF electronics. -- RF electronics, although not nominally a computing element,is included here because the data in Table 5 show it to be an impor- tant cost factor and because the performance requirements for airborne re- ceivers, and to some degree transmitters, remain fairly constant regardless of the class of aircraft involved. Briefly, this is because bandwidths and " signal formats are dictated Largely by ground equipment and regulation rather than by aircraft type or mission. There will be differences in RF equipment, but they will be in the areas of reliability, maintainability, and service life. Reference 5 describes this situation and gives estimated costs for microwave landing system (MLS) receivers for both low-cost general The ratio of prices is less than aviation and air carrier use. 3:1 ($1, 750 is far lower than would be the case for an autopilot or versus $4, 500), this the primary flight displays where the ratio will be nearer 10:1. These differ- ing cost ratios indicate that there is a real need to develop true low-cost RF electronics and that the performance requirements for flight control hardware do vary considerably with the type of aircraft.

control Inertial sensors and servos. - Neither of these items are, '.

strictly speaking, part of avionic computers, but they are discussed here I _ s because better and cheaper stability augmentation systems and autopilots would greatly contribute to reducing pilot work load, particularly in IFR con- Reference 6 gives an excellent example of the benefits of stability ditions. ji augmentation.

The technical level of both inertial sensors and servos will vary consid- erably with the class of aircraft. Inertial sensors for general-aviation flight control and display purposes generally consist of angular displacement and In a Class C airplane, a rate threshold of 0.25 degree/second rate sensor and an attitude threshold of 0. 5 degree would be tolerable. These figures e correspond to those found in panel-mounted (for display) gyros, and in sev- eral current light-plane autopilots the gyro signals are taken from electrical pickoffs on panel instruments. On the other end of the scale, a Class A turbojet autopilot will need thresholds below 0. 1 degree/second for ra ge and 0. 25 degree for attitude., There will also be a need for the turbojet sensors 9-5 _._ have better dynamic performance (i. e., damping and natural frequency).

to Quantitatively the performance differs by a ratio of about 3. 5;1, but the cost will vary much more, probably at least 5;1. Some top-level Class A turbo- jets will carry INS using very precise gyros and accelerometers that are priced accordingly (approximately $50, 000 per set). In all cases, current inertial sensors, particularly gyros, have relatively high maintenance costs.

Current performance levels are satisfactory, but there is an obvious need to apply advanced technology to reduce purchase and maintenance costs.

Somewhat the same comments apply to control surface servos. Because of the low control sensitivity and low hinge moments typical of Class C air- planes, servos with low dynamic response and torque capability can be used.

Even so, there is a premium on low weight and power consumption that makes most industrial actuators unsuitable; and thus there is a need for semi- custom designs. A few light-plane autopilots have used penumatic servos, but with the development of solid-state power amplifiers the trend has been more to electrics.

Servos for Class A aircraft are usually similar but more advanced in all aspects of performance (e.g., response, resolution and torque). Two obstacles to the use of the generally higher-performance hydraulic servos are 1) the lack of powered surfaces, which makes the use of series servos difficult and 2) the expense and maintenance associated with aircraft hy- draulics. (A series servo is one that drives the control surface without causing any motion of the pilot s s controls. ) It should be noted that while general-aviation aircraft servos are not the most advanced available, they are performing satisfactorily in their current roles. However, the exploita- tion of advanced control techniques such as ride quality improvement and .

relaxed airframe stability will require improved performance.

Computer architecture and software. - The level of technology in these a areas will vary with the class of aircraft for many years because the more simple avionics suites for Class C aircraft will not have a critical need for the features that more advanced techniques offer,' The advanced techniques

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for architecture and software (as described in Section 5) consist of multiple processors cooperatively handling tasks too large for any one processor, and higher-order languages for creating the software. Digital electronics are now being used in low-cost avionics (e.g, in R-Nav and distance measuring equipment), but there is little need for complex intercommunication and no

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lack of computing capacity in available single microprocessor-based com- puters, As digital computers are applied to more functions such as flight

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and engine control, ` there maybe a need for the crossfeeding of some data, but this form of communication is relatively simple and does not involve the advanced techniques discussed in Section 5, One possible new function in which advanced computer architecture would be involved may be a central preflight and maintenance test system. As the separate avionics become

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digitized, a central checkout system becomes more feasible in principle, but is still subject to the practical considerations of standardization of sys- tem configurations and box interfaces as well as the level of field mainte- nance technology.

In regard to software, the desirability of higher-order languages (HOL , s) for production systems has been a subject of controversy for several years.

It is true that the use of a. HOL will reduce programming time, particularly when the programmer is not familiar with the processor being used and whin. the HOL compiler is efficiently and completely developed. What is sometimes not considered is that in avionics computers the I/O and I/O con- tr•ol often affect the timing of operations to the point that a HOL compiler for y a particular processor must be tailored to fit the specific application of that computer. To the extent that this is true it would create processor in a problems (or at least design restraints) for an avionics manufacturer who bought a processor and a HOL compiler to use in constructing his own com- puter, In general, it seems doubtful that for simiple digital appli^.atiorrs the HOL will be the better approach; however, as the digital capability (through- { put and memory) is increased, the HOL ,approach ;will _become more attrac- tive and may be desirable, particularly for the manufacturer who buys a a processor or computer to put into his hardware, s i -r `s

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Overall Avionic System Configuration. - The application of the tech- nologies discussed to general-aviation avionics will undoubtedly improve the performance and cost characteristics of the various subsystems, but the total potential benefit will not be realized unless the combined airframe/ avionics/pilot system is considered as a whole. If it is assumed that a Class B or C aircraft that is being flown by a pilot with less average training and experience should perform its mission with the same safety and depend- ability that is expected of a Class A aircraft, then it would appear that the avionic system effectiveness must really be better in the Class C aircraft than in the Class A aircraft. Admittedly, the airplane may be more forgiving and the landing category requirements lower, but the allowable cost and - complexity should also be lower. These considerations indicate that careful attention should be given to defining what the total system functional require- ments should be and what system configurations will most efficiently meet those requirements.

To obtain the desired improvements in safety, dependability, and cost within the projected aircraft and ATC environment will probably require significant innovation and sophistication (but not complexity) in the overall system design. Thus, the level of overall avionic system technology will need to be higher for all classes of general-aviation aircraft, i ;^

SECTION 5 ASSESSMENT OF CURRENT TECHNOLOGY This section presents a review of the current status and trends of many types of: Semiconductor Technology Component and Module Technology Computer System Architecture Technology P Y Software Technology Operator /Computer Interface Technology !

In general, all devices or techniques that are beyond the basic research stage and appear to be practical are reviewed.

For a variety of reasons some of these technologies may not be applicable to general-aviation, but are included for the sake of completeness.

Wherever it is clear whether or not the technology is applicable to general aviation, such a distinction is noted.

SEMICONDUCTOR TECHNOLOGY Circuit Technology a Advances in the semiconductor art over the last five years have been impressive. The basis for much of the recent progress in integrated circuit (IC) technology has been advances in photolithographic, device isolation, and ion-implantation processing schemes.

Semiconductor chips with 14, 000 transistors are available as off-the-shelf items, and microprocessors, hand- held calculators, and complex memory chips are readily available. -Research into methods, -beam ion newer such as electronand -beam implantation pat- tern generation, promise more improvement.

To prevent mask damage due to contact printing, efforts are also underway in projection printing and i i "near contact" printing. Feeding these developments is an array of tech- noligies remarkable for their diversity and ability to enhance circuit performance.

As shown in Figure 1, most of these technologies still employ silicon as the base material and are primarily of two basic types: bipolar and MOS.

The bipolar technologies can be broken down into at least 16 distinct circuit forms, based on three approaches to circuit construction: Epitaxial collector techniques D Triple diffusion techniques j • I Oxide-isolation techniques • Substrate material Silicon on Silicon substrate Basic device Bipolar MOS MOS type Primary 3D Ox,dc EPI device fdOSFET CCD isolation collector structures T 3 L EFL T?L PMOS Surface NMOS T2L ECL ECL NMOSBuried CMOs i TRL CML 12L CMOS j Circuit Forms T2L5 DIMOS ECL DMOS OTL VMOS RTL CIVIL I2L DCT2L Semiconductor Technologies Figure 1.

<a : f } The circuit design characteristics of each of these semiconductor technologies are summarized in Appendix A.

The most promising new developments for digital logic are presently being made in high-density, low-power bipolar logic, where a number of

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circuit forms are approaching the density levels of present-day MOS.

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MOS is being fabricated on both bulk silicon and on sapphire substrates.

While MOS has historically been classified as a very dense and low power but faster, approaching slow circuit form, new developments are making MOS

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today's most popular bipolar circuit forms. The recent emergence of charge- coupled devices will allow significant advances to be made in the areas of

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signal processing, imagery, and digital memories.

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To achieve good yields at high levels of integration in a given technology, three factors must be minimized:

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• Devise area • Device power Process complexity Figure 2 shows the gate delay and the required chip area for various Note that the high-speed bipolar tech- some of semiconductor technologies.

nologies can be fabricated with very small area consumption. Figure 3 shows the speed versus power relationship for a typical two-input gate for a number Most technologies widely available today are outside the of IC technologies., Process complexity is to some degree a function of the 10 picojoule line.

These are given in Table 6 number of mask steps and diffusions required.

along with the total number of process steps where known.

y TTL 5400 Schottky TTL MECL 10K — TABLE 6.—MEASURES OF PROCESS COMPLEXITY s Mask Process form Circuit Diffusions steps steps TTL ( low power) 7 4 60-65 TTL std 7 4 60-97 TTL Schottky 60-74 TTL LSI 7 4 PMOS metal gate 4 1 29 NMOS (Si gate) 5-7 3 23-34 NMOS (SOS) 5-7 3 30-40 CMOs 7 3 37 CMOs (SOS) 3 7 30-40 4 2 I2 L EFL 5 3 ECL (isoplanar) 6 3 3-4 1 VMOS CML 7 5 DCT 2 L 7 5 DMOS 2 i From this table it is apparent that the bipolar processes commonly in use today are significantly more complex than those used to fabricate MOS tech- nologies. More recent bipolar technologies, such as I 2 L, EFL, and isoplanar a i ECL, require fewer mask steps and diffusions, and thus promise higher yields on LSIC chips.

Guidelines for the Effective Application of LSIC 1 Until the early 1970's, the only implementation tools available for the s digital portion of a system consisted of IC's, which contained an averap of about four logic functions_ per package. As a result, the cost, size, weight, power and reliability of a system were almost a direct function of the number a i of login gates in the system. Thus, a heavy emphasis was placed on mini- mizing the number of gates. Because the logic complexity per package was so limited, the design of standard multi-usage devices was a simple task.

With LSIC, hundreds of logic functions can be contained in a single pack- j age. Designing functional elements of this complexity that have universal appeal is difficult. Nevertheless, during 1974 and 1975 many complex, but standard LSIC devices that perform significant digital computing functions have appeared, and it has become relatively easy to assemble efficient digital processors using standard LSIC's. The proper use of the new implementation provided by LSIC requires that new design approaches be used and that tools the system designer be fully aware of the :a: ivantages and limitations inherent -to LSIC implementation, a in LSIC. To define a system ideally suited designer must consider the following guidelines Replace analog and mechanical devises with digital circuitry • Increase the use of semiconductor memories • • Use functional and computational parallelism • Replace software by hardware • Increase system fault tolerance • Reduce system interconnections an implementation ap- Once the system has been properly defined and into unique LSI proach selected, the system must be properly partitioned tu: goals for proper systein partitioning are circuits. The • Maximize the use of standard'LSIC -`chips • Minimize the number of unique part types Minimize the total number of parts required • Maximize the gate-to -pin ratio of each part • • Ensure economically testable chips a

Appendix B discusses each of these guidelines in detail, and presents clarifying examples.

A major benefit of the use of digital rather than analog electronics is a much lower failure rate, thus an increase in safety and a decrease in mainte- currently operational digital avionics indicates an nance costs. Data on increase in mean time between failures (MTBF) of from 4 to 10 times that for similar analog units. This current digital equipment is built using MSIC.

count, future Because failure rate is roughly proportional to-piece -part equipment using LSIC (and thus fewer parts) will show even more improve- ment. Appendix C gives further data on LSIC reliability.

COMPONENT AND MODULE_ TECHNOLOGY Microcomputer Technology A microcomputer can be discussed on three distinguishable levels of a sophistication: the coalponent level, card level, and system level. In Figure 4 the microcomputer is divided into hardware and software and the various elements that constitute the three levels of sophistication. These elements and terms used in describing microcomputers are defined in the next pages : Microprocessor. The microprocessor is part of the lowest or com- ponent level and corresponds to a rudimentary central processing unit. In a fixed-instruction system, it contains the control logic and arithmetic logic sections, acid in a microprogrammed system, it contains an additional control memory section. The processor portion of a computer can be purchased in one of the following three forms, all which are sometimes referred to as a _microprocessors: • Functionally Partitioned Chip Sets - Separate LSIC chips or parts are provided for CPU, control, register banks, stacks, etc. An example of this type of unit is the Fairchild 9400 series of circuits.

i O ,0^

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^^ OK Microcomputer System level Software Hardware J Assembler utility an ua a k Card level Display Microprocessing 9 g programs simulator Control sPPP(eeS unit Buffers, Clock Mmnory 1/0 .croprocessor drivers f Component level ^ntro( Control Arithmetic Registers mrIt logic logic F Ii li Figure 4. Integration. Levels of a Microcomputer w • Bit Slice Partitioned Chip Sets - The circuitry for CPU, registers, control, etc. , is provided on a single chip or part; the part may provide a 2 to 8 bit "slice". These slices are then interconnected with 10 to 30 standard MSIC devices to form whole-word pro- cessors. An example of such an unit is the Intel 3000, which is a 2-bit slice unit that can be used to form a processor of any word length.

• Monolithic Processor -- All circuitry for the entire processor (all bits) is provided in a single part. An example is the Intel 8080, an 8-bit processor.

Microprocessin g unit. — The microprocessing unit is in the medium or card level and encompasses the entire group of circuits necessary to render the processing function. It includes, in addition to the microprocessor, the microprogram memory (in microprogrammable devices) or wired memory, the clock, the I/O devices, the buffer and drivers, and the interface circuit elements_ where and if required. It does not, however, include power supplies and enclosures. This level of sophistication corresponds to the naked mini- computer and is called a bare-bones microcomputer by some manufacturers.

conventional computer, the main If the microprocessor is used as a part of a an integral part of the operation of -frame memory is not included unless it is the microcomputer subsystem.

card or a number of The microprocessing unit may consist of -a single the circuit technology and the physical size of the printed cards, depending on cards used. The Honeywell HDC-301 and Teledyne TDY-52B are circuit typical examples of microprocessing units.

sophistication Microcomputer. — This is the highest or system level of system. The claims by some and comprises an entire operating computing microcomputer manufacturers that a microprocessor represents a "computer T on a chip' s and that as such its price is less than $100 is misleading. Such a chip is not a complete computer; it is only the central microprocessor.

To be functional, a complete microcomputer requires additional chips for read/write and read-only memory, 1/0 decoding, clock generator, address batch, control and interrupt logic, and data buffer, as well as the assembly and testing on a printed circuit board, power supplies, and cabinet. Further- The total price of a complete, more, the price of software has to be added.

usable microcomputer system is one to two orders of magnitude higher than that of the microprocessor chip or even of the microprocessor plus -a few memory and I/O chips. Thus a typical microcomputer, at least at present, will not cost $100, but at -least five to twenty times as much.

The expressions "microcomputer" and "microcomputer system" are used interchangeably. In the degree of sophistication, the microcomputer system corresponds roughly to the minicomputer system, although there are a number of differences mainly of price and performance between micro- computers and minicomputers. The differences between the two types of small computing systems are rapidly disappearing.

i k; The most complete survey of all forms of microprocessors currently available is Reference 7, "Microprocessor Directory and Microcomputer Systems- Directory", found in the November 20, 1975 issue of Electronic Design News Magazine.

Rather than summarize the state of the art in microcomputers and micro- processors as an independent item, these units are discussed in comparison to minicomputers. For the purposes of this report, we can define a mini- computer as a complete package consisting of processor, memory, and I/O circuits, which performs at a_moderate level of speed and functionality.

This loose definition is sufficient as the.. primary reason for including mini- computer technology in this technology assessment is to allow a direct comparison with the speeds and functionality of the more important micro- processor and microcomputer technology area. An excellent summary of available minicomputer is "The Auerback Computer Technology Report, Volume 110, Minicomputer Notebook." This document is available directly from Auerback and is updated on a monthly basis. A general survey and combination of data on minicomputers shows the typical machine to consist of the following characteristics: • Sixteen-bit word size for internal data paths and memory In contrast, microprocessors are typically 8-bit machines with a limited number of 4-bit and even fewer 16-bit machines available.

9 Memory address space of 64K words While some microprocessors are capable of addressing memories of this size, the number of internal operations and, therefore, time required to address a single word within the 64K is considerably longer for a microprocessor.

• On the order of 50 to 100 instruction types - In contrast, a micro- processor instruction set generally contains approximately 50 instructions. In addition, the functional capability of a single in- struction in a minicomputer is often equivalent to a number of microprocessor instructions, causing an even wider gap between the two.

• Typical short instruction time of 2 microseconds A short instruc- tion (store, add, etc. ) in a typical minicomputer will manipulate a, full 16-bit operand in 2 microseconds or less, A microprocessor (or microcomputer) typically requires 6 to 8 microseconds for 8-bit operands. Microprocessor instructions, ,which operate on 16-bit operands via multiplexing, typically require 20 microseconds for the same short instructions.

• Multiply and divide capability Virtually all available minicomputers provide a multiply and divide capability that operates in two's com- plement, signed format; typical times for these (fixed-point) opera- 3 tions are on the order of 10 microseconds. In contrast, current microprocessors seldom provide these more complex instructions a in the basic set. If included, the time for such operations may be on the order of 100 microseconds to 1000 microseconds, depending on whether the answer is to be generated as an 8-, 16-, or 32 -bit word.

• Floating-point capability A hardware floating-point capability is rarely provided in the basic minicomputer configuration provided by a manufacturer, although it is sometimes provided as an add-on item at additional cost. In contrast, the only way this capability can be obtained in a microprocessor is through special design by the user; th€: , e_are no directly available microprocessors that have vendor-provided floating-point capability.

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t ti t- Ni t d i d croprogramme ins r uc on se os L mi t L.L pu ers an micro processors use microprogramming for the basic instruction decod- ing operations. (Note: There is often confusion between a micro- processor and a microprogrammed machine; the terms refer, respectively, to a type of machine and a specific design/ implemen- tation technique for any machine. ) A microprocessor is not neces- sarily a microprogrammed machine. This is discussed in Appendix B.

• Input/ output capability , - Three types of output operation are of interest here: direct program control, blockl/O, and direct memory j access (DMA). ' For direct program control,, CPU processing time is required to fetch the I/O instructions and to fetch the data itself.

a In the case of block I/O, CPU processing time is spent fetching the The I/O instructions are fetched once per block. In con- data only.

trast, the CPU is involved in DMA only to the extent that it 'cannot access the memory while the operation is occurring; CPU and I/O accesses are generally interleaved. Minicomputers generally pro- vide both direct I/O ar:.d DMA, and sometimes the block form of I/O '.

operation. Microprocessors generally allow only direct I/O, although DMA is provided in a limited number of cases.

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• Vendor support - Software packages, documentation, packaged (hardware and software) interface options, and general user assist- ance is normally provided with a minicomputer. This type of vendor support is not as prevalent for microprocessors, but is available on some of the more widely used units.

0 Cost - The original equipment manufacture cost of a minimal (4K, a minicomputer is on the 16 -bit words of memory) configuration for order of $2K to $5K. Additional memory, CPU options, etc., can increase this cost considerably. The cost of a minimal micro- processor (no memory provided) is on the order of $50 to $500, depending on whether the processor is provided as parts for assem- bly by the user or as a complete, assembled PC card, A typical computer may contain 256 to 8000 8-bit words of memory; the cost for these units varies from $500 to $5000 depending upon packaging, control panels provided, etc.

Memory Technology a The main emphasis in memory technology has been towards the develop- ment of larger and faster memories. Today's memory devices can be classified into two basic categories: • Fast and relatively expensive electronically accessed mainmemory.

Slow and inexpensive electromechanically accessed peripheral • memory.

Because of size and low speed, electromechanically accessed memories a have had very limited use in airborne computers (none in real time applica- tions). For example, cassette tapes have been used to store programs or data for navigation and/or maintenance application. This use will continue but will not greatly influence the performance of future avionics; accordingly, data on movable memory devices is not included in the survey. r semi- Currently, two electronically accessed technologies predominate: These technologies are used to conductor storage and magnetic storage.

y These include: implement a number of memory forms.

Random access memory (fast read-write) • Read-only memory (ROM) • Electrically alterable (ROM) (fast read-slow write) j Block-oriented RAM (serial transfer of data blocks) • Content-addressable memory • forms are used The areas in the memory hierarchy where these memory and more detail on the devices are given in Appendix E.

In recent years there has been considerable effort in MOS to develop a While this development has not yet resulted in high-speed, nonvolatile RAM.

the desired speed, electrically alterable nonvolatile ROM's (MNOS)have been roduced. Such memory devices can be ve r y useful in remote commercially p y y p Y vehicles such as satellites,, where data alteration through ground intervention The development of a high-speed read/write semiconductor is desirable.

RAA(i that is nonvolatile would be of significant benefit and should be encouraged,.

As in semiconductor logic, the fastest semiconductor memories are fabricated in bipolar, the most complex in MOS. Access time of semicon- ductor memories today range from 20 to 500 nanoseconds and will be at least twice as fast for a given chip complexity in the 1980 time frame. While most semiconductor memories are random access in nature, block-oriented mem- ory chips are currently under development with access times in the micro- second region.

The most common technology fo^„/nd in memorysystems today is mag- The main problem with this technology, is the difficulty of netic storage, ;i interfacing with the semiconductor devices with which they must communicate.

Another shortcoming has been the need for electromechanical access when the memory capacity exceeds 10 7 bits, Recent developments in magnetic bubbles promise to extend the electronically accessed range to 10 9 bits.

The general characteristics of the most important nonmovable storage technologies are ranked with respect to avionics applicability in Table 7. At present, only magnetic and semiconductor technologies are used extensively in available, off-the-shelf memory. Each technology is summarized in Table 8 with respect to five quantifiable parameters. For semiconductor memories, a further breakdown is given between (volatile) RAM and programmable ROM.

Input/Output Technology Data bussing and multiplexing. Bussing and multiplexing techniques for interconnecting separate processors within a system and for connecting 1/0 terminals to processors are becoming popular in all types of real-time control systems. However, this particular area cannot be summarized with "typical" values, for two reasons: l 1. The technology is relatively new and has not matured to the point where a single approach is accepted and used within specific applications.

2. The details of a bussing system design will vary considerably depending upon the area of application, y i s i CHARACTERISTICS OF MAJOR NONMOVABLE STORAGE TABLE 7.- TECHNOLOGIES WITH APPLICABILITY OR POTENTIAL APPLICABILITY TO AVIONICS —4 4^ :4 Ira Cd .,4 (U bn .1.4 Storage W 0 0 a) 0 Cd ^2. 0 technology U) U Do P., Semiconductor L R/W H H Bipolar VH H M L L R/W H MOS H M VL L R/W H C-Mos H M L L R/W H SOS/MOS Magnetic NO M L H M H Core L NO M H H M Plated wire Legend: VH - Very high H - High M - Medium L - Low VL - Very low R/W - Read/write A C; T TABLE 8 0 CHARACTERISTICS OF MAGNETIC AND SEMICONDUCTOR MEMORY TECHNOLOGIES Technology Paramrtcr Magnetic Plated wire Nonvolatile Access time: 100-1000 nsec Density: 103 -104 bits/cm2 (a) Subsystem cost : 2.1¢/bit Power consumption; 500 uW/bit operating/0 uW/bit standby Capacity: 4K bits and up Core Nonvolatile Access time: 100-10000 nsec Density: 10 3 -04 bits/crn2 Subsystem cost(a) : 4.0¢/bit Power consumption: 600 uW/bit operating/0 uW/bit standby Capacity: 4K bits and up Semiconductor Bipolar Access time: 110-100 nsec D(-:1 -:r .: 104 -10 5 bits/cm2 i Sul, ,.m cost(a) r 2. 60/bit Power consumption: 1000 uW/bit operating/50 uW/bit standby • Read/write (RAM) - volatile - capacity: 1K bits/chip • Read only - nonvolatile 8K kits/chip - -capacity: • Programmable read only - nonvolatile - capacity: 4K bits/chip MOS_ Access time: 80-2000 nsec` Density: 104 -105 bits/cm2 Subsystem cost (a) : 10/bit Power consumption: 300 uW/bit operating/ 10 uW/bit standby • Bead/write (RAM) - volatile - capacity: 16K bits/chip • Read only - nonvolatile - capacity: 48K bits/chip • Programmable read only - nonvolatile - capacity: 4K bits/chip - | / ! i | ] \ / i . , ' ^ ^ The points of variance between systems are: ` T - The physical or geometric pattern used for inter- connection ^n m Control Mechanism for Bus - This may range from a single-point ^ r (central) control eobezue to o} stezoe in which all terminals (processors) may control the bus at different points in tizoa, .

^ ` m Communication Mechanism - There are a large number of options -| available regarding codi ng , modulation, and data tzanaz^ieedoo _ ^ ` techniques.

^ | m Speed ~ This will vary with the transmission media (twisted pair, oOaoc cable, etc, `^ distance batvveau terminals and/or processors,`i number of terminals (drops), etc, | Data Format - This deals with issues such as bit-serial versus word-parallel data transnAssion, inclusion of definitive information for various bus management functions, organization of the data into specific messages, etc.

Error-Control Techniques - This may vary depending upon whether error detection is important, whether bus recovery is desired or j necessary upon occurrence, etc.

To indicate the extent of variance poss i ble, two existing bus designs are summarized in Table 9.

With the introduction of LSIC-implemented bus terminals and the use of (wide-band) fiber optic transmission media, it is sufficient tosay that in a given application, there is an unlimited range of alternatives in bussing.

' The initial general- aviation data ^ redundant busses or a dual-ring bus structure with zone disconnects such d .

em c an p er for m it e o f open that ----'-- syst —^ - sp - ' shorts to groun ` ^ 1^ `47 Intrasystem Bus STD 1553A Bus AADC Characteristics MIL Topology Linear, all terminals connect Linear, 3 feet maximum length to a single global bus, 300 feet maximum length Control mechanism Centralized with polling of all Decentralized, round-robin passing terminals for message (bus of control I usage)requests Communication Phase modulation, manchester Non-return to zero (NRZ), request/ mechanism (biphase) coding acknowledge Speed 1-megabit data rate, 2-megabit 150 nsec per 32-bit word bandwidth 32-bit data word transmitted in Data format 20-bit basic word with 16 bits of data,, transmitted bit serially parallel, Error control Parityover 16-bit data Parity over 32-bit word techniques ,t t i Handling the aircraft, engine, and flight control communications digital multiplexing to central p rocessors could reduce the numh connects and improve system noise immunity by performing analog to digital (A/D) conversion at remote analog sensor locations. A complete survey of bussing and multiplexing is beyond the scope of the report. Reference 8 gives more information.

Some electronic systems and components manufacturers indicate that they expect automotive electronics to develop in an orderly progression of discrete, combinational and central proces; sor- data bus phases over the next ten years. The safety aspects to be perfected before use of a central processor-data bus in general- aviation avionics will undoubtedly require additional time. Therefore, data bus application in general aviation is unlikely prior to 1990.

Interface components and modules. — Because natural parameters such as temperature, displacement, anci pressure are analog and because the more advanced methods of data handling and computation are digital, conver- sion between digital is fundamental analog and quantities a operation in computing and control systems.

TI -lus analog-to- digital (A/D) or digital--to analog (D/A) converters are found at all interfaces between sensors of phys- ical quantities and digital computer and output devices.

Digital 1/0 function modules, analog 1/0 function modules, and 1/0 components may provide some of the same functions performed by the con- verters. Also, digital transducers, which are another type of 1/0 module, are discussed in this su7bsection. More information on these 1/0 modules and components is included in Appendix F.

Converters: Despite the widespread use of A/D and D/A conN.-erters, there is little staildardization. and there are no product lines that dominate the converter business sufficiently to provide a practical basis for standardi- zation.

These difficulties are compounded by the diversity in nomenclature and error definition. Changing manufacturing technology, developin-ent of new semiconductor components, and varied application requirements, when combined with minimal standardization, lead to a growing variety of available converters. Furthermore, as the conversion process varies, similarly specified units may exhibit subtle but important differences in behavior.

As a result, choosing the best converter for a specific application requires careful consideration. Converter selection criteria are discussed in detail in Appendix F.

Because A/D. converters are essentially interface devices, the basic conversion circuitry must be adapted to suit different applications. Adapta- tion .includes adding registers, buffers, digital clock, and reference voltage; these are frequently provided external to the converter. The exact definition of what is included in the converter module obviously has an important impact on price and makes it difficult to compare competitive models, Hybrid D/A and A/D converters are being greatly integrated such that units requiring no outboarded devices for operation are becoming more common. Monolithic data converters having 8- or 10-bit resolution are now readily available. However, most converters require one or more associated external components.

Development of complete monolithic convert'Ers, both D/A and A/D, having 12-bit resolution is not far off, However, there is now a whole array of 10- and 12-bit monolithic analog and digital building blocks available for making either A/D or D/A conversions,'' They include successive-approxi- mation registers, quad switches, and precision current sources.

The epoxy-encapsulated variety of modular converters continue to offer the ultimate in performance, For example, conversion time for °a 12-bit i modular A/D converter is now down to 2 microseconds. Also, complete data acquisition systems have become available in modular form. These units low-profile packages smaller than a human hand are multiple-channel systems, containing A /D converters, sample-and-hold circuits, multiplexers, and sometimes even programmable logic, z l For pricing comparison, D/A converters may be grouped according to resolution,with performance parameters such as accuracy generally corres- ponding with resolution. At the lowest end are 4- and 6-bit converters for use in low-accuracy programming applications and in digital communications; these sell typically for about $20 per device. Converters having 8- and 10- i bit resolution are essentially similar except for the number of bits, with a relatively small price differential for the larger number of bits. The 12-bit converter is the most accurate of the readily available production types and uses precise analog components, which are nevertheless inexpensive and widely available, It is no coincidence that 12 bits corresponds to the accu- racy limit of most analog instruments and control systems. Digital to analog converters in the 8- to 12-bit range typically cost $10 to $20 per bit; a good 12-bit decoder costs about $200.

Converters having 13- to 16-bit accuracies are used. in very high- accuracy or wide dynamic-range applications Their cost can easily be many times that of the 12-bit converter, running $10 to $ 50 and more per bit. At this resolution level, every additional bit adds substantially to cost. Of course, the user of high-resolution devices must be very concerned with I long-term stability, susceptibility to noise, response or settling time, trimming adjustments,- and similar factors that must; be controlled to ensure that the specified accuracy is actually actLieved s High-speed converters of 15 or more bits represent state-of-the-art performance and are consequently very expensive. Because it is expensive

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to even test such units, there is skepticism about long-term performance.'

C Where speeds above about 1 MHz are required, prices can soar to many times those of the low-frequency equivalents with the highest speed units costing twenty times more than lower speed units.

Technological advances in data converters have been snowballing for several years particularly for hybrid and monolithic devices. There are now many more of all types from which to choose (Table 10). The biggest factor in comparing digital converter prices is assuring a uniform basis for J vt TABLE 10, A SURVEY OF DATA CONVERTERS k•1 C1 Digital-to-analog converters Analog-to-digital converters (a) Resolution, Technology binary its Y Approximate Approximate Conversion small quantity smal! quantity Notes dotes Settling time price, dollars time price, dollars (b) (b) 8 All units require external 10 approx. 18 Ps approx. All complete 12 approx.

85 as - 1.5 p s reference source and operational amplifier 25 - 100 40 ps approx. All require external 75 approx.

Monolithic LO 250 ns - 1.5 Some complete; others need us clock and comparator reference source and /or operational amplifier 35 approx.

12 500 ns approx. All require external - - reference source and operational ampimet• 8 All complete 10 - 50 1 ps - 60us All complete 60 - 195 10 p5 - 23 us 10 23"s approx. All complete 60 approx. As low as 2 u Some complete; others 35 - 110 need external register 25 - 275 12 Sus — 23us Most complete; a few need 30 - L50 Bus - 30ps Most complete; a few hybrid external operational need external refer- once source and/or amplifier register and clock, 125 - 130 Ups - 50 p s Integrating types only 75 - 250 16 LOOPS approx. All complete Both current- and 10 - 255 800 as - 350 p s All complete 60 - 475 8 25 ns - 20 ps voltage-oulpnt types 20 - 200 Lus - 300 ps All complete 80 - 485 10 25 ns - Sus Ruth current- and voltage-output types 35 - 180 All complete 115 - 585 Modular 12 50 ns - 20us Buth current-.and 2us - 350ps voltage-output types Both current- and 250 - 850 lops - 5Ous All complete 200 - 700 14 lus - 250us voltage-output types 1,400 - 16 750 ns - 250us Both current- and L00 - 1,500 Sus - 400us All complete 3,000 voRage-outputtvpzs b a Por commercial-grade products.

Principally successive-approximation types.

low -cost con- comparison. It is easy to make the specification sheet of a verter appear superficially equivalent to that of a more costly unit; factors i relating to stability, noise sensitivity, and other important parameters may be omitted or inadequately defined. Completeness of the converters, with regard to system interfacing, may vary substantially among various choices such that the lowest cost device ultimately becomes the most expensive when all extra interfacing is included.. Further, tieing in the interfacing can re- quire costly debugging due to subtle incompatibilities of hardware and prob- lems relating to system layout and wiring. In general, when performance requirements_ are high and quantities moderate, shopping for price is usually a poor decision.

G i Because there is no industry-wide standardization, second sourcing can be a problem. This emphasizes the importance of choosing a reliable matiu- facturer,. Sometimes a system can be designed at slight extra cost to accept either of two nonidentical. converters with little or no modification.

Digital transducers ; Digital transducers are defined as devices in which the parameter to be measured is subdivided into increments by a special_' quantized transducer, and conversion to digital form is accomplished by determining the number of increments contained in a particular motion or - change of state. Digital transducers are comprised of two primary subtypes: 1) devices in--which successive increments of position are indistinguishable and must be counted, and 2) devices in which successive incremental positions are coded (numbered) such that the number corresponding to any position can be determined directly.

The absolute encoder has a distinct code for every position and, con- sequently, has previously been preferred for its inherent reliability. The recent trends; toward use of solid-state light-emitting diodes (LED's) and integrated digital circuitry in the encoder package has resulted in an improve- ment in the reliability of the formerly less popular incremental encoders to the point where they are challenging absolute encoders for angular position and rotational speed measurements. a With an incremental encoder, only one track is needed,; in principle, to obtain an indication of position as compared to an absolute encoder with multiple tracks (number of tracks dictated by the resolution required: 8 tracks for 2 8,10 for 2 10 , etc, ). The incremental encoder is considerably less expensive, and the continuing improvements in [C's, solid-state LIsD's, and electronic processing will -serve primarily to increase the application of incremental encoders. Reference 9 discusses a number of other changes affecting digital encoders.

Digital transducers for the primary parameters of temperature, presfi Lire, position, and rate are setting the pace for the development of inexpen- sive control systems, Hybrid IC's, which appear to male the best and cheapest pressure transducers for the automotive market, are under develop nzent b y several large semiconductor vendors.

Hybrid IC pressure transducers will include the _necessary transducing elements; diaphragm with its constraint and vaccuum reference cell, piezo- resistive sensor bridge, signal conditioner with temperature compensation j and bridge balance, and signal amplifier, A typical pressure transducer con- 115 mil 'chip. The pressure diaphram occupies 90 x 65 mils, sists of a 165 x leaving enough for temperature-compensating diodes, bridge-balancing area resistors, and a zener regulator for the bridge power supply. In is final form, the l:.ybrid transducer consists of a ceramic substrate with laser- trimmed, thick-film resistors, one or two operational amplifier chips, and the transducer chip,_ Diaphrain 'dimensions set the transducer is nominal pressure range, tiwhich is selected to stress the silicon to less than 15 percent of its, rupture points The diaphram can actually operate double range and will survive triple-range excursions without offset or degradation to the transducer chip, In another of the many possible applications, IC pressure transducers -will meet the needs for electronic fuel injection systems. These systems must measure pressures with accuracy over a 1 to 15 psi range while operating in ambient temperatures of -40 to 200°F.

Honeywell has had a digital pressure transducer under development that may be applied to automotive as well as aviation uses. The details of its operation are typical of the new IC digital transducers. The pressure sensor developed by Honeywell for application to digital systems is shown in Fig- ure 5, and a block diagram of the transducer is shown in Figure 6.

The transducer consists of a diaphragm cut from a single crystal of silicon (semiconductor material) which has resistors diffused into it. The diaphragm is housed in a small cylinder. One side of the diaphragm is evacuated, the other side is exposed to ambient pressure. Ambient pressure causes the diaphragm to flex, producing a resistance change (AR) propor- tional to strain (which is proportional to pressure).

The resistance change (AR) is a function of pressure, resistance, and.

temperature. Strain can produce resistance changes of up to 10 percent of nominal resistance, and AR is approximately proportional to pressure,- Most temperature effects are canceled out due to sensor resistor - bridge circuit mechanization.

{ Signal conditioning circuitry in the sensor provides means for converting ^R to a digital form, provides sensor, temperature information in digital form, and provides constants for characterizing the sensor to provide ^ Tt

i

corrected for temperature and diaphragm nonlinearities.

The sensor signal output is transmitted to a'digital processor that con- verts the three digital signals to pressure by solving polynomial equations,, rn Shrink tubing Dual-redundant leads for pinch-off protection Ball bond to diffused circuit elements Weld pinch-off Vacuum chamber Resistance weld Silicon cup Seven Leads Bond Silicon backpla:te Weld Evacuation pipe i Ceramic stud Three manifold Machined Kovar mounting holes manifold Threaded to receive P. or PT pressure fitting Silicon diaphragm Figure., 5. - II()«evweil Solid-Stole Pressure Transducer a.

Q .

U FS 011.d-state transducer U a I PS°t I Time Pressure pulse ---^ - input to probe RT RT+AR A/^ Pressure data Iconversion IRR RR - AR Transducer — I electronics ' Constants I Constants I board A/D conversion Temperature I!

data Temperature _ - — — — — — — — — -- voltage _,To central Signal conditioning processor Trans uCn9 Probe z COMPUTER SYSTEM ARCHITECTURE TECHNOLOGY General Considerations Rapid advances in semiconductor technology have recently spawned the microprocessor --- the general-purpose, stored-program processor based on a small number of LSI circuits (ref, 10). As logic elements, these processors provide unprecedented power and flexibility to designers, and will precipitate many dramatic product developments. From a computer perspective, the current microprocessors are somewhat primitive, but they clearly presage the evolution of much more capable ones.

Thus far, it has been computer architecture which has influenced _micr o- processors. They first emerged in the form of small, special-purpose calculators and have steadily evolved in the direction of general- purpose computers. Now, however, that relationship is becoming less one- sided; microprocessors are having a growing effect on the organization of larger computer systems. The principal impact is an accelerating trend toward distributed function architectures, in which a larger machine is structured from a multiplicity of 'smaller ones (ref, 11). Bistorically, high J processor costs have restricted this approach to those few applications that demanded (and could afford) the potential reliability and performance advan- tages, Because processors are no longer the limiting resource, distributed a computers are becoming increasingly feasible on a wider scale, i The techniques for designing distributed computers are as yet in their infancy because the motivation to do .so has only recentl y developed. Perhaps the most significant issues are how the computational load is to be partitioned j across the processors, how the resulting processes are to intercommunicate, and ,what sort of processor interconnection structure i c, needed to support this j communication, 1 I ^ The way in which the processors are attached to each other is largely dictated by the interprocess communication requirements, which in turn reflect the process partitioning and assignment, Other major issues, which are discussed in detail in Appendix G, are; • interconnection transfer strategies • transfer control methods • transfer path structure system topologies • cost-modularity s place-modularity connection flexibility • failure-effect • • failure-reconfiguration • logical complexity bottlenecking It is clear that the three principal distributed processing issues of 1 process partitioning and assignment, interprocess communication, and pro- cessor interconnection are intricately related, and must be traded off for specific applications. Some unnecessary and distracting separations of them have traditionally been based on a dichotomy between hardware and software implementations of various functions (ref. 12) Certain aspects of contempor- ary distributed processing approaches suggest that conventional hardware/ software interfaces should be re-evaluated; advances in hardware components and implementation techniques are making it possible to combine flexibility; i with low cost and high performance.

Distrhuted computers can be generally categorized according to the way in which the processing is partitioned among the processors, Processors r F ^ 1 function as: purpose components of a larger processor, may special- cess- dedicated ancillary processors supporting the main (i. e, , central) pro or(s), or as multiple main processors. Any or all of the levels in this hierarchy may appear, in a particular distributed computer, as illustrated in Figure '7, Processor 5ubprocessors Microprocessors may themselves be special-purpose components of a larger processor, performing functions previously clone by hard-wired logic or software, or not done at a11.

A function that must occur in all processors is instruction and operand preparation; selecting the next instruction to be executed, forming its effective address, obtaining it from memory, forming the effective address- This may involve dealing with such es of its operands, and accessing there, issues as protection and sharing; address translation; memory and bus con- Frequently, these operations tention, arbitration, and allocation; faults; etc, could be overlapped with the execution of previously prepared instruction The extent to which this form of pipe- on previously prepared operands.

lining can improve the computer's performance depends on such factors as Usuall y exactly= how it is implemented and locality aspects of the software.

the look-ahead mechanism is part of the processor (ref, 13), but may instead be part of the memory (as considered. later).

The incorporation of a dedicated pr(-c:essing component to perform odu- certain arithmetic functions within a main processor may offer bott If the functions are optional, larity and performance advantages (ref, 14) placing them in this separate processor may provide a very clean interface Rather lengthy computations (such as brie string to the rest of the machine.

i or trigonometric operations) can sometimes be carried out by a separate processor in parallel -with other functions.

^.

Main processor i Main processor i Decimal processor Floating Bus Bus point interface interface processor processor processor Lookahead e processor Q Q Memory - hrj. 1 (.. management 1-0 processor & OH Global bus I/O processor Communications — jD processor q q It — ^ Channel \^ / Line Buffer processor protocol manager ^. Channel processor processor processor i Deutcr- Device controller controller J processor processor Modem Pro,, _.r f0 Vic \ ^^^1 ^ ♦ /0 e Processor Processor l Commuiication L+nes a Distributed Computer Figure 7. — Examples of Micro ,rocessor-s in a { t t 1 h 1 Occasionally very special-purpose tasks need to be performed, such as graphics, signal processing, etc. These may call for either internal processor components as described, or external ancillary processors.

Dedicated Ancillary Processors { Microprocessors can be very effective in the capacity of dedicated function processors supporting the main processor(s). Input/output process- j ors have been a feature of larger computers for some time (ref, 15) and are becoming%commonplace on smaller ones as well. Microprocessors bring the sarne decentralization advantage to I/O processors as to entire computers; a the I/O processor can itself be decomposed into individual channels, each controlled by its own microprocessor (ref. 16). Autonomous channels not only have potentially higher bandwidth, their increased intelligence facilitates the performance of functions such as code and format conversions; error and exceptional condition handling; buffer and queue management; device address transl.M.,ion; protection; routing and device selection; seeking, searching, label checking, etc. Microprocessors are also seeingincreased use in 1/0 device controllers to handle complex interface functions (such as for disks f ref, 17 1) and to eliminate specialized hard-wired controllers (ref. 18 and 19).

At the bottom level of this hierarchy, microprocessors are also appearing in the I/O devices themselves.

A special type of I/O processor worth noting is one which is used for communications applications. Microprocessors are becoming well suited for handling the line protocols, data compression, routing, monitoring, 20).

testing, formatting, etc. (ref.

a # Memory_ continues to be one of the major cost factors in a computer, so its 'efficient management is an opportunity for employing microproces40r•s, Memory management includes address translation, protection, segment/page replacement, garbage collection, etc. It may also include instruction and operand preparation, as discussed earlier. Associating this function with z r j ^ 4 i I ^ t the memory rather than the processor, has potential advantages in certain multiprocessor configurations, i, e, , use of the bus connecting the processors with the memories can be reduced from four cycles (instruction address, instruction, operand address, operand) to one (operation code and operand), thus reducing bus contention and raising throughput (ref, 21). The pro- grammable capabilities of a microprocessor are often useful in conventional memory management tasks, but are virtually indispens:1ble for this ''distrib- uted fetch" concept. Carrying this idea one step further results in a multi computer, one of the mi k1tiple main processor cases considered next, Multiple Main Processors Over the past Hecade, parallel and associative processors have re- ceived. considerable attention in the literature, but high hardware costs have restricted actual construction and experimentation. The advent of the microprocessor has revitalized interest in these architectures (ref, 22) as now it is becoming economically feasible to build them. While parallel and associative processors have rather limited application, they are good examples of the trend toward dedicated and special-purpose rnachines which ` a has been precipitated to large extent by microprocessors,` The more general-purpose multiprocessor and multicomputer (in which processors are interconnected by I/O channels rather than a common memory [ref, 21) ]-architectures are also benefiting from decreasing pro- cessor costs; it has been difficult to find instances of these organizations having greather than three processors until recently. The necessity of maximizing processor use has led to complex multi programming e-,ecutive software. Even if one could afford multiple processors, using them efficient- ly usually required so much overhead that system performance rarely improved as expected and often even declined when additional processors Now, when the processor portion of system cost is heavily were added.

outweighed by the software and configuration portions, the economic 'incen- tive to optimize processor use is diminishing. By emplo ying suitable intercommunication mechanisms for both hardware and software, distributed architecture can be devised which permit easy incremental changes in processing power using standard, low-cost modules.

One consequence of this modularity is the potential for overcoming the normal price/performance discontinuities between smaller and larger com- puters. Within a general-performance class of machines (such as micro- computers or minicomputers), an increment in price buys a proportional increment in performance (whether a consequence of technology or marketing factors). Ilowever, when the desired increment in performance crosses a boundary between classes of machines (e, g, from minicomputers to ''full size" data processing computers), there is generally a large step in price; to get ten times better performance than a particular machine may cost one thousand times the price of that machine. On the other hand, it may be poss- ible to interconnect fifteen copies of that machine at perhaps thirty times its price (allowing for the interconnection cost) to achieve the desired perform- ance. Thus, the availability of ver y inexpensive though limited-capability rnicroprocessors should be of interest, even to many of those who need higher performance than just one microprocessor can supply.

The microprocessor possesses Iwo important features that gainfully eN—Joit LSI technology. Ii takes a minimum rniml)e r of chips i o conf'igLl r e a dedicated function. Also, it;permits the easy formation (,I' microprocessor - networks, i a Th.cre are many systems now using a single processor/memory, approach that are r•ipc for a multiprocessor application, -Such systems inc°ltude point- of-sale terminals, electronic automobile cont rol and general-aviation avionics, a i If the multiprocessor approach is used, unique controllers, sensors, and long wire runs to the CPU for each input could be replaced by a more modular arrangement. The heavy load on a single CPU could be replaced by light loads on multiple CPU's. Software would be simplified in some cases,and shorter runs at the lower data-transfer rates used purely for the exchange of processed data could be substituted.

Current efforts, in the direction of multiple main processors include relatively unconventional architectures (ref. 24 and 25), as well as more traditional ones (ref, 26). It should be noted that distributed computers as considered here differ considerably from computer networks, both in per spective (building one larger, computer from .a number of smaller ones, versus loa and resource sharing among a number of individual computers) and in environment (electrically and geographically short interconnections, versus electrically long and geographically long [ref. 27 _] or short [ref. 28 interconnections).

While microprocessors are expanding the possibilities in computer , sys- tem architecture, at the same time they are imposing some limitations; the primary limitation being that the processor designs will be determined by the semiconductor industry and will less frequently be subject to the design influence of the computer system architect.

SOFTWARE TECHNOLOGY The software technology areas relevant to future avionic systems requirements are modularity, higher-order languages (HOL), software verification, validation, and support, and avionic software libraries. The prime bene=t of progress in these areas is reduced software development costs and increased reliability. A summary of software technology is given here, and Appendix II reviews this area in depth.

r.

The concept of software modularity relates to work division and function- al software building blocks. Implementing modularity begins with partitioning a system into well defined subtasks. Each subtask results in a program module with well defined inputs and outputs that can be developed, debugged, and validated independently of each other. For example, interrupt routines and input/output service routines are typical executive function modules.

Manageable work assignments can then be made for each module.

Software systems are usually defined with a functional hierarchy Hi gh- level program modules can be divided into submodules consistent with this hierarchy; conversely, the submodules at lower levels can be considered as building blocks for the higher levels. The levels extend from the machine object code level Go IIOL source level. Adherence to modularity can greatly reduce the software development effort, especially at the debug a.zd validation stage. It must be done carefully, however, so as not to introduce functional rigidity in an en N iron;nent with changing requirements.

Software functional modularity is strongly influenced by the level of the programming language used. In a high-level language, a compiler is used to transform each source statement into one of many machine-level object code instructions; Also, high-level language symbols have more complex attri- butes than the simple values associated with low-level language symbols.

This the use of high-level languages guides program structure;, forces discipline, and facilitates modularity.

There are several general requirements used to select a particular TIOL, j a The language should be commonly- used to facilitate the training of pro a grammers, transferability of code, and the availability of useful soft-",are library functions. The language should be consistent, general, and easily understood; it should also be efficient in terms of writing speed, -compile speed, and memory requirements/execution speed of the compiled code, Y {

t

types of operations The specific requirements of avionics include several and functions that must be represented in the language. These include

t

mathematical functions, conversions, sorting, list processing, data packing and unpacking, low-level I/O, and digital communications control.

Some of the major HOL candidates for avionics applications include FORTRAN, JOVIAL(J3/J73_), PL/I, SPL, and CMS-2. Each of these languages has a particular set of advantages and disadvantages in avionics applications. The choice between theirs should be guided not only by the general language requirements and specific avionics requirements, but also the new concepts that are developing in higher-order languages. These include the relationsiAp between data and program structure, the concept of an extendable language ., source level modularity, and structured programm-

t

ing.

The use of HOL's_ can greatly facilitate software verification and validation.

select test cases, evaluate execution for testing software is: The procedure and The use of HOL.'s, modularity, results, and estimate correctness, structured programming techniques reduces the quantity of errors and isolates those that remain to a functional area.

An additional path for solving some of the current software problems is This "bottom-up'' to provide hardware support to various software functions, approach provides clean interfaces, enforced. standards, faster execution, and -a lower level of software detail; however, it results in a loss of flees- The prime bility and increased size, weight, power and component count, areas for using this approach are executive and communications functions.

An avionicssoftware library can greatly reduce recurring software _ The software modules must be developed to span the levels from =.

costs, an avionics function such as navigation or air data processing, through subfunctions such as flight control, to the subroutine level such as mathe- matical or I/O routines, The types of functions that are most useful in library li form are those that are not highly applicatio-a dependent such as LORAN and inertial navigation functions, which can be mouularized for inclusion in an avionics software library.

In practical applications, the cost effectiveness of higher-order languages d (HOL's) for production systems has been a subject of controversy for several It is true that the use of a HOL will reduce programming time, par- yeras.

ticularly when the programmer is not familiar with the processor being used ""hat is and when the IIOL compiler is efficiently and completely developed.

sometimes not considered is that in avionics computers, the I/O and 1/0 con- trol often affect the timing of operations vo the point that a TIOL compiler for a particular processor must be tailored to fit the specific application of that To the extent that this is true, it would create processor in a computer.

problems (or at Least design restraints) for an avionics manufacturer who bought a processor and a TIOL compiler to use it in constructing his own coni- In general, it seems doubtful that for simple digital applications the puter.

HOL will he the better approach; however, as the digital capability° (through- .

put and memory ) is increased, the HOL approach will became moiro attrac- tive and may be desirable, particularl y- for the manufacturer who bu;vs a It is also true thUt a TIOL processor or computer to put into his hardware.

is quite useful in s y stem development when it is desirable to be able to make There ma,, be situations when it frequent changes to software programs.

would be advantageous to use the HOL in development and shift to assti.mhl-,, language for programming the final production hardware.

OPERATOR /COMPliTER I- T`ERFACE TECH-NOT,0M Digital techniques are changing military and commer i cial aircraft crew i station layout concepts,' The evolution of digital techniques is following the trends in ii7formation processing and interactivemarl/machine interfaccis, which are t?.lcing place in computer graphic terminals, as well as the results

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of intensive experimental psychological studies of the man-machine relation- ships, The general-aviation cockpit design requirements that are tailored to smaller, cheaper and lighter aircraft appear in direct conflici with the complex advanced developments, but an obvious solution to the problem of making the most efficient use of available cockpit space is the appropriate integration of selectable controls and displays. For example, fuel quantify could be stored but not displayed until 1 •equested_or until 1/4 full is reached.

If desirable, rate of consumption (lbs/hr) could be computed, monitored, and warnings issued if the rate becomes too high.

If one excludes those controls needed for emergency and safety of flight purposes, there remains a vast number of independent avionics control and display functions that are used comparatively little and yet continue to occupy valuable cockpit space. A more efficient use of available space could be achieved by the application of programmable controls and displays, .

which can he quickly reconfigured to suit the modes and functions desired at some specific time.

Computer Input Technology Innumerable alternate completer input methods have been developed within the computer industry. Several types that might possible be useful in digital avionics are discussed in this subsection, Graphic data entry. — Graphic data entry offers mans- intriguing possi- bilities for simple :interactive cornmunication ^ itlr a central computing systcrn, The hardware developed to date is primarily for laboratory and commercial use, and no avionics applications of this technique have been defined._ Be- cause graphic data entry is based on use of a relatively pow°: ful'central com- puter and very specialized hardware for data entry and display, application in general aviation does not appear to be likely in the near future.

G0 a ^ f r Hard-copy entry, — The commonly used hard-copy entry methods in- elude punched cards, paper tahc, magnetic tape, and magnetic cards, and their continued use for digital avionics appears likely, The reprogramming capability offered by small, magnetically coded cards such as those used with the Ile wlett-Packard HP-65 calculators appears to be a technique that may readily be expanded and improved for in-flight general-aviation avionics applications. The low cost and small size of present digital cassettes will undoubtedly be further improved, resulting in widespread application of this form of magnetic tape input for preflight test programs, as well as loading of -Nav, etc.

operating programs, and bulk data for R The U. S, Air horce has recently announced the develop Voice entry.

ment of a voice-input code identifier that enables a computer to recognize spoken digits and certain command words. Several other similar develop- ments have also been reported in the literature (ref, 29). The primary disadvantage of these systems is the relatively high cost associated with the very limited number of recognizable inputs. Also, regional accents create is complex, needs significarnt problems. The equipment developed to date extensive memory capability, and does not yet appear to he near a production appear that even high-cost voice-entr y devices status. Therefore, it sloes not will be available in any quantity for the 5 to 10 years. Thus, there :s little likelihood that, quch equipment will be available for general aviat or use in the 1980'sa

i

The most common application of keyboard entry to Keyboard entry-, digital systems has been the use of teletype consoles, ilTost avionics appli- cations do not require the full alphabetic set of characters, and consequentll , the number of keys may be reduced. Keyboard configurations may range from a fixed keyboard set to multiple projected legend push-button switches and displays, programmable keyboard and displays, and to fully interactive ke:, Joards, a i With the advent of multiple projected legend push-button switches and displays, a new degree of flexibility and design freedom has been achieved.

A rush-button switch and display can be used for more than one function; i, e., they may be time-and function-shared. These devices„ however, have complex designs and require some changes if a word, symbol, or letter of g' the total repertoire is to be changed. In addition, if multiple legends or annotations to the legends are to be displayed simultaneously, the overall flexibility (multiple functions- and modes) would be reduced, as the total number of messages is fixed.

With the programmable keyboard and display, the limitations and proh lems encountered with multiple projected legend pushbuttons and displays can be eliminated. The aumber_of different legends that can be displayed on a given push button or display will not be a function of hardware complexity or size, although the number of alphanumeric characters and/or symbols that can be displayed at a given time will be, of course, Limited, by the push button or display size. The total repertoire, however, becomes a. software and computer function.- The total number of push-button switches required in a cockpit is at present determined by how many control options the operator requires, for the worst-case condition plus N for growth. In the future a pro- grammable keyboard can essentially solve the problems of space limitations and control location priorities for the designer.

i An advantage of the programmable Keyboard is that if the designer has to add control functions after the total number of switches has been cast in concrete, he may accommodate the growth without a hardware design change, a This can be accomplished by 'a staging technique, where a hierarchy of con- trol formats are prep-ogrammed into the system by software or hardware, The hierarchy extends from the top level overall control/system interface doom to the detailed mode option selection. The hierarchy can be organized at the discretion of the systems engineer and programmed into the computer, .

i Low cost of ownership is another advantage of the programmable keyboard and display, This is made possible by the reduction in units required for the system (with resultant savings in support costs) and the minimum costs of modifications required through the system's life cycle, To perform the integrated avionir.s functions that have been described, a control and display system must provide at least the following functions simultaneously • A primary alphanumeric display surface • A programmable keyboard /pushbutton array of at least 25 ^ey.s.

The programmable keyboard provides the computer data entry, mode and function selection, and status. This is achieved bS, using a transparent keyboard overlay on the displa y surface.

The application of fully interactive ke yboards with structured, pro grar7imed, decision-free control offers the advantage of consolidation of she large number of independent control panels normally found in aircraft ,cock- pits. This type of multi-function control is particularly beneficial in cheep- list'and routine monitoring, and initializing of aircraft systems, Also, the use of interactive keyboards provides structural dialog with the computation system, ensures that adequate communications are established, and avoids i errors or oversights, The principal objection to this format is that it does not permit the speed of reaction requires] for critical emergency procedures a ;i Computer Output Technology This subsection describes those output devices not covered in the displa or D/A converter discussions_. Analog output devices that can be driven b b/A 'converters have not been included ire this study because they are ossen- a analog st• stems. It should he noted tiall^v the same as those used with pure that servos, particularly for fight control, are critical to th(- cost and per form,ance aad that improvement is highl y desirable in both these areas..

g j j Hard-copy output, audio output, and mechanical output devices driven by digital signals, pulse trains, or discrete-pulses] signals will be discussed.

Hard-coy output devices. - Hard-copy output devices are represented by magnetic tape recorders, paper-tape punches, card punches, printers, graphical recorders, and X-^ plotters, tn-flight use of such devices has been very limited because of their weight and volume requirements as well as cost. In the past few years however, the development of printers for use with It small electronic calculators has resulted in equipment that is suitable for those general-aviation applications requiring hard-copy output (ref, 30).

Typical, larger, commercially available printers may also be applicable and are available from Practical Automation, Inc. They come in a number of sizes (18,- 35, 60 and 80 columns), but the 18 column size appears most suitable for general-aviation use. These printers use ordinary paper up to 8-1/2 inches wide, and ribbon or impact sensitive paper rolls.. A 7 by 5 matrix produces an ASCII set of 64 characters. The serial input rate is 110 per second. The price for the 18 column size is $440 (quantity characters of 100). Overall dimensions are 3 inches in height by 3-1/2 inches in width by 7 inches in diameter.

a Audio outputs, Auditory displays commonly used for, alerting or warning purposes have included whistles, buzzers, bells, horns, chines, and sirens. These devices are relatively inexpensive and will undoubtedly con- , tinue to be used for urgent warnings. The literature on audio outputs deals _ primarily with problems of signal-to-noise ratio, ,signal intensity, inter- a mittency, and discriminability. There has been relatively little avionic use of speech as an auditory output; however, audio coini-nunication from machine to man has been developed in other, applications tothe point where it is a viable technology, j I j i+ E T On-line interaction with a talking computer requires that the computer stem generate speech output. The most simple way to generate speech out- s y put is by means of messages assembled by the system out of prerecorder] words and phrases. Fully digital systems have been developed that store spoken phrases in the computer system, The recorded speech is filtered, converted from analog to digital form, edited as necessary, and stored in memory. Each phrase is given an identifying code. Speech output involves If adequate computer memory is allocated a reversal of the storage process, for speech storage, the audio outl-ut can be of high fidelity, indistingui suable from the voice of the original human speaker. In practice, the economics of computer storage as well as problems of voice matching results in storage: of speech in a somewhat degraded form such that the resulting computer voice is still intelligible, but does not have and' individualistic human quality, Research may lead to techniques for storing only words rather than bott words and phrases or it in2y prove n7ore practical to work with still smaller y llable, Eventually, it inay be units of speech such as the morpheme or s set of programmed rules for computer sN nttiesis of possible to store only Reference 31 discusses the direction this research is presently speech.

taking.

izc^d i1w AiiC ti500 audio Master Specialties Co, has recently puhlic • response calculator, which has a solid-state synthesized %-ojer tiiai announces , calculation, Thc' eighi -ftinc•i ion d( % ice each entry and the results of every llac;h spoken word is digitizud and stored also has an 8-digit visual display, Another Thc prico of this device is IP5f;5.

permanently in its own ROM, Inc. , ("J',3 1 95) uses talking calculator (Spoech Plus) from T( ' lesensor,y ` y shc ms, , , si at ihc• Uni\ er • sity oi` a speech'system, invented by Professor Forrc California. at Berkeley, which is implemented in a custom LS1 chip, developed These and office similar by Silicon Systems, Inc, , Santa Ana. California, • h c onimands err warnings may lwc o ne devclopmonts indicate! that, simple spec^c , ial icon application in the next few yc•arse practical for general- a.

f PAGE X^ GTN ^ !'E^gI ^^ALITY ^^ pQOR `f ► ii } output devices — Themechanical out u i 1 o Mechanicalo p toutput devices used c m mercially and for military avionics are also suitable for general- aviation use because they are relatively simple and inexpensive. Solenoid actuators and solenoid-field switches driven with discrete signals are the most common ^. mechanical-output devices. The applications of solenoid-operated devices are extensive, with an extremely wide range of uses, characteristics, and cost. Incremental servo motors include both stepless, high-performance prime movers as well as the more familiar stepper type of incremental servos. The variety of these devices is so great that this study can only make reference to recent technical literature that explores their application trends (ref. 32). Another type of mechanical output device is illustrated by the stick shaker or vibrator, which provides an alerting or warning signal through the sense of touch. The stick shaker has been used in a number of military aircraft as the output device of a system warning of a potontial pitch-up condition. There is an obvious application of these devices in any aircraft where a stall warning is_nceessary, and the necessary sensors (angle

r

of attack, usually) are available.

Computer Display Technology Aircraft display requirements and display types. -- The primary re- quireinent for any cockpit display is that it must be legible under high and low levels of illumination as well as in darkness and to pilots of all aae groups. Illumination levels in direct sunlight can be as high as 10'5 s Increased reliability and ruggedness beyond that typical of incandescent lamps and electromechanical devices is sorely needed.

It is also desirable for displays to have a graphic (line-drawing) capa- bility and be able to image alphanumeric characters and`s ,ymbols without a large number of wires connecting the display to the drive eleCLT-f)n cs. The most promising new technique for realizing these features appears to be a matrLx-type electronicall y controlled display. Also, aircraft displays must e be compatible with modern integrated circuits and should operate on low voltage aircraft power. The display should also operate over a minimum temperature range of -20 0 to +70'C, Displays may be classified into one of two types; passive displays, which function by modulating ambient illumination, and emissive or active displays, which generate light, The following paragraphs briefly describe promising examples of both types and give their general characteristics; more technical details are supplied in Appendices I through Q.

The introduction of on-board computing systems means that rnore sophis- ticated displays can be made available. For example, an on-board computing system can directly indicate through the display the estimated time of arrival at any particular point instead of requiring the pilot. to read several dials and perform a calculation. Displays can also present navigational information, data on the mechanical state of the aircraft, and results of an y automatic checks carried out by the calculator. It is gLLite possible that one or more larger displays may be used to perform these functions, reducing the cock- pit area taken up by instrumentation.

Contemporary electromechanical instruments are bulky, require large panel areas, and are undesirably: heavy. Also, thev have relatLvely slow response, contain moving parts, and may be sensitive to %, iteration. The only other display technique in con-irnon use is the cathode ray Whe (CRT ) however, CRT's are rather heavy and bulky, require a high voltage, and carry a slight risk of implosion.

Because of cost restraints, it is not. practical to develop new displa;, techniques specifically for general aviation. Consequcntl^ i er..hnology from other fields must be explored (e. g. military /commercial aviation for highh technology and the automotive industry for high-volume. low-cost techniques).

This section is devoted to a discussion of the potential application of current and projected display technology to general aviation: i l i Characteristics of passive displays.. -- The advantage of reflective, passive displays is that their contrast is independent of the illumination level, ie light. i, e. ,they modulate the ambient g This modulation is controlled on individual elements to form the desired image. They have low-power consumption and are ideal for large-area displays. A difficulty .with. passive displays is ma- terial saturation with increasing drive voltages. It is impossible for the passive display to compensate for the necessary short-address period by driving the display harder at higher voltages. To fill this need, some form of either inherent (in the form of high decay-time/rise-time ratio) or on- site memory must be employed Passive displays also require some illumination for night viewing and their field of view may be limited. An additional possible disadvantage in airborne application is a degradation of contrast in diffuse illumination, i. e. ,' pP g flying through a cloud, for those displays based on a scattering mechanism, Characteristics of emissive displays. -- Light-ernitting displays (LLD) are less critically dependent upon the color, reflectively, and position of surrounding objects than reflective displays and are more easily read in low ambient lighting conditions.

However, they must have sufficient luminance to compete with ambient illumination (up to 10 5 1m/nZ 2 )_, must be visible when the eye is adapted to luminance levels up to 3. 4 x 10 4 im /sr/m.2 , and must have adequate contrast with the immediate surrounding cockpit area, j Several techniques are available to reduce the amount of ambient light reaching the display. Bezels can be used where a limited field of view is acceptable and the space is available. More compact methods restrict the range of incident light on the display through the use of louvered plastic' or imbedded mesh filters. Alternately, ; neutral density, colored, or circularly polarizing' filters can be used. The colored filter matches peak spectral em.ittance of the display. All filters attenuate the incident ambient illumination twice while they attenuate the emitted display light once, resulting in improved contrast.

Q} t d One important advantage of the emissive display is its nonsaturable output.

The emitted light increases in proportion to the drive voltage up to a relatively high level. However, a means must be provided to reduce the display lumi- nance, as emitted display light which has sufficient brightness under high illumination conditions will be too bright and therefore unreadable at low luminance levels. The disadvantage of the emissive display is the liigh power consumption that results from the low emission efficiencies.

Cathode ray tubes (CRT) are currently the dominant- electronAc displays "except for pure alphanumerics. They are the standard of performance to which all other displays are compared, The CRT is a vacuum device with a cathode luminescent phosphor that is bombarded by a position-controlled elec- tron bearn, Operation is generally either video raster-scan or random access.

In the raster-scan mode, the beam traverses the whole area of the dis- play line-by-line. Display brightness is determined by the beam power, phosphor efficiency, and duty cycle. The random-access mode is used with computer-generated nonvideo signals, typically alpha-numeric or graphic information, which is usually generated with a stroke writing technique.

The disadvantages of the CRT for general-aircraft application are the large ratio of tube-depth to viewing- face- diameter, high voltages required for ade- quate brightness, associated electronic circuitr y, and bulls and power require- ments (ref. 33).

The basic advantage of the CRT (ref, 34) is the high peak brightness of greater than three million cd/m 2 , which,permits ,high, average brightness at TV display rates. The primary concern for , television is the low Ciuty cycle of typically 1/500 or 1/1000. In; spite of this low duty cycle, there are displays (ref. 30) with luminance levels of 10, 20`0 cd/m 2 with resolution in excess of 40 lines/mrn. The CRT can achieve these luminance levels due to very high instantaneous luminance and their long decay time relative to the frarne rate.

r Another display requirement that is fulfilled by the CRT is the uniformity of both the threshold voltage and output beyond the threshold. Without uni- formity there is undesirable mottling of the picture (ref. 35). The CRT meets the uniformity requirement as there are more than 1, 000 phosphor particles within the electronic scanning beam; this averaging gives good uniformity of luminance across the face of the display. The redundancy of the display, i. e., multiple elements within the scanning beam, also gives a high degree of reli- ab ility.

For a material to be considered for a display it must not only, have the capability of high peak brightness but also must have intrinsic memory or persistence. The CRT meets both these requirements. The CRT's n-lajor advantages are cost, which is 23 cents per character (Table 11), and the fact that further development is being funded.

TABLE 11, — DISPLAY SUBSYSTEM PROJECTED PRICt.S a 1Vumber of Gas Gas Liquid CRT, LED's, discharge, crystal,, characters plasma, $ S 32 6.05 5, 29 3.56 256 3.75 1. 09 1.10 512 2.33 0.78 0.66 0.40 0.75 1.69 0.62 0.35 2048 0.97 0.56 0.23 a Original equipment manufacturer price per character including decode, drive and refresh buffer.

A typical aircraft CRT display for an imaging forward-looking infrared sensor has a mean luminance of 171 cd/m 2 , with ,a peak luniinance of 630 cd/m 2,and requires 75 watts of power. The display is 11 x 8 cm and has an 800= line- per-picture height resolution. Envelope' dimensions are 19xl7x28 cm. Typical mean luminance levels for alpha-numeric CRT displays will run as high as 1710 cd/m 2 , The cost of a commercial TV display is $100 and a MIL spec unit will cost between $4000 and $5000.

CRT bulk leads to the desire for flat panel displays. Unfortunately, existing flat panel materials are not bright enough without increased per- sistence (inherent memory) or creating persistence by use of electronic on- site memory; consequently, this report defines the problems and require- ments of matrix addressed displays with intrinsic or on- site memory.

1vlatrix address displays, Today the potential for flat panel video — technology is limited to liquid crystal, gas-discharge, and possibly electro- phoretic devices. Little effort has been devoted +o the problem of addressing or signal distribution in multi-element area displays as compared to the Currently, however, the problem is development of novel display materials.

primarily that of getting the display message to all paints on the screen; the display material itself is becoming a secondary problem.

It is necessary to distinguish between active matrix addressing and pas- Active matrix addressing is defined as containing sive matrix addressing.

gain-producing, switching, and/or memory elements at every display cell.

A passive matrix, in contrast, is normally composed of two sets of parallel conductors oriented at right angles to each other, with the display medium sandwiched in between. The major problems associated with passive matrix driven displays are: 1) the excessive demands placed on the electrical and optical characteristics of the display material, and 2) the complexity and cost All of these problems can be solved or x of the external drive electronics.

bypassed by the development of active matrices.

The function of the active matrix is to integrate the electronic functions and to compensate for the deficiencies in the electro-optical characteristics displays, for example, have of the chosen display material. Liquid crystal - slow response time while eLectrolaminesceni display materials require com- Field effect liquid paratively high voltages and lack inherent memory.

i J t s crystal panels with their own capacitance and high impedence form their own memory; consequently, only a transistor is required at each display element to gate the initial charge (Figure 8). Ele ctrolumine scent displays, on the other hand, in either ac or do types require a more complex circuitry due to high voltages and significant current levels. A comparison of the circuits in Figures 8 and 9 illustrate this point.

Most flat panel display schemes use a matrix arrangement in which the individual display elements are connected between row and column elec- trodes (ref. 35). Because all elements of the matrix are permanently interconnected, when a single element is addressed at the intersection of a row and a column, all other elements along the row and column are partially stimulated. Therefore, most elements will be partially excited (cross talk) many more times than directly excited._ Each element must have a sharp threshold above the partially excited level to have adequate contrast. In display media not having this inherent sharp threshold, an additional diode is required.

if C. lrlatrix address P r, rays are generally operated at a line at a time such that each element in the line can be driven for full line time rather than for just one element time. This provides an increase in excitation time by a factor of the number of elements in a horizontal line, increasing the output brightness of the display as much as 500 times.

i The longer excitation time relieves the drive electronics of handling short, high-powered pulses to high-capacitance electrodes, However, line- I at-a-time operation at TV rates requires a 15 -kllz shift register for the horizontal rows, a video sampler- distributor, two storage registers, and a column driver (see Figures 1.0 and 11). The video signal for one line of in- formation is fed into the sampler-distributor, Parallel video information is then stored in one register while the other storage register is feeding the column drivers. The storage registers and column drivers maybe either analog or digital, but it is difficult to produce a large number of analog cir Source and data bus TFT Gate bus Liquid crystal element Figure 8, Design of Elemental Matrix Circuit for the .Large-Area Liquid Crystal Display Xi X i 1 Xi E 2 Y.

-- ---- cs Element j' ^ EL i T l.j, I I I j +1

4^

Matr-r d^;ilag pane.!

+Vo Off +Vo Off 0 Volts On +Ve u Off N +VO Off +U I o Off +Vo T Off +Vo Off Video Vertical signals 0 - V5 .

sync Sync Colunui drivers sep b Horiz Storage register Sync Video 10-MHz sampler - s Amplifier Figure 10. — 'Block Diagram of Matrix TV Display (Diode shown can be inherent feature z U ) of display elements (V s 0 J -; Storage capacitor To power source Al To row selector circuits T J Picture element i t J To column drivers (video signals) Figure 11. — Circuit ,Conf figuration Needed for ;Frame Storage in Matrix Display 'i cuits with the same characteristics, thereby avoiding vertical streaks in the picture. It is expected that digital circuits will be used to overcome this difficu,Ity.

The average brightness of matrix displays develo developed to date of a s n as g gp great as desired. T,,^tble 12 lists the expected maximum brightness for vari- ous display media when operated in a line-at-a-time format. This problem can be eliminated incorporating an analog memory driver at each picture by elemen; location (Figure 11), which would maintain the display element exci- tatioi during the whole frame time and increase display brightness accordingly.

Moreover, the memory elements must either control an external power Source or act as amplifiers, which creates problems of element-to-element uniformity.

TABLE 12. — AVERAGE BRIGHTNESS AND LUMINOUS EFFICIENCY OF DISPLAY MEDIA Maximum average brightness Peak at 1/5000 2 Cd brightness, Cd /m duty factor, /m Efficiency, lm /-\^r ;10-15 0.5-1 Plasma 7500 1-5 5=10 AC EL 500 3000-5000 25-50 0.5-1 DC EL 5000 5-10 0.5 LED Catho- luminescent > 100 000 N 500 100 phosphors display. Monolithic integrated circuits of matrices over 2 to 3 inches may be beyond -the present or near-future capability of silicon technologies (ref.

36). However, thin-film technology appears adequate for large-area active matrices and can be integrated with a large variety of display media. Thin- film transistor work is currently being conducted by Westinghouse and Aerojet General to build large active matrices.

It is not clear which 'technology - thin-film transistors (TFT' s) or silicon processes will eventually produce usable matrix displays. A one-inch square silicon matrix is huge by silicon IC standards; shorting problems, insulator pin holes, metalization, wafer breakage, in-process inspection and testing are the problems encountered with obtaining the needed crystalline perfection over large areas, The key problem in thin-film technology is the need for 100 percent area yield in all process steps. This is different than the semiconductor circuit manufacture where many chips are formed simultaneously on a single wafer and 100 percent wafer yields are neither needed or expected. The thin-film operator to deposition sequence is long and somewhat complex and subject mask fabrication (for thin-film deposition) but also the only errors. Not alignment during thedeposition steps must be perfect. However, mask loca- tion changing, deposition material sequencing, thickness monitoring can all be done by automatic equipment, and the process steps are quite fast, therefore, a large output per machine can be expected with reasonable vields as manual operations are eliminated.

and Passive display material types. -- Liquid crystal, electrochromic, electrophoretic, and PLZT are three examples of low-power passive displays.

emit visible radiation; rather, they control the passage These displays do not of externally generated light through the display. Structurally, these three displays have similar principal operations but dissimilar properties, I 77r a ,.

Liquid crystal displays: Liquid crystal displays (LC D 1 s) possess the normal solid and isotropic liquid phases of normal liquids, but have a third phase which occurs between the solid and the isotropic liquid phase. In this intermediate phase, the liquid crystal flows like a fluid but exhibits a crys- talline organic state. The molecules are usually long and rod-like in shape and are responsible for the display-related anisotropic properties.

The liquid crystal is confined between two glass plates with their con- ductive coatings in contact with the material. The electro-optic phenomena can be divided into two groups: 1) those caused by dielectric forces and the so-called field effects, and 2) those induced by a combination of dielectric and conductive forces.

The most promising material and arrangement results in a cell structure called the twisted nematic. Linear polarized light propagating perpendicular to-the cell is rotated approximately 90 degrees. ` Maximum light transmission is obtained by orienting a crossed polarizer and analyzer. The transmitted light decreases when the applied voltage exceeds a; certain threshold voltage and the liquid crystal molecules start to change their orientation and the polarization of the display, The advantages of the LCD's are low voltage and lowcurrent, which allows the cell to be driven by CMOS IC's and the fact that their contrast is independent of ambient light level. The disadvantages are slow response time (10-100 msec) and the difficulty of multiplexing. They have a limited temperature range for operation and the viewing angle affects the contrast.

Electrochrornic displays (ECD's): An electrochromic'material is one in i which the color is changed by the application of anelectric-field. current.

J

One version uses an aqueous solution of a special organic dye contained be- This display relies upon the oxidation- tween a pair of transparent electrodes, reduction reaction of the dye controlled by the application of voltage to the electrodes. The dye is colorless in the oxidized state, but applicationof about = 2 volts across the electrodes causes the reduction reactionto occur, and hence, a dramatic change in color as the dye is reduced:, When the polarity of the voltage is reversed,.the color compound oxidizes back to the colorless state.

Another type of ECV uses a solid, inorganic film as the eleE trochromi material. A grass substrate with a transparent conducting layer or electrode is coated with a thin film of the material. A layer of insulating material is deposited over the film, followed by a second electrode. The film is colorless in the normal state, but when a voltage is applied display appears blue.

'When the polarity is reversed, the film again becor c-s colorless.

The advantages of this material are that it operates at 5 volts or less, and its appearance does not change with ttie viewing angle. The disadvantages are the slow response time (between 20 to 200 msec) and the difficult multi- plexing.

Electrophoretic displays: This type of display uses pigment particles of one color that are suspended in a liquid of a different color. The suspension is sandwiched between a pair of electrodes, and at least one of them is trans- parent. The pigment particles are held in a colloidal suspension and carry a charge. When the electrodes are charged, the pigment particle moves toward' the front electrode, where they collect to scatter the ambient light, making the display change color. Reversing the polarity causes the particled to move towards the other electrode, changing the color of the display to that of tile suspension fluid.

The advantages of this display are that they operate at low voltages (less than 10 volts) and are legible over a wide range of viewing angles,- The dis- advantages are that the response time is slow ( in 100 1 s of msec) and that-the particles may eventually settle out of suspension or maybe damaged by shock ;!

and vibration.

PLZT: PLZT is a transparent ceramic electro -optical material (Pb, Liz, Zr, Ti), which exhibits light transmission properties that are voltage depen- dent. Because the material is in the solid state, it is necessary to use the optical properties of induced birefringence and of scattering. The birefring- ent mode is implemented by operating the material such that the applied voltage will vary the polarization of the transmitted light. The effect can be observed through an analyzer sheet as a change in intensity. In the scattering mode, the transmitted light is diverted from the normal propagation direction and scattered into a larger solid angle by the application of the voltage to the material. Within these two modes of operation, the ' material can be classified according to its memory materials. The material may either have memory or no mewories in both of the modes of operation.

The advantage of the material is that it has the potential for intrinsic memory, which would permit displays with higher contrast. However, the disadvantages are high drive voltage (40 volts), cracking under stress, _poor contrast, small viewing angles, and a requirement for transverse exitation.

This last requirement requires either depositing interdigitized electrodes or cross-slotting the material itself. Both techniques are difficult for matrix cell fabrication.

a material types . - displays Three examples Emissive of emissive dis- plays are light emitting diode (LED), gas plasma devices (GPD), and electro- luminescent. devices (ELD). These devices emit visible radiation and consequently require more power than `the passive display.

Light emitting diode: This device is essentially an electrical transistor.

y Basic components are the diode leads, crystal chip, and possibly a, diffuser lens. Diode chip emitted light is proportional to the current flow. L..uminous /m2 are common without heat sinking and cooling, levels up to 340-1400 cd Voltage levels vary from 1, 4 to 4. 5 volts depending upon the material. Color of the output of the device is primarily red,; but green and yellow are available and a b,j.^ue output is under development. LED's are high-current, low-voltage devices that are compatible with discrete MOS transistors.

f -< 89 l The advantages of LED's are that they can be molded into a large variety of shapes with a large range of optics. They are ^ compatible with the low- i They are rugged, voltage supply provided by conventional transistor circuits.

g have a high reliability with a long life, and are resistant to temperature change. The disadvantages are that the material is relatively expensive and not readily driven to maximum brilliance by MOS IC's, particu- the LED is r Consequently, larly CMOS IC's, due to the electrical current requi ements.

they are not likely to be used in large matrix driven displays.

i Gas-plasma devices (GPD): A plasma panel is a gas-filled device. It It has two modes of is the most advanced class of all flat panel displays.

ac and dc. The gas fill is usually neon or other noble gases mixed operation: A panel resolution element is defined with other inert gases such as nitrogen.

by a very small gas volumebetween orthogonally oriented sets of parallel conductors; one is on the front transparent surface, and the other is on the The visible plasma discharge is observed when a back transparent surface.

Some of the high-voltage, low-current is applied between the electrodes.

many display types are self scanning and require few electrical connections.

to develop real-time These displays have been under moreintensive stud TV displays as they are closest to having all the required characteristics.

The advantages of GPD's --re that they have sharpthresholds with a high The response time is fast contrast ratio and that gray scale is possible.

The disadvantages are that they pri- enough for line-at-a-t.me addressing.

marily come in red color and require 170 volts.

These devices are essentially an electrical Electroluminescent (ELD): luminous capacitor consisting of two flat electrodes, one of which is trans- When a low- parent with a space filled with an electroluraine scent phosphor.

current, high voltage is applied to the electrodes, - a field is created causing- Most displays, are single the coated areas to emit a luminous cool light.

The colored, usually green or orange l because of the 1 igher efficiencies.

potential may be ac or do depending upon the structure, but they usually operate in the ac mode:

i

, The advantages of these devices are that they can be driven by TFT's for large-scale matrix displays. They are lightweight, have low current require- ments, and produce no heat. They have high reliability and a long life and are not affected by temperature, vibration, or shock. Luminance levels are usually only 15 to 100 cd/m 2 , and they come in only one color for a particular display type,but that may be red, green, yellow, blue, or white. The dis- advantage is the requirement for high voltage (up to 600 volts).

basic parameters for comparison Display material comparison. -- The of candidate display materials are visibility in the high ambient background illumination of the cockpit, luminance, contrast, life, power requirements, and resolution. A comparison based upon the size and bulk is not made as the materials are all intended for flat panel displays, and it is assumed that panel

i

not be a problem as drive electronics can probably be miniaturized depth will with IC. If the bulk of the electronics becomes a problem for high-voltage in a remote location. Thickness of the panels is displays, it can be mounted expected to be less than one inch.

Table 13 presents display material characteristics, and a detailed dis- cussion of these parameters is presented in Appendices H through P. The pacing requirements for a display material are contrast and lu-n1inance.. A for these requirements is presented in Table 14. A discussion case specific of these requirements and the deviation from them is presented in _Appendix 3 not available in the literature, five per- P. Because data on reflectance is all materials. A display or time-averaged cent reflectance is assumed for contrast of 10:1 is also assumed as a requirement. The intrinsic material contrast and 111rmnance is equal to the time-averaged contrast and luminance only when the display elements are on continuously (nonmultiplex or memory matrix addressed). However, the contrast luminance is reduced when a character is multiplexed or a matrix is addressed one line at a time witiiout memory.

I !

' I P.mperature C' . ompatible ( Voltage Intrinsic lyrrsrnt ITltittmtr resolution, Alnterial and Response times elech • on^•s `C range. g and resolution, limit, lines/:rm type of display contrast ratios current lint 0 to X70 0 msec rise iV C`NOti IC _ 40 100 l0- 2 LCD 15:1 to 50:1 y I Possible time; and 300 ti (Pass ivel I μlVlem 2 - i me y. msec decay 30 to 50 V Discrete transistor Vot determined PI ' Z1 100;1 at 90 V Not ',lot dr tormiricd 1 to 100 p sec (Passive) repotted μA 1 20. 40 100 nsec 1,4 to 4. 5 V Bipolar transistors \% We LI:D 50 : to interface with - - (Emissive ) 1. 5 :\/em" _ AMS drivers M I D 1 (time 2 0 40 1 to 10 M Sec 170: V. MOS to swing 14ide 50 : lower voltage of lower (Emissive) averaged) 0, 1G 1 /tin - 25 V on 135 V hive 15 to +50 msec rise 10 V to 't0 V Discrete transistors EPID 30:1 to :10:1 q nnnown I'nknown '0. to 100 (Passive) time acid 100 iasoc or PAIOS X's T.ow current decay tiiae. at 50 V Wide P]LD >50 ; 1. a 40 200 to 000 V `t IT matrix and (Emissive) Time averaged) (3lcliz ac) high-voltage. I PT's ( < 5 V Bipolar transistor. - 20 to +70 ECD - Limited contrast unknown Unknown. . 100 to 500 msee (Passive). more suitable than High current A105 TABLE_ 13 • — DISPLAY MATERIAL CHARACTERISTICS (Concluded) Color anti viewing angle I Intrinsic on-site I Life and Comments and contrast memory memory luminance, cd/m - reliability sensitivity TFT and • Alatrix displays under development Not applicable No 50, 000 hr 15, to 20, silicon chips • Regnire heaters for temperature control Angle sensitive Ample development funds available from • computer and watch industry for multiplex displays TIT or • No high-volume user Not applicable 1 as Life not Poo` contrast ferroceramic .

beyond 15° determined y Seven-segment numerical display available in hirefringent mode Not rugged No Silicon • Limited to small displays lied, green, yellow, Lenses to I 106 hr orange transistor increase J • dis lay brightness Power High reliability p luminance.

and rugged - 1000 peak a Red ispoor color for aircraft displays decrease view angle Potential 1 e • Alost advanced Rat panel technology Iced, orange, blue, Wide - > 20,000 he fo r • Supported by TV industry - Rugged and 0 (time averaged) reliable •.

Sharp threshold for good contrast and gray scale being developed T TIT • No application yet 106 to 10 Not applicable ] es Very wide cycles in Not sensitive Not reliable 3000 he • Red,. green, yellow, Phosphor Tl^T Thin,. lightweight, flenble Very wide 20,000 hi•s blue, white 140 to 940 decay Not sensitive Rugged ^• Matrix display under development (time averaged) 1: es with Unknown • Alatrix development unlikely: 10+6 to 10" Blue, green Very wide cycles Open Not applicable • ` New technology Not sensitive circuit Unknown voltage TABLE 14, - FLAT PANEL DISPLAY MATERIAL INTRINSIC CONTRAST AND LUMINANCE REQUIREMENTS - - Reflective passive displays Active display- (a) (a) \onmultipiexlonmultiplex or on-site or on-site \lultiplex or nonmen,ory' dine-at-a-time memory matrix Multiplex or rtonmemory line-at-a Mince memory matrix matrix address, 30 frames/sec matrix address,30lrame>lsec address address 16 line 100 line 50t; line - 16 tine 100 line 500 line Luminance Contrast IB) luminance, Luminance, Luminance, rd/m= Contrast sdlni" Contrast cd/ ni2 Contrast Contrast. Contrast Contrast Contrast cd/n`2 CL 2/100 to B1. BL C_L BL CL Lumumnce and CL CL C^ C \- 4 \ A \ \. 5!100 of contrast.

White cloud eye 2x104 680 3200 5 10 to adapted display 10:1 to 53:1 to 340:1 1700;1 10:1 53;1 340:1 1700:1 to 2.8x105 shaded from 1700 9100 .:5.7x10'1 ambient illumin.ition C1.

C' L. CI. NL (I-C) \ C1. LL ^ Luminance and CI. .

\- 1tL:1 • c• 1 >lo-- RLI' -c) >10— >]oc ltl:c- -c') >lo— L L 1 \ 1. _^ C \... -r C' 1 \ contrast I — . _ 1 I C rr C - C rr C t\ (C,--- .

It fC: - tC.

Ll I.

]t ftlt Ambient sky 8,2x105 17000:1 '.10:1 53:1 340:1 1700:1 4,460 100:1. 2. 6x 104 530:1 1,6x105 .3400:1 illumination of display pirect sun 53:1 t!10:1 1700:1-. 16,000 100:1 0.2x104 530:1 6x10 3400:1 3xic5 17 000:1 illumination 10:1 of display :.

p1 uuntra6t ratios and luminance am peak or intrinsic required levels for display material It should be noted that passive display luminance is a function of reflected ambient illumination. It is assumed that the cover glass reflectance is lower than the display reflectance and, therefore, display contrast remains con- stant with illumination.

Table 14 presents the contrast and luminance requirements for three conditions of high ambient illumination in the aircraft cockpit. The first con- dition is when the display is shielded from all ambient illumination, and the required display luminance is established by eye adaption to bright white clouds. The second condition is when the display is shielded from direct sun- F light but is illuminated by reflected light from white clouds through the cockpit windows. The last condition of direct sun illumination is the most difficult for active display visibility. This table does not include the use of ambient light suppression techniques for active displays because specific display reflectance data is not available. T herefore, Table 14 presents aworst-case -- set of requirements and provides a basis for relative comparison of display materials.

Table 13 shows that all passive display materials have adequate intrinsic contract (10:1) for nonmultiplex or`memory matrix address displays. All display materials except electrochromic (ECD) and perhaps electrophoretic (EPID) have enough intrinsic contrast (53:1) for use as 16-character line multiplexed_ or nonmemory (line-at-a-time address) matrix display. However, - there are no materials that have adequate intrinsic contrast when a high resolution (100 to 500 character/line) nonmemory display is required. PLZT . may have a future potential of 1000:1 contrast, but it requires a high drive voltage. On-site memory is a better approach to the development of high-resolution passive displays as any material with lower intrinsic contrast but superior electrical characteristics can be used.

: Intrinsic contrast requirements for active displays become much higher than for passive displays when the active display is in ambient illumination (Appendix Q). These ratios range from 530:1 to 17, 000: hand none of the a materials meet these requirements. On-site nonlinear devices could be used to improve the material excitation threshold (Appendix Q) and contrast; however, on-site memory can be provided as easily and then high contrast would no longer be required, it should be noted that intrinsic luminance requirements for active displays in ambient illumination (Table 14) becomes much larger than the capabilities of the display materials. Even two orders of magnitude reduction in luminance requirements (Table 14) for high resolu- tion displays through the use of ambient light suppression techniques will not help. Consequently, on-site memory is definitely required for both passive and active high-resolution matrix displays, E G y y f ;,

SECTION 6 PROJECTED LARGE-VOLUME USERS The technology used in future general-aviation avionics systems will not be defined and developed primarily through the efforts of general aviation; rather-, these advanced avionics systems will largely be based upon exploita- tion of technology developed for other high-volume users. The trend is toward development of technology with the largest user base. It is, there- fore, the purpose of this section to define the industries and/or applications that are the driving forces behind this technology and the direction in which those forces are operating, MICROPROCESSORS, 1/0' s, AND TRANSDUCERS Automobile Industry The automobile industry is potentially one of the largest volume users of microprocessors. The world-wide annual production of passenger cars, trucks, and buses is measured in the tens of millions of units. If several are used in each unit, the volume requirements microprocessors production for microprocessors could exceed one hundred million units with a value in A excess of a billion dollars.

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The U. S. automotive industry is facing increasingly stringent federal regulations for emissions, fuel economy, and safety. Emission' control and fuel economy tend to work against each other as well as against overall engine performance (power, starting ease, smoothness). Industry leaders L feel that electronics is the only viable near-term solution to achieving the precise balance required in all these factors, They are particularly interested in microprocessors because they offer the computational power,, flexibility, and potential low cost necessary to the following applications: Engine control (ignition timing, fuel management) • Drive train control (transmission shift point, speed control) • Safety systems (anti-skid braking, collision warning) Other areas that are being investigated include diagnostic systems (both on the vehicle and at service centers), display management, passenger comfort, and entertainment control. Solid-state electronic systems have already been used in several of these areas (electronic ignitions, fuel injec- tion sy stems, speed control), but it is hoped that microprocessors can provide increased capability at lower cost.

The main areas of concern to automobile manufacturers are the cost of rugged, high-reliability microprocessors and the availability of good, low- cost transducers. There seems to be no question that currently available microprocessors can meet the speed and performance requirements of these applications; however, there is doubt that the microprocessors, transducers, and all their associated electronics can meet the tough environmental problems found in automobiles, i, e,. , temperature, humidity, vibration, and A dirt, The requirements are stringent; the manufacturers require failure rates less than 1 percent per 50, 000 miles because of legislative maintenance liabilities. In terms of electronics, this translates to about 700, 000 hours mean time between failures in a 25-component system, The costs of produc- tion and screening for these requirements makes the currently available microprocessors and transducers too expensive for general application.

i Automobile manufacturers are confident, however, that cost and availability "problems will be solved as a result of large-volume demand. They need a microprocessor under $10 and a transducer at about $1.50, +'.

i The first microprocessors in automobiles may be introduced. as early as the 1977 model year. Ford has indicated the possibility= of including one for ignition timing in its Mark IV line, Each of the major manufacturers will probably follow by introducing microprocessors in their highest price model lines during the 1977-79 model years. If prices decline enough, the general y spread of microprocessors to all model lines should occur by 1980. By 1982, several microprocessors tied together in a multiprocessor network will probably appear.

In summary, the automobile industry has the need and the large - volume demand necessary to be a major influence in the microprocessor market.

Computer Industry The general computer industry will, of course, be a major user of microprocessors. Application areas include nearly all phases of the industry, including: • Peripheral controllers • Data Communications Multiprocessor configurations for mainframes • There is an increasing trend toward replacing the special-purpose, hard-wired peripheral device controllers with microprocessors. The " peripherals include card readers, floppy'' discs, cassette tape units, line printers, and CRT display terminals. The use of microprocessors dramati- cally reduces the total parts count while lowering cost and performing the required function as well as or better than the dedicated special-purpose hardware. This area is already a large andrapidly expanding market for j microprocessors. Bit slice microprocessor chips in particular have been designed into a number of- such =applications since early in 1975.

Data communications is one of the mostromisin a p p lication areas p g pp within the computer industry. The typical uses of microprocessors in this preprocessors, intelligent t fYeld include test e ui ment, re rocessors, Lerminals, data q .p concentrators, message switching, and communication instrument controllers, ; 99 i { a The availability, low cost, and functional capabilities of micro- processors has generated interest in multiple microprocessor networks as an alternative architecture to large mainframe CPU's. This approach can increase throughput, reduce resource overhead, and increase fault tolerance in large-scale computer facilities. Maintenance costs and repair time can also be greatly reduced through the reduced parts inventory requirements of this approach. The multiple microprocessor network will affect the entire computer industry from minicomputers to large mainframe CPU's.

Consumer/ Commercial Products Microprocessors are having a tremendous impact on the consumer and commercial products industry, They are being used both to enhance the performance of present-day equipment and in the development of completely new producta for offices, stores, households, and entertainment centers The personal electronic calculator, whose components were the forerunners y t micro pr ocessors, u ickl y of toda y's is an exam ple of how uckl a new product can P q attain international prominence.

Point-of-sale terminals and supermarket checkouts are already using v large volumes of microprocessors. Other areas that are currently using microprocessors include investment houses and the finance industry,')anking, business inventory control, and electronic test_ instruments.

^ ^ i Microprocessor technology is expected to cause the low-cost household computer to emerge_ as a significant product within, the next few years.

Hobby kits based on currently available microprocessors have been on the market for about two years. Although the early kits were relatively expen- sive for the general hobby market, they immediately sparked tremendous enthusiasm. This enthusiasm will become more widespread as prices drop and the variety of household uses becomes known. The home TV set connected to a` microprocessor will become an interactive information and : .^ entertainment center as opposed to the passive role it now plays. The home computer will become as widespread as the ubiquitous TV set by the mid 1980's. This will cause an annual demand for microprocessors in the millions of units.

The microprocessor has begun to show up in household appliances as a replacement for electromechanical controllers, This particular application does not require a great deal of speed or accuracy, but will still provide a healthy market for low-end microprocessors. Typical applications include control systems for dishwashers, ranges, clothes washers, microwave ovens, and sewing machines.

In the entertainment segment of the commercial market, the old electro- mechanical pinball machine is rapidly giving way to a variety of sophisticated games using TV screens and microprocessors. The new electronic games not only provide greater interest and complexity, but sharply reduce the high maintenance costs associated with their electromechanical counterparts, Highway .departments x . Federal and State Highway Departments are faced with ever increasing problems of traffic safety and congestion. In their attempts to solve these problems, they are using automated controlsystems for intersections and a super-highway entry ramps. Until recently, they were forced to choose between minicomputers and special-purpose, hard-wired controllers for these systems. Microprocessors offer significant advantages over both.

Compared to minicomputers, microprocessors are a better match in terms of computational power, cost, and size; when compared to hard-wired random logic controllers, they offer much greater flexibility, reduced parts count (at least 60 percent), and reduced power requirements, size and weight.

s y } ^ G u There are several companies already active in the traffic control busi- ness. Multisonics Corporation of San Ramon, California, uses the Intel 8008 as the CPU in its Model 901 intersection control system. Comstar Corporation teamed with TRW Systems, Houston, to Provide 1000 micro- processors for traffic control in the city of Baltimore.

With the current and expected future problems bf highways aipty and traffic congestion, microprocessors will most certainly be used in ever increasing volume. This application may prove to be one of the largest volume users of microprocessors in the next 5 to 10 years.

Military The Military has shown a rapidly growing interest in designing micro- processors into their defense systems.. This interest has generated intense competition from semiconductor firms through defense systems contractors to supply military needs. Estimates of the near-term potential military market for microprocessor devices are in the 8-to-10 million dollars per year range.

The military's interest is sparked by the promise of higher reliability, greater hardware and software flexibility, smaller size, and lower power drain. The Pentagon also sees the microprocessor as a means of lowering defense systems' initial and life-cycle costs. They are constantly pushing for lower maintenance and logistics costs and see the microprocessor as a possible answer. The microprocessor can make it far easier to design built-in-test and diagnostic equipment into their defense systems to trouble- shoot potential, problems before they arise.

'There are several current military projects that involve microproces- sors. They include jet engine monitoring and control systems, communica- tions control systems, airborne and manpack navigation equipment, fault G, detection and diagnostic systems, and torpedo control systems. The Navy' ,s Interim Standard Avionics Digital Computer, which is slated to be used in i all future naval aircraft, is one of the first major military projects to specify microprocessors. Three basic designs are expected; a standard avionics computer, a stand-alone I/O processor, and a combination computer-I/O processor.

The most significant problem areas as far as the military is concerned are finding microprocessors that can meet stringent military specification environmental and speed requirements and cost. Most commercial micro- processors cannot meet these requi7rements therefore, many military sys- tems douses are trying to develop their own microprocessors. One concept that is being examined is that of a ''standard microprocessor building block.

This approach would help to alleviate the problems of small prodite ion runs of specialized processors for particular applications.

It is almost certain that by 1980 several military-qualified micro processors will be in production and available for use in general-aviation avionics. It is also probable that the cost of these units, even though greater than that for commercial-grade microprocessors, will be compatible with general-avionics economics.

Industrial Automation There are a myriad of applications for microprocessors in industrial equipment and factory controls. They are already being used in factory automation systems, numerical control, data acquisition systems, and in { industrial robots. They offer flexible, low-cost computational power that can meet the rugged environmental problems of factories.

i The situation within the process control industry can be termed explosive". Within 1 to 2 years every producer of industrial control equip- ment will be required to include microprocessors to remain competitive, The availability of microprocessors may encourage newcomer's in the indus- try and will certainly lead to new and more diverse applications, Current industry surveys indicate a market of about a thousand micro- computer units per year at an average price of one thousand dollars. This is expected to increase to nearly thirty thousand per year by 1984 at an average unit price of $300 for the system.

One area that will develop rapidly as a result of microprocessor tech- nology is industrial robots or programmable manipulators. This application also dep?nds upon other technologies including sensors, actuators ; and the development of sophisticated algorithms for pattern recognition and goal- directed behavior by machines. When breakthroughs occur in these tech- nologies, especially in the area of algorithm development, the demand for microprocessors will increase dramatically in this application. Although quantitative estimates of this demand are difficult now, it seams feasible that it will reach the tens of thousands of units by the mid 1980's, PROJECTED LARGE-VOLUME USERS FOR DISPLAY MATERIALS The rapidly growing digital timepiece and calculator markets will boost production of the newer displays such as GPD's, LCD's, and LED's, Low cost is an absolute requirement for the consumer market in general, and low- power consumption is a vital requirement for wrist watch and portable calcu- lators. Liquid crystals, which have lower power consumption, will be priced lower than LED's due to batch processing, The GPD -requires a higher voltage than LCD and is not a candidate for this high-volume market, The largest potential market for flat panel displays is the consumer TV.

Gas-discharge displays are leading the race for this application, but area long way from adequate performance at the present time, Almost all flat- panel research is based on the use of matrix arras- of display devices, which requires the sharp and uniform threshold of gas-discharge devices.

T It is expected that there will eventually be a high-volume consumer a market for flat-plate GPD's as the result of current extensive researctl and a development (Appendix N), ,p

i SECTION 7 COMPUTER TECI-INOLOGY PROJECTION The technologies that are of interest based on general-aviation require-

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ments and large-volume users have been covered in the previous sections, This sectionwill address the future of those technologies selected as most significant for future general-aviation avionics advancement in implementa tion technology, subsystem technology, system technology, and operator/ computer interface technology, SEMICONDUCTOR TECHNOLOGY_ PROJECTION Progress in the circuit design and packaging of various technology areas will continue at the current rate at least. Prediction of the specific circuit technology that will be dominant in the 1980 1 s is not within the scope of this study; however, the dynamic advances occurring in the various areas show no signs of approaching a limit, Appendix A discusses probable trends, i COMPONENT AND MODULE TECI-INO.LOGY PROJECTION Circuit/systems designers can expect even a wider variety of component J and subsystem modules to choose from in the 1980 1 s, For example, the microprocessor offers- the designer of inexpensive systems the computational power of a computer functioning as a component, Processor, memory, and IO module technology projections are the major areas covered in the follow- ing subsections.

u4 Processor Technology Projections Large scale integrated circuit (LSIC) technology made the mi sor possible. Further developments in circuit technology and arc «rill-product the following general trends in p^•ocessor technology:

• Greater functional capabilities

• Greater speed • Lower power requirements • Increased standardization o Increased reliability and 'ruggednes s e Increased flexibility • Lower costs The functional capabilities of a microprocessor are measure( power of its instruction set, ease of addressing, and by its data /instruction word length. Today's microprocessors have relatively simple instruction a sets when compared to today's minicomputers. A typical microprocessor has 20 to 60 instructions while mangy- minicomputers have 150 to 200. The i short word lengths of today's microprocessors (usually 4 or 8 bits) result in curnbersome addressing when compared to minicomputers. This has already begun to change with the appearance of 16-bit microprocessors with a variety- of addressing modes. The application of bit slice microprocessor chips also provides great flexibility. It is anticipated that b,- the 1980's microprocessors will achieve or exceed the functional capabilities of today's it nicompute:7s Features such as hardware multiplz and divide will be gen erall-,- availal,)le, and some microprocessors will also include floating point hardware and trigonometric functions, Microprogramming techniques zna-, also be applied to provide powerful instruction sets for particular applica- tions This does not imply that the 4- and 8-bit microprocessors will fade awav; for many applications they are perfectly adequate and will definitely- see large-volume use.

a I There are many factors affecting the overall speed of a processor.

These include memory access time, instruction execution time, and the the instruction The power of set. most meaningful comparisons of processor speed are made with benchmark tests where the same general function is performed by several processors.

Based on this type of comparison, today's microprocessors range from about an order of magnitude slower to the equivalent of today's minicomputers. It is expected that by the 1980's most Is microprocessors will achieve instruction execution times in the 0, 2- to 2- Iasec range, which is equivalent to today's minicomputers.

There will be a i spectrum of available speeds, depending upon the circuit technology used, a TTL and ECL will be used in high-performance microprocessors, while the various MOS technologies will be used in low-performance microprocessors, Microprocessor power consumption is a function of circuit technology and word length, Today's bipolar microprocessors dissipate about 3 to 5 watts, single-polarity MOS microprocessors about 0. 4 watt, and C110S microprocessors about 0, 03 watt, These power dissipation, levels will gradu- ally decrease over the next few years, and by the 1980's they will be reduced by about a factor of two for a given technology and word length, I2 tech- nology will see increased use for microprocessors and will produce' a range of power consumption as a function of speed, There is currently very little standardization among microprocessors.

This is primarily due to the immaturity of the industry, the explosive growth ^PS as a result of the demand, and the lack of a clearly dominant product.

Second sourcing of microprocessors and associated components is becoming more common. By the 1980's, the industry will mature, and a few superior products will emerge. Standardization will be necessary -to keep the industry growing and will occur in the following vital areas, o Instruction Set - Manufacturers will develop upward-compatible instruction sets within their own products, 1\Iany of these will a emulate popular minicomputer instruction sets to take advantage - of large software-support bases, • Higher-Order Language - A few higher-order languages (IIOL's) will emerge as industry standards for broad appli- cation areas. They may be based on today's FORTRA- , BASIC, COBOL, or PL/1, • Voltage Levels There is a wide variation in the required supply voltage levels for today's microprocessors, This will be standardized by circuit technology, with those tech- nologies requiring the fewest levels (such as TTL or I2L) emerging as leaders,

Interface Requirements Interface standardization is urgently •

needed, but will come slowly. Complete standardization is not expected by the early 1980 1 s; there drill, however, be advances towards universal I/O modules for common peripheral devices.

0 Packaging - Current microprocessors come in 16, 18, 24, 40, 42, and 48 pin dual-in-line packages. The 40-pin package is the most popular at the present time, but cannot be con- sidered a standard. It is expected that packaging standards will follo standardizatiotr in other areas.

Microprocessors are inherently more reliable and rugged than today's minicomputers, This is a direct result of LSIC technology- and reduced parts count, One area that does require improvement is the operating temperature ra n Most of toda y 's micro pr ocessors ^^i11 only o p erate within the range P ge •' p of 0 to 70 ` C. This range is too narrow for most -n-iilitary and automotive applications. The large-volume demand in these_ applications will result in microprocessors that meet extended temperature range requirements ( -25 to +100`C) in the near future. Full military temperature range (-55 to =125'C) { will be available in 'Lhe early 19801s, _As the size, cost, and performance levels of microprocessors improve, their flexibility will be enhanced. These trends will lead to increased { fl c microprocessor modularity, which is their greatest asset. Microprocessors will form modular system building blocks that can be assembled into complex computing systems, Microprocessor manufacturers will design fully com- patible lines of processors with a wide range of capabilities. Modularity will allow low-performance systems to be easily upgraded as requirements change. The problems of standardization, however, must be overcome if microprocessors are to become truly universal computing elements.

The total cost and cost distribution in computer systems has been chang- ing rapidly in recent years. In the early 1970's, minicomputer systems' costs were in the $10 to 20K range with the CPU cost as a major component l of that total cost. Current system prices are in the $1 to 5K range for com- a puters based on LSI techniques, with memory taking over as the major cost component. Microprocessors will accentuate this trend until limiting factors appear. As processor prices become insignificant compared to memory, I/0, and peripheral devices, the downward pressure on processor prices will lessen and will shift to the other components of a complete computer system. There will be a tendency to maintain processor price levels while j increasing performance and reliability, Figure 12 shows the history and projection of the price /performance ratio for single-card processors. Included are processors using MSIC and LS1C, as well as current and future 16-bit monolithic microprocessors.

^^. The price/performance ratio was determined for each device as the adver- tised single-unit quantity price, divided by the number of bits, and multipliekl by the device throughput when operating with a flight control instruction mix, l - fhe family of Honeywell processors in this projection is intended for mili- tary applications and, consequently, is designed to more stringent environmental requirements than the commercial processors for which data points are in cluded. The figure is not intended to present a comparison of specific proces- ^ f i f t i 0.010 O MONOLITHIC El LSIC, MSIC /ASSEMBLIES O HDC-301 p (,800 \ Q HDC-301A p IMP 16 0.001 NDP-5301 TMS 9900 ^\ (9904 CPU) PROJECTED P%P RATIO FOR A FAMILY OF HONEYWELL SINGLE CARD PROCESSORS \ HDP-5301 COST i$) P/P RATIO = BITS X THROUGHPUT (KOPS) \ PROJECTEDP RATIO SLOPE DUE TO , PRICE \ REDUCTION OF SEMI- CONDUCTORS ONLY.

a74 1975 '1976 1977 1978 1979 1980 1981 1982 -1983 4 19E sors, but only to indicate trends. The dotted line on the figure indicates the trend due to the semiconductor price reductions projected. The total cost of a processor includes PC board, connectors, and other components, as well as assembly labor, which may be increasing rather than falling with the semi- conductor prices.

The factors involved in lowering microprocessor prices include the usual pressures of competition and the economics of large-volume production.

There are other significant factors that specifically apply to the micropro- e cessor industry. Testing is a rhajor contributor to the total cost of a micro- processor. It is expected that new automated testing techniques will be de- veloped to speed this process, and that the testing devices themselves will be based on microcomputer systems. Assembly labor will decline as LSI tech- niques give way to very large-scale integration, and computer-aided design techniques will be used in the initial phases of microprocessor development.

These techniques will lead to a level of automation where the design, produc tion, and testing of microprocessor will be controlled by microcomputer systems with very little, human intervention, N As a result of these factors, an 8-bit CPU should cost less than $20 by the mid 1980 + s. In commercial grade and large quantities, a 16-bit CPU will cost less than $50, and a complete 16 -bit microcomputer system will cost less than $200. Particular microprocessors that become very popular and are used in a variety of applications in large volume may well reach the $1 to 5 range.

Tabie 15 shows the estimated volume and value of the microcomputer market for the years 1978 and 1982 with a breakdown by word length, execu- tion speed, and application areas, `s Value, million $ Quantity, million Microcomputer breakdown 1978 1982 1978 1982 486.0 1082.0 2.40 5.92 By word length, bits s 4 120.0 208.0 1.76 3.86 8 185.0 364.0 0.48 1.46 12 11.7 20.4 0.02 0.05 z 16 169.0 489.0 0.14 0.56 By execution speed, μsec <0.1 0.6 <0.01 <0.01 6.2 90._7 0.1-1.0 205.7 0.06 0.18 132.2 1-10 347.0 0.15 0.63 120.5 10-100 243.0 0.51 1.63 > 100 142.0 280.0 1.68 3.49 By application Business /education 108.0 222, 0 0.98 2.10 Communication - 131.0 0.07 0.21 71.2 Consumer/auto 27.2 60.2 0.84 2.08 Computer 148.0 374.0 0.37 1.11 Government/military 47.1 124,0 0.02 0.05 Industrial 69.5 120.0 0.07 0.16 Instrumentation/medical 14.2 50.8 0.04 0.21 (Numbers are rounded off) E Memory Technology Projections This subsection describes the characteristics of memory technologies expected in the 1980 time frame with applicability to avionics.

Bipolar semiconductor, — It is expected that a 4, 096-bit bipolar RAM with access times in the 10 nsec region will be available by 1980: An I2 4K-bit memory array with 100 nsec access time is expected to be available in sample quantities by 1976. The present power dissipation of 0, 5 mW/bit will most likely be cut in half by 1980. It is expected that by 1980 RAM. s with 16K-bits per chip will be readily available. It is also expected that non- volatile semiconductor RAM's could be developed of 2 to 4K bits/chip and I read/write speeds in the 200-nsec range by 1980.

CMOS semiconductor. - CMOS RAM's with access times as low as 40 nsec and complexities of 1K bits per chip are available now; by 1980 4K RAFT RAM's should be available, MNOS EAROM'S. -- MNOS EAROM's of 8K bits per chip are currently under development and extension to 16K bits should be possible by 1980.

Charge- coupled device (CCD), -- A 64K-bit charged coupled device (CCD) should be possible by 1980. CCD's operating at 20 MHz and with access times in the l to 10 μsec range should also be available for high-speed applications. Because of their serial operation, they will be used mostly for secondary storage.

Magnetic bubble memories, -- Magnetic bubble memories have been constructed using single crystal garnet films and amorphous cobalt films.

The presently more difficult to process amorphous material promises higher speed and can be put on almol t any substrate material.

Bubble technology is very new and the eventual characteristi.cs are diffi- cult to predict. Density projections for magnetic bubbles range from 10 6 to 10 9 bits /in2 by 1980, Projected access times are in the 2 to 10 μsec range, and transfer rates are estimated at 2 to 5 NIH,z, Also, a 100K-bit memory 4 has been developed on a 300 by 300 mil area. This technology may become useful for avionics at some point, but it does not appear applicable to general aviation in the 1980-1990 time frame.

a Optical memories. -- Optical memories are being researched using both storage. The major problems in this area are real image and holographic concerned with the storage media; a permanent, ,yet selectively eraseable, storage medium is needed. Techniques which may be viable in the 1980 time r frame are given in Table 16 (ref, 37). Two of these approaches are described in detail in Appendix R. Optical memories will be aimed at the secondar y and mass memory- areas of the memory hierarchy. Optical memories along with

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bubbles are a threat to existing magnetic technologies for these categories.

There does not, however, appear to be an application to general-aviation i avionics in the foreseeable future.

i - J - — n , ow low low Imi ow now TABLE 16., CHARACTERISTICS OF OPTICAL STORAGE MEDIA Storage Write / Memory density, Read , Problems material er_ asc bits/cm Optical Optical ^^ Gradual data loss Photochromic ( 106 absorption absorption (alkali halides) Ferro- Current sense- Resolution-lifetime Ferroelectrc 104 i electric destruction (B'aTiO ) 3 ^ ° Lou readout efficiency Ferromagnetic 107 Thermal Magneto-optic MnBi Thermoplastic Thermal Optical Resolution-efficiency hologram Cathode life beam Semiconductor 107 Electron Optical capacitors beam deflection . ___ -A Memor Ttechnolo ro ec .ions summary. - The characteristics of selected nonmovable memory technologies with current or potential applica- bility to avionics are qualitatively summarized in Table 17.

TABLE 17. - CHARACTERISTICS OF MAJOR NONMOVABLE STORAGE TECHNOLOGIES' WITII APPLICABILITY TO AVIONICS o P, 0) Cd L) , bZ Storage o o o zn 3 P- o P technology Semiconductor VII H L R/WM H H Bipolar H L R /WM H M MOS L C-MOS H VL L R/WM tI M SOS/MOS H L L R/WM H M_ L CCD VL L R/WM M L H M L L Amorphous NO M Magnetic Core H H M M L NO Plated wire H H M M L NO ,L L Bubble L NO L• L tOptical Holographic VL NO VL $ M L t' The major characteristics for selected on-line bulk memo] ogies expected in the 1980 time frame are quantitatively summ, Table'18.

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TABLE 18, EXPECTED 1980 ON-LINE BULK

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MEMORY CHARACTERISTICS Average Read/write Shift/bit access, cycle, raise, Volatile psec MHz μsec Charge- coupled 1 N /A 10 Yes devices' Semiconductor 10 2 No BORAN[ N/A Yes Bipolar semi- 0.05 0.08 conductor RAM 0.3 N/A Yes MOS &^miobn- 0.15 ductor RAM N/A 2 No Magnetic 10 bubbles Fixed head 9 x 10 3 N/A 0,2 No disk/drum N/A 0.08 No Movable 0. 2 x 10 6 head disk N/A No Magnetic core 0.3 0.4 Electron beam I 4 N/A 10 No divides the total market for nonmovable storage media into the Table 19 major technology areas for the year 1978. The total market (captive plus noncaptive) . for semiconductor memories will be about $1, 3 billion or 459 i billion bits in 1978.

{ i TABLE 19, — MEMORY MARKET SUMMARY Component price, Memory Quantity, Value, million $ c/bit technology billion bits i Semiconductor 459 1338 0.29 667 0.63 Bin nlar 106 MOs 279 562 0, 20 SOS 13 64 0.52 0.08 CCD 61 45 Magnetic 74 309 0.42 Core 48 136 0,29 Plated wire 16 156 0.94 17 0. 1`7` Bubble 10 Other 4 1.53 Total 537 0.32 Among all the memory technologies - core, semiconductor, disk, drum, plated wire, and the more recent memory types only semiconductors will show significant advances during this decade. These advances are size reduction, capacity increase, speed improvement, reliability improvement, and fabrication cost and price decreases. Presently almost every new com- puter regardless of size contains semiconductor memory or may have a choice between semiconductor and core memory._ In addition to advantages in terms of perforrzance, price and reliability, semiconductor memories offer significant advantages in other parts of the system because of their easier interfacing of logic and memory, In magnetic memory, the incom- patibility of the memory signals with the seaiconductor logic and the high price of the interface electronics puts economic restrictions on the system rr organization, Progress in MOS technology (Figure 13) is best illustrated by plotting the figure of merit of commercial RAM's versus the year of production (Figure ,13a) Figure of merit is the product of chip area (mill dissipation (W), and access time (Ijsec) divided by the number of bits, Cost/bit curve`, (b) does not truly reflect the increase in performance with time, For C l MID a. RAM figure of merit (M)a versus years of production p E 1101 Static memories b^ C) 2102o l:o 2102A a ^ i l ^^ 2107 2115 0 S n 2107B 0 1 o Dynamic memories RAM \ _ ^ _ N 0.01 196° 7u 71 72 73 74 75 76 77 78 79 80 Years of production U 0.1 M= Area X Power Dissipation X Access Time a" Hits h. The Designations Above Identifv a Famiiy or intet Memory Devices that are Tvpical of Current Pro- duction RAIVYs.

0.01 example, a single bit of storage in 1975 requires far less power and can be accessed much faster than the same bit in 1970.

I/O Module Technology Projection There has been very little discussion in this study of sensors and servos because this is a computer technology study and is not primarily concerned with peripherals common to analog as well as digital control systems. However, the development of both sensors and servos designed .. a to operate specifically in conjunction with digital systems can be expected to receive an increasing amount of attention. This focus on I/O has already begun as processor costs, performance, and reliability Have improved markedly.

It appears that direct digital sensor and servo development will not achieve a breakthrough equivalent to that of the microprocessor in the com- putational area; data converters are expected to be an important part of digital_ systems in the 19801 s.

Digital to analog (D/A) and analog to digital (A/D) converters are getting faster, s,^naller, and cheaper. The trend seems to be towards pack- ing more and more electronics into small packages. Instead of just getting an A/D converter in a module, a whole data-acquisition system is packaged as one, including an A/D converter, multiplexer, sample-and-hold amplifier A and logic. Often even memory and buffer, amplifiers are included. This field is still in its infancy; as it matures, the integration and miniaturization will continue. As shown in Figure 14, by 1980 more than half the data converters sold will be monolithic, about a,quarter will be hybrid, and 5 to 10 percent will be encapsulated modular units. Unlike what happened with operational amplifiers, market dominance by monolithics will be consider- ably slower, to develop, 1 } s .f i D A / 4 D / D/A A/D ................... ......................... .......................... .......................... . ................... . .......................... .......................... .......................... ........................... ......................... ...................... ........................... ........................ ........................ ............................ .................. ........................ ........................ ......................... ......................... ........................... .......................... ........................ ........................... .......................... ........................ ......................... ......................... ........................... ........................ .......................... .. ................ ................... ........................ .................. ........................ .......................... ...................... ........................ ........................... . .............. ......................... ........... . ............... ........................ ............... . .. ......................... ........................... .......................... ....................... ...... . ......................... .........................

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U Q Modular Hybrid Monolithic Key: Figure 14. - Potential Growth of Modular, EIybrid, and Monolithic,A/D and D/A Converters a i n: Fiber Optics Data Transmission A development that will have a major impact on computer systems of all sizes in the future is the use of fiber optics technology for data communica- tions. This technology is in its infancy now, but will see rapidly increasing use as its strong inherent advantages over electrical transmission systems are realized.

Fiber optics technology is based upon the propagation of optical energy through small-diameter, flexible-fiber wave guides multiple internal by reflections, Conventional optical fibers are comprised of a transparent cone material (usually glass or plastic) with a cladding that has a lower index of refraction, Light that enters the fiber within its acceptance angle will be conducted by multiple internal_ reflections at this boundary. This effect allows light to be "piped" wherever desired.

A fiber optic data transmission system is composed of a light source that can be modulated (LED's and semiconductor lasers are being used), a fiber optic bundle or cable and its associated connectors and couplers, and a photodetector. With the proper electrical interface, this system can directly replace an electrical wire or cable for data transmission. There are several important advantages in doing this, the most important of which are summarized in the following paragraphs, Optical fibers have a theoretical bandwidth in the`Gigahertz range, Current demonstration systems have shown reliable transmission in the 10_ to 20 MHz region, and some laboratory systems have exceeded 100 MHz.

This capacity allows extensive use of data multiplexing, which produces major savings in component count, power, size, weight, and cost. Also, the high bandwidth capabilities enhance the reliability and maintainability of data communications systems by permitting more imaginative data multi- i plexing schemes. This results in fewer cables simpler connectors and and allows redundant data paths.

Optical fibers are made of glass, plastic, or other dielectric materials; as a result, they do not pick up electrical noise. This RFl/EMI noise immunity eliminatesthe need for extensive shielding and careful cable routing present with conventional electrical cables.

Fiber optic cables show excellent immunity to heat (glass fibers), humidity, corrosive atmospheres, salt spray, and vibration. Performance in various strength tests (tensile, shear, abrasive, crush, etc.) has varied, but is more a function of cable structure and materials than the optical fibers themselves.

i y Low levels of optical energy are usQd to transmit information in a fiber optic transmission system; thus, loose,or damaged connections cannot spark or ignite combustible vapors or materials.

A common electrical ground is unnecessary, for a fiber optics data link.

This eliminates the problems of ground loops, voltage offsets, and ground noise pickup. Short circuits and the possibility of spreading_ damage through circuit loading are also eliminated. This attribute of electrical isolation .

alone may justify use of the technology for intrasystem communications over short distances.

Due to the nonradiative nature of fiber optic data transmission, there is no crosstalk between data cables. This also results in vastly improved data security as it is very difficult to tap a fiber optic data cable without break- ing the link.

Reliability is vital in avionics systems. This is more easily achieved with redundant data paths using fiber optics technology. A short circuit in a branch of a redundant electrical path can destroy the entire link through circuit loading. The normal failure mode in a fiber optic cable is equiva- lent to an electrical open circuit, which would have virtually no effect on the alternate transmission path.

There are a variety of applications areas where the advantages of fiber optic technology are important, Military and commercial avionics data transmission systems are a logical choice for near-term use of this tech- nology as the required cable lengths are short such that very low-loss optical fibers are not required. The required data rates are also relatively low and easily achievable with current devices.

In one demonstration system, the electrical data cables associated with the navigation and weapons delivery system of an A-7 aircraft were replaced with fiber optics,, Results were revealing. The number of cables was re- duced, from 302 to 13, the total length of cabling was reduced from 4832 to 260 feet, and the total cable and connector weight was reduced from 82 to 3, 6 pounds, Also the total cost for connectors and cables was reduced from $7, 9K to $1. 1K. The performance of the system is excellent, Also, tests were conducted that demonstrated the RFL/EMI noise immunity of fiber optic systems.

The total lack of crosstalk and spark hazard greatly simplifies the cable routing task in aircraft design, This is a significant cost ,savings in the development of new aircraft systems and in the retrofit of new avionics to aircraft. It is clear that military avionics systems will be one of existing the af:,phcations areas for fiber optics. By the 1980'5, fiber optic data com- inixnications be common rather than the exception in military avionics systems.

t i As with'any developing technology, there are significant problems limiting the immediate application of fiber optics technology. Most of the problems purely with the level of maturity of the technology are associated and not with anyinherent disadvantages, Availalsi ? ity, standardization, and component costs are typical of the problem areas in fiber optics that will be solved as the technology matures; none of the currently known problems seem to be insurmountable. The area of coupling for multi-drop data bus applications is a significant problem area that will take innovation, research, and development to overcome. The problems of ionizing radiation (lumin i escence and transmissivity degradation) are being attacked through basic' materials research. Maintenance tools and techniques must also be devel- oped to install, repair and modify fiber optic systems in the field, Also, to exploit the advantages of fiber optic technology, new approaches to computer system architecture and data bussing must be developed. These techniques must take advantage of the high bandwidth capabilities in optical fibers, The development of these extremely complex techniques and their application to

t

general-aviation requirements doe not appear likely in the 1980's, but may be achieved in the 1990 era,

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OPERATOR/COMPUTER INTERFACE TECHNOLOGY PROJECTION As the computer becomes more of a direct user device, man/machine Methodologies for analyzing control and interfaces becomes critical.

display parameters based on the optimal control model, of a human operator have been under active development for the past decade (ref, 38), These methodologies appear to serve as useful tools for analyzing the efforts of r specific- controls and displays on system performance and r feliability, The common conclusion offeredby most of the recent studies is that a significant performance improvement is provided with integrated and interactive control/ display systems. The specific display technologied anticipated to be most used during the next` decade are discussed in the following paragraphs, Prices of the fastest growing technologies — LED's, gas discharge panels and liquid crystals — will decline significantly over the next five years due to increased use and technological advances. 'Thetie technologies are IC compatible and require less decode and drive circuitry to operate, which also contributes to the declining cost.

Liquid crystals and gas-discharge panels will be used increasingly in portable calculator applications as both' types of devices can be powered dil ectly by a CMOS chip and offer better legibility than LED's, The liquid k Ii I I I crystal temperature problems are being solved, making them more compe- titive with LED' s and gas-discharge panels for use in calculators. Also electronic watches are a primary application area for liquid crystals. LED' s cannot compete with liquid crystals in this application due to their higher cost, high power requirements, and a need for more decode and drive cir- cuitry. LCD' s will be the least expensive display.

The GDP will continue to be used for computer terminal applications and will compete with CRT's for the high-price end of the market. Significant progress has been made in gas-discharge panel fabrication techniques, cir- cuit design, and gray-scale control for the consumer TV market. In addi- tion, IC's for driving the GDP are rapidly improving in capability and are coming down in cost. These factors plus the effort being expended on flat panel TV make it likely that GDP will Le used for consumer TV sets.

The market for flat panel alpha-numeric displays is estimated to be 800 million by 1980. To achieve a significant market penetration, active matrix display will require completely integrated drive circuits with the display, Long-term plans are being made by both industry and government in the area of active matrix displays. For example, Hughes has developed a 1 by 1 inch matrix display with 100 by 100 elements. The display uses liquid crystal for the passive display element and is driven by a monolithic semi- ?

i conductor chip. (See Appendix I).: The ultimate size of the display will not be limited by the individual chip size but by techniques of assembling mod ular arrays. However, it is not expected that silicon-based matrixes will be used for very large areadisplays; thirty inch diagonal displays are too great for modularization. 3 i a _ =ate Silicon technology is in a maturing phase and approaching the end of its rapid growth. As this technology begins to saturate, the next breakthrough will come from thin-film technology. Thin-film integrated circuits have a much lower cost than silicone integrated circuits due to the inexpensive substrate and starting materials and the single-step batch processing, t Use of thin-film transistors (TFT) for display drive and address c1r- cuitry will be continued, It will have a wide range of application due to its ruggedness, reliability, long life features, and low cost, Current Th'T matrix drives are 6 by 6 inches for liquid crystal and electroiuminescent panels, Larger pane sizes are expected in the future.

The incandescent indicator display market will not be severely impacted by the new technologies because simple indicator lights will continue to be used extensively in control equipment applications. While planar incan- descent displays can be produced, equipment designers are afraid of filament M< breakage. Therefore, segmented incandescent panel display production is declining and is being replaced by LED's, The CRT is a mature technology and marginal improvements in per- formance life and reliability can be expected, but no significant cost reductions are predicted. The primary disadvantages of a CRT are its bulk, lack of memory, and high-voltage requirements. However, there is no serious challenger to the CRT for many types of displays, and it is the most cost-effective solution for a data display in the region of 500 to 1000 char- acters and above.

t COMPUTER SYSTEM ARCHITECTURE TECHNOLOGY PROJECTION At one time the driving force behind system level technology was the business data processing industry, The goal of development was to obtain maximum capability in a single central processing system. This lead to the development of extremely high-speed processors, and the eventual trend toward centralized multiprocessors. The development of languages and software was also directed to this type of system. This trend has now sub- sided.

The primary driving force in system architecture is now the so-called small user. This has led to increased emphasis on smaller, more flexible systems, which can be upgraded as requirements change. The current interest in the area of distributed microprocessor systems in one specific example of this trend. C(brrespondingly, increased effort in the development of software and interconnection technology for modular computer systems can be expected in the next decade.

The role of military avionics should not be overlooked in predicting the driving forces behind system level technology. In many cases military avionics maybe directly applicable to general aviation with only minor seal- ing down of requirements. Because there is a trend in military avionics systems toward distributed, processor systems,_ general-aviation avionics will undoubtedly follow this trend.;_ The concept of multiprocessor networks is well suited for microproces- sors (μl's). First, microproecessors are able to perform many'' dedicated functions at low cost without the use of supporting, electronics or special I/O chips They can be used as a universal standard component for literally any definable task, particularly data gathering. Second, the microprocessor, - 12$

T 1 l r SECTION 8 RISK IDENTIFICATION/TECHNOLOGY DEVELOPMENT As delineated in Section 5, a number of technologies are being developed that can be directly applied to general-aviation requirements. In most cases, the driving forces brought to bear by the large-volume users suer, as auto- motive and process control equipment-,=anufacturers will result in continued deveiopment in directions most desirable for general aviation, i. e, in- creased temperature range, improved reliability, and reduced cost. In view of the overwhelming effort of the large-volume users to satisfy many of j the same hardware requirements as the general-aviation avionics require- for NASA to expend additional effort in ments, it does not appear necessary the semiconductor, circuit, or component development areas, except for display and sensor technology.

i In the field of overall system technology, ,however, it does not seem that ether agencies will contribute a great deal toward the improvement of general- aviation avionics. Even though bussing, multiprocessor, and-fault tolerant architecture technologies may be developed for other uses, the effective use of these in producing SsLfer and lower-cost general aviation systems will a require effort specifically orientedtoward general-aviation problems, s r3 DISPLAYS •a Passive displays. - The most promising passive display material is liquid crystal with on-site memory (.see Appendix I), which is being devel- oped by botli Hughes Aircraft and Westinghouse. Currently, there appears' to be adequate development funding available. a considerable portion of which: is aimed at military applications. This should ensure that displays suitable for aircraft use will become available. The risk lies in being able to adapt the military technology to the general-aviation cost and reliability require- ments.

The next most promising class of passive display materials are the electrophonetics (EPID I s), with the colloidal-sized T10 particles (Appendix K) as the best candidate. As there does not appear to be a specific aircraft- oriented program on this material, there is, even more risk than in the case of LCD' s that a product suitable for general aviation will result.

Because of the current effort being expended on,GPD' s Active displays. -- for TV use, there is a high probability that GPD' s with performance suitable for general-aviation displays will be available in the 1980 1 s. The risks in involved are thesuitability of the physical configuration (size mostly) and the question of how much ambient light suppression and shielding will be required.

y ry LED' s will be available in large volume and many types, but because of the relatively high dritTe currents required for high brilliance, there are some doubts as to the development of the on-site memory necessary for high-resolution matrix displays. There is no doubt as to the availability of - suitable alphanumeric displays.

- ° 131 i l } Recommendations. - As indicated, there are several promising tech- niques for _application to general-aviation displays in advanced development.

There is risk, however, that none of these techniques will be developed into a form particularly adapted to general aviation unless specifically oriented programs are initiated. Therefore, in planning future general-aviation programs, it is recommended that NASA consider a two-step program to: 1 Define the formats and dynamic performance requirements of a 4-inch multiformat display for high-level general-aviation aircraft.

2. Sponsor the design and manufacture of prototype flat-panel displays to meet the requirements developed in Task I.

a OVERALL GENERAL A VIATION A VIONIC SYSTEM CONFIGURATIONS) y The many hardware, software, and architecture techniques discussed and cited as potentially applicable to general aviation give assurance that the performance of current functions can be improved, that desirable new functions can be added, and that cost can be reduced during the next ten years. There remains, however, the question of how best to combine the technologies and their resultant functions into overall systems that will significantly improve the safety and utility of general-aviation aircraft: It does not seem reasonable to assume that the improved overall system a technology can be adapted from on-going work on either military or com mercial aviation. There are many differences, most notably in the pilot qualification and economic areas, that strongly indicate that general- ^viation avionics system configuration must be considered as a unique area of development. According, it is recommended that NASA pursue programs j to • Determine the functional requirements of improved avionics systems for general-aviation aircraft of various classes Conduct design studies to define the characteristics (con- • figuration, cost, weight, etc. ) of candidate systems these will meet the established requirements.

y i

~^

T REFERENCES 1. Winblade, Roger L.; and Westfall, Judy A.: NASA General Aviation Research Overview. 750500, 1975.

2. Staff. of,Decision Services Corp.: Analysis of the General Avionics Requirements for the 1980's. NASA CR-137629, 1974.

3. Bender, M. A. et al: Digital Flight Control `systems for Tactical Flights. ' AF Tech. Rep, AFFDI,-TR-74-69, AF Contract F33615-72- C-1058, July 1974, 4. Borow, M. S. et al: Navy Digital Flight Control System Development.

IToneywell Doc. 21857-FR,_ Contract N62269 = 72-C-0141, NADC Warminster, PA, 5, Anon: Time Reference Scanning Beam Microwave Landing System, U. S. Proposal for a Non-Visual Precision Approach and Guidance System, U. S. Dept.' of Transportation, Federal Aviation Administration.

Driscoll, Norman R.: Effects of a Simple' Stability Augmentation 6.

System on the Performance of Non-Instrument-Qrza.lified Light Aircraft Pilot During Instrument Flight, Langley Research Center, NASA, NASA TN D-3970, May 1967.

a 7. Anon. Microprocessor Directory and Microcomputer Systems Directory, Electronic Design News, 20 November 1975.

i 8. Aronson, Richard L'.: Line-Sharing Systems for Plant Monitoring and Control. Control Engineering, Jan. 1971, M y s } k S Solid State Optical Designs Set the Encoder Pace, Andreiev, N.: 9.

Control Engineering, May 1975.

Directory. EDN 3 Robert H. (Ed, ); Microprocessor Cushman, 10.

Nov, 20, 1974.

i Microprocessors in Unconventional Architectures, 11. Johnson, Melvin D.: Proc, Asilomar Conf, on Circuits, Systems, and Computers, December 1974, i Lampson, Butler W.; A Scheduling Philosophy for Multiprocessing 12..

Systems. Cormmunications of the ACM, May 1968.

i Flores, Ivan: Lookahead Control in the IBM System 370 Model 165 13, Computer, November 1974, Tiecher, S.; and Hughes, L.: Implementation of 'a Hardware Floating 14, Point Processor, Computer Design, May 1972.

Svigals,_ J.: IBM7070 Data Processing System, 15. Proc. WJCC, 1959, 16, Staff of the Modular Computer Corporation: The Input/Output Micro- 307-32002-000, 1975, processor.

Y 17. Hancock, R. J,: Microprogrammed Disk Peripheral Control _Units, Proc. IEEE COMPCON, 1971, a 18. Chung, ,David H.;, and Hay, Don B.: The T-Box: A Lo,,--,-Cost Software- ... ...

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Based Interface, Electronics, March 13, 1972, ,1 19, Anon, Computer Automation; ,Distributed I,/O Systems User's Manual, 91-53629-OOAO, April 1975, 20.

Steele, J. M.; and Mattson, R. C. : Architecture of a Universal Communications Processor, Computer Design, Nov, 1973, Deerfield, Allan J.: Architectural Study of a Distributed Fetch 21, Computer, NAECON Record, May 1971, 22. Thurber, K. J.: Introduction to Associative and Parallel Processors, CICS 5299 Class Notes, U. of Minnesota, 1975.

Enslow,, Philip H. (Ede ): Multiprocessors and Parallel Processors.

23.

John Wiley and Sons, 1974.

24. Heart, F. E.; C)rnstein, S. M. Crowther, W. R, and Barker, W. B., A New Minicomputer/Multiprocessor for the ARPA Network, Proc, NCC, 1973.

25. Jensen, E. Douglas: A Modular Computer System for Real-Time Control, Proc. Symposium on Computer Architecture, January 1975.

6.Wulf, ffilliam A.; and C. Gordon Bell; C. MMP--A Multi-Mini- Processor: Proc. FJCC, 1972.

rs 7.Carp, P.: Origin, Development, and Status of the ARPA Network, t Proc. IEEE COMPCON, February 1973.

y 28. Farber, David J. ;'Feldman,' Julian; Heinrich, Frank R.; Hopwood, Marsha D,; Larson, Kenneth C.; Loomis, -Donald C, and Rowe, Lawrence. A The Distributed Computing System, Proc, IEEE COMPCON, February 1973.

z The SRI Speech Understanding Systems, IEEE 29. Walker, Donald E.: Transactions on Acoustics, Speech, and Signal Processing, Oct. 1975, 30. Design, 1975. Digital Dec.

Anon: Printers/Plotters Rosenthal; Rabiner ; Schafer; Cumminsky; and Flanagan: A Multiline 31.

Computer Voice Response System Utilizing ADPCM Coded Speech.

IEEE Transactions on Acoustics, Speech, and Signal Processing, Oct. 1974.

Incremental Servos for Digital System Compatibility.

32. Bailey, _ S. J.: Control Engineering, Jan. 1975.

Display Devices; A Perspective on Status and 33. Reingold, Irving: Proceedings of the S. I. D. , Vol, 15 -2, Second Quarter Availability.

1974, pp. 63-74.

Matrix TV Displays; System and Circuit 34. Van Raalte, J. A.: IEEE Transactions on Consumer Electronics, Vol. CE-21, Problems.

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35. Summary; New Techniques in Video Displays. IEEE Sobel, Alan: Transactions on Consumer Electronics, Vol. CE-21, -No. 3, Aug. 1975, 290-297.

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Large Scale Integration for Display Screens. IEEE Brody, T. P.: 36.

Transactions on Consumer Electronics, Vol. CE-21, No. 3, Aug 1975, 260-287, pp .

APPENDIX A This appendix summarizes the salient characteristics for representative circuit types listed in Table 6 of the main body of the report.

Epitaxial Collector Structure The EPI collector device structure is the most common bipolar processing method in use today. It has resulted in a large number of unique circuit forms as sho n in Fig ure Al. The most promising of these for future applications are IZL and DCT^L.

The size and low-power advantages of I2 L come directly from shrLnking the old direct coupled transistor logic (DCTL) into a single complementary transistor equivalent.

As shown in Figure Al, a vertical NPN transistor with multiple collectors operates as an inverter. A lateral PNP transistor serves both as a current source and load. Note that no ohmic resistors are required for either the source or load function. In a typical TTL gate, six to eight area consuming transistors are required.

C 1 C 2 C3 Outputs Input Figure Al. 12 L Gate Note also that the base of the multicollector NPN transistor is common to the collec- tor of the lateral PNP current source, and that the base of the current source is common ^l with the emitter of the NPN transistor. This means that both transistors can be fitted into the area of a single transistor without requirements for device isolation or intracell I ., wiring. This gives rise to the term-merged transistor logic (AITL), which is another name for I2 L. Other names used for logic types that are basically I 2 L are: I • _ CHL -- Current Hogging Logic C3 L -- Complementary Constant Current Logic

•

• SFL -- Sub°'krate Fed Logic The essential feature of IZL logic is the use of a transistor as the current source and load rather than the conventional resistor. All units are powered by these transistors, and the current that reaches each unit is simply the total injector current multiplied by Al i

Appendix A the a of the PNP, and divided by the number of units associated with the injector. Thus, by altering the current into the injector, a wide range of speed-power operation can be achieved.

12L devices fabricated by conventional bipolar processes are presently limited to a delay of 10 to 30 risec/gate. If the process is optimized for I2 L, it is felt that delays of 1 nsec can be achieved. I2 L devices can be included on the same chip with Schottky TTL, ECL, linear circuitry or other circuit forms because of process similarity. This feature can be very useful in the reduction or elimination of special interface circuit requirements The only standard product presently available in 1 2 L is the SBPO400 by TI, This 4-bit processor element chip contains over 1450 gates and is fully TTL compatible, Triple Diffusion Structure The triple diffusion device structure (3D) is a relic in integrated circuit technology that has been recently revived for LSI applications, This structure, introduced in the early 1960's, offered the most direct and simplest means of producing electrically iso- lated transistors and resistors on a chip. This structure gave way to the epitaxial struc- ture due to the difficulty in controlling the light collector diffusion required, with the availability of ion implantation, this deposition can now be controlled within 5 percent, and this structure is again a viable choice. This process allows both NPN and PNP transistors as well as self-isolated resistors to be fabricated on the same chip.

The simplicity of the process required in 3D allows very large chips to be fabricated with reasonable yields. To date, over 50 LSI designs have been produced with chip sizes as large as 300 by 300 mils. The high density offered by 3D has allowed these chips to contain from 2000 to 20, 000 devices per chip.

Presently two circuit forms employ the triple diffused structure, emitter follower logic (EFL), and emitter coupled logic (ECL). Note that ECL can be realized with any of the three bipolar structures, Most of the LSI effort to date has been in EFL, Basic EFL gates are shown in Figure A2. Note that both PNP and NPN transistors are employed to give wire-AND and wire-OR functions, EFL presently operates in the 5- to 10-nsec speed range (like TTL), but exhibits -power and size advantages over TTL, which is fabricated using the standard EPI struc- ture,_; While not as dense as 12 L, EFL does not require the tolerance on current levels of I2 L and is thus less sensitive to low-level defects that cause leakage, As a result, much larger chips can be fabricated with good yield using EFL.

Presently under investigation is the combination of EFL and CIVIL (current mode logic) on the same chip. The reason for such a development is that while EFL has more - power to perform combinatorial logic, CML performs register logic better than EFL, Such a combination would allow speed and density advantages over the use of a single circuit form.

Oxide Isolation Structures Bipolar transistors involve bulk phenomena and, therefore, must be isolated from one another when combined on one integrated circuit chip. In the EPI collector structure; this isolation is accomplished by diffusion to form P-N junctions between devices.;- Be- cause the diffusion areas spread laterally as wellas into the wafer, this form of isolation consumes considerable chip area. Thus, in EPI structures, most attempts to increase ) -z A2, AGE PQO'?- Qj^ALI

Appendix A cc A.B- C C A B AND Gate C A 0 B A+B+C OR Gate (omit resistor when output to R/S FF) Figure A2. Basic EFL Gates density involve the use of very thin epitaxial layers and minimization of the size and number of components :?equired for a logic function.

With oxide isolation structures, diffusion isolation is replaced by a form of dielectric isolation where material is removed around each device. This can be accomplished with a much narrower isolation region than results from diffusion, The material is removed by an etch, which does not have as much lateral movement as in diffusion. The use of such an isolation wall eliminates the need for a collector sinker diffusion, thus saving additional area.

Specific names given to this basic structure are isoplanar (Fairchild), VIP (Motorola), and V-ATE (Raytheon). While there are differences in each, the result is the reduction in device geometry through advanced isolation techniques.

However, while this structure results in area advantages, the processing steps are more critical, and yield over a given area is not as high as with the standard EPI structure.

While nearly all circuit forins that are fabricated using the standard EPI process can be made with oxide isolation, only T L, ECL, and 12L have employed this option to date. Of these, L has already been discussed, and the other two are commonly known circuit forms, not warranting further elaboration here.

The basic impact of the oxide isolation structure is that it provides better device ^' isolation, both in tern-is of leakage capacitance and area.

Thus, smaller chips with improved speed-power products can be achieved for a given complex function. The process control is more stringent, thus resulting in lower yield over a'given area. The A3

{{1^ I Appendix A choice of which structure to use will be a function of the degree of process control that evolves and/or the price per function that is tolerable, Metal Oxide Semiconductor Field Effect Transistors (MOSFET) The field effect transistor is a majority carrier device where the current flow is modulated by an electric field rather than gate current. Unlike bipolar technology where most device characteristics are a function of diffusion processes, the MOS device is primarily dependent upon the geometry of the gate and its insulation structure. Because t1l e basic phenomena are surface related, surface impurities are much more critical.

The main advantages of MOS over bipolar technology are; • Smaller device geometry • Lower power dissipation • Higher vields due to fewer process steps • Use of cross-iinder conduction paths which reduce requirement for-multilayer metallization The main disadvantages-of MOS with respect to bipolar are; • Slower switching speed • Limited chip-drive capability i At present, there are three basic logic configurations in which MOS can be obtained iu low-cost, high-deris ty arrays: • Static • Dynamic • Complementary Conventional static or d-c circuits employ circuit forms similar to those used in bipolar circuits, and a; direct path exists from the power supply to ground through a resistance when the gate has been turned on, The basic principle of dynamic logic is the elimination, through pulse techniques, of this d-c pa^h between power and ground. This is accomplished by multi.phase clocking of the load devices. Dvnaniic logic has device size, speed, and power advantages over static MOS, The majo drawbacks of dynamic logic are the required minimum clocking rate (to preserve data integrity) and the difficulty of generating and distributing high- speed, high-voltage clock pulses. These disadvantages have limited dynamic MOS mainly to memory or register arrays, with random logic primarily realized in static form.

In complementary '1,IOS, both P-channel and N-channel transistors are formed on the monolithic substrate and are arranged such that very low power is dissipated in the logic, `Phis will be discussed in a special section on CMOS.

Of the circuit forms shown in Figure A3 for MOSFET structures, P-MOS is falling from use and will f ilerefore not be discussed in any detail. Very few new designs are expected to enzploN P- biOS:, The main reasons for this decline are the incompatibility a with TTL and the emergence of N-MOS, j ORIGINAL 'PAGE IS A4 { I f" POOR QUA L ITY Substrate Silicon on material Silicon substrate Basic device Bipolar MOS MOS type Primary Oxide EPI y device 3D MOSFET CCD isolation collector /1 structures 3 2 EFL T PMOS Surface NMOS T L L j ro

L

T2 ECL ECL NMOS Buried CMOs R.

r• k L TRL 12L CIVIL CMOs Circuit forms DIMOS T2LS ECL DMOS DTL VMOS Q Q RT L CIVIL 12L DCT2L "Y.

Semiconductor Technologies Figure A3, A ppe ndix A N-Channel MOS (NMOS). - N-Channel MOS circuits possess a carrier mobility that higher than that available with P-Channel circuits and, therefore, they exhibit is much higher speed characteristics. This was realized years ago, and attempts were made at that time to process N-Channel devices, Because N-Channel devices are much more susceptible to surface impurities and because process controls were not very good, this process was dropped in favor of PMOS. After years of experience in processing PMOS, the processes became very clean and it was found that NMOS could be economically pro- new circuit starts are in NMOS. As an example, in duced. In recent years, almost all 1974, nine of the 10 producers of the 4K 'MOS RAM used N-Channel devices.

Most N-Channel devices today employ the self-aligned silicon gate process rather than the area-consuming metal gate process, As shown in figure 3 of the main body speed/power product in a of the report NMOS can operate in the 10 nsec/gate region with the 10 pj range.: With a 6 to 14 milt/gate, NMOS is also a high density LSI technology.

Because of the process simplicity and widespread experience in this technology, NIV'lOS will see widespread use in_LSI developments.

a A number- of alternate structures have been postulated to further improve the char- acteristics of NMOS; two of these are DMOS and VMOS.

i Double- diffused (MOS (DMOS). - Double-diffused MOS technology yields a high- performance MOS transistor ma e by bipolar techniques.. It uses the time and tempera- j determine transistor parameters in contrast to the standard ture of diffusion cycles to MOS process in which characteristics are controlled by geometric tolerances. This process allows very short channels to be achieved with ordinary photolithography and 1 nsec) and high density 1_,SI circuit form. The primary results in a very high-speed (w as today , s bipolar circuits.

is that the fabrication process is nearly as complex I drawback V-Groove MOS (VMOS), - This MOS structure is also borrowed from bipolar tech- nology, and uses a preferentially etched V-shaped notch, like V-ATE, VMOS allows fabrication of high-performance transistors with very small channel lengths and twice higher packing density. Another advantage of the current density of DMOS as well as simpler processing.

VMOS over DMOS is VMOS is capable of very high-speed operation (2 nsec/gate) at very high levels of n mi12 /gate) and is competitive with bipolar I 2 L. VNIOS is most com- integration (3 to 7 monly used to fabricate N-Channel devices, but results in a two to one size reduction over the conventional NMOS structure, l Complementary metal oxide semiconductors (CMOS). - The name complementary is based on the use of both N Channel and P-Channel transistors on for this logic form the same substrate. The principal advantage of CMOS is the very low power consump shown in Figure A4, the basic gates ?

tioh (nanowatts/gate) in the quiescent state, As consist of a P-Channel device and an N-Channel device between the single power supply the input will enable one of these transistors and will disable and ground. The voltage at the other. Because the input impedance of the transistor pair is extremelyhigh (typic is consumed during the transition from a logical 0 power ally 10 12 ohms), nearly all the logical 1 when both transistors are momentarily on. Thus, the power dissipation to a of the frequency of operation.

is a' direct function the d-c power is so high that tho a-c component is not For most other logic forms, discernible, With C:IIOS, the opposite is true,: the a-c power (PAC = CV 2T) is much load off chip, 1 pfd on chip) than the nanowatts of d-c power. Because higher (at 5 pf per low frequency to greater power dissipation ranges from nearly zero at of this feature, the than TTL at a few MHz.

i A6

i Appendix A vDU F S ..

' D IN BUT N S Figure A4. Typical CMOS Inverter The advantages of CMOS include; • Low power il 0 Operation from a single power source • Logic swing's equal to supply voltage • High noise immunity (4510 supply) Insensitivity to supply (3 to 15 volts) • • High speed

• High fan-out (typically 50 loads)

• Compatibility with TTL The disadvantages of CMOS include a loss of packing density caus3d by three factors, The most significant factor is the need for guard rings around the devices to ensure high field thresholds. The second factor is the larger number of devices required to perform - a logic function in CMOS; a CMOS gate requires 2N devices, where N is the number of inputs, A single channel MOS device requires only n + i, Thirdly, the N-Channel tran- sistors have higher carrier mobility; they have roughly twic- the trans conductance of the P-Channel transistors with identical geometry. Therefore, to match the characteristics of the pair, the P-Channel device with a given channel length must have approximately twice the channel Y Ldth of the N-Channel device, Thus, not only are more devices re- quired, but only half of them can be of min rf.-Im geometry.

Most CIVIOS today uses the metal gate structure, with very few silicon gate 'devices available, If the industry solves the process problems associated with Si gate CMOS, density imprpyements will result. Presently CMOS chips are roughly twice the area of an equivalent"ll-Channel Si gate chip.

A form of CMOS that is similar to the isoplanar structure in bipolar is called DI-MOS, or DI-electric isolated 1VIOS. This structure reduces the output capacitance of the CMOSate to essentially zero offerin g improved speed and a g es power advantages g Y ^ P p P g over the more common junction isolation, A7 t _

Appendix A Charge Coupled Devices (CCD) One important offshoot of the basic MOS device structure is the Charge Coupled Device (COD) announced by Bell Telephone Laboratories in 1970, The CCD is a MOS integrated circuit shift register for analog sigi;a)s, which is made in the form of a string of MOS capacitors. The initial work was in surface channel devices, where metal elec.- trodes were placed on a silicon dioxide insulation layer over a P-type silicon substrate.

No diffusions are required for surface-channel devices. However, because of the noise caused by the trapping of charge at the Si-S02 interface, most effort is now in buried layer CCD' s, Buried layer devices are formed by selective diffusion or implantation of N-type silicon into a P-type silicon substrate In comparison to MOSFET structures, CCD's are very simple to process, and thus result in good yield over a very large area. No isolation is desired between devices, making this a very high density technology.

COD's operate as shift registers or delay lines, where the mobile charge stored within a semiconductor element is transferred to a similar, adjacent storage element by the external manipulation of voltages. The quantity of the charge can vary widely, de- pending on the voltage applied and the capacitance of the storage element, Thus CCD's can represent analog as well as digital data.

Many companies are presently developing CCD technology using a number of unique approaches, and government funding is assisting this development. A great number of these devices can be placed on a single chip. For use as digital devices, the complexity is a function of geometry and yield; for analog devices, the chip complexity is more a function of transfer efficiency as analog repeaters are difficult to fabricate. CCD's are useful in three application areas: Digital memory, The potential low cost and fast access of CCD serial memories make them candidates for replacing the slow, unreliable electromagnetic disks and drums presently in use. More discussion of these devices will be presented in the memory section, Ima gery, - In imaging, charges are introduced into the device when light from a scene is focused onto the device's surface. As in all semiconductors, the absorption of light quanta creates hole-electron pairs which, under the influence of the potential be- neath each storage electrode, are collected as a charge pocket. The quantity of charge stored is proportional to the intensity of the image. In this manner, a spatial chargL representation of the scene is stored in the device. By clocking the electrodes, the charge pockets are moved from site to site until they have all been read out.

Applications in imagery for CCD's include: • Sensors for TV .cameras • Facsimile recording i • Optical character recognition Signal processing, - The analog properties of CCD's allow this technology to be ,.sed in signal processing applications, and efforts are presently underway, to realize: e Analog delay lines • Reprogrammable filters' • Cross correlators • Fourier transform processors • Multiplexers a g m A8 i

I , Appendix A These devices can eliminate the need for D-A/A-D conversions and ca p , provide coat, size, weight and power advantages over digital_ approaches in many canes, The clock frequency control of CCD's allow analog delay lines to provide a delay ranging across several octaves, from microseconds to milliseconds per stage, By adding a conventional MOS PN junction alongside any desired CCD elements, a tapped delay line can be constructed. Signals can then be pulled out at any specified point along the line, processed, compared to other independent signals, fed back into the delay line, multiplexed, added, subtracted, and manipulated in various manners, while maintaining their analog nature at time intervals that are simply controlled a clock by frequency. Because the transfer of data between CCD elements is not completely loss- less, and because the charge in any element decays with time, the length of the array and the minimum clock frequency must be limited. The analog signals will accumulate the stage- to-stage errors and will result in degraded performance.

Silicon on Substrate (SOS) All previously discussed IC types have been fabricated on monolithic silicon wafers.

As has become obvious, most of the attempts at circuit improvements have been con- cerned with improved device isolation. With this approach, no bulk silicon is used; instead, a thin film of silicon is `grown on an insulating substrate, and silicon islands are formed bys elective etching. The transistors are then formed in the standard way except that no guard band diffusions are required. To date, almost all efforts in this technology have employed sapphire as the insulating substrate. Some work was done using Spinel, but it appears to be inferior to sapphire.

The benefits of this approach are the size r. edr ction (see Figure A5) and the lower capacitive characteristicsthat are achieved by the air isolation between devices. This isolation results in improved speed, lower power, and improved radiation tolerance.

A CMOS-SOS chip would be roughly 20 to 30 percent smaller than an equivalent N-MOS Si gate chip.

to this approach has been the difficulty in putting single-crystal The drawback to silicon on the substrate efficiently. This problem now seems under control, as standard MSI circuits are being offered for purchase. The problem stems from the difference between the crystal structure of the substrate and that of the silicon. Distortion in the silicon structure slows the minority carrier mobility to about 300 CM 2 /V-sec`as opposed to 1500 CM 2 /V-sec in bulk silicon. Despite this phenomenon, high speed is achieved due to the reduction in parasitic capacitance.

SOS has been limited thus far to -IOS 'circuit forms, with the highest emphasis on CMOS. The military is very interested in CMOS/SOS because of its inherent resistance to radiation.

A9

Appendix A Si Gate PMOS ♦ '_' Si Gate NMOS .-----.^ ° 25 U Z 20 ^ t NMOS- 1980 — — — i, SOS 15` ♦ CMOS `d 1 TTL 5400 ^^ Q 10 I 2 L` CMOS (3) SOS 5 ^ Schottky- TTL} ^_ _ -^. EFL CML LSI TTL CML MECL -^ DCT2L 0 10 3c, 40 50 60 70 80 90 100 V MOS JT L Isoplanar Gate Size in Square Nails ECL Figure A5. Gate Delay Versus Gate Size A10

i

l

APPENDIX B ARCHITECTURAL GUIDELINES FOR TIIE EFFECTIVE USE OF LARGE SCALE INTEGRATED CIRCUITS (LSIC) IN AVIONICS SYSTEM;S

i

Introduction The advent of LSI has provided system designers with a powerful new tool to meet the expanding requirements of new avionics systems, This tool requires new approaches to system architecture, Although some of the standard criteria for enhancingsystem performance minimize costs, they are now obsolete. Until recently, the only IC imple- mentation tools available were a number of small-scale integrated circuits, which realized an average of about four logic functions per package. This resulted in cost, size, weight, and power being almost a direct function of the number of gates in the sys- tern; thus, gate minimization was emphasized. Because complexity was minimal, the design of standard devices, which were used many times in a system, was relatively easy.

These devices, because of their high usage, soon become very inexpensive.

Semiconductor technology now permits putting thousands of logic gates on one mono- lithic chip. This capability has been hard to use as it is difficult to define commonly used arrays of such complexity, except in the area of memories. This capability has also greatly changed the system implementation considerations. Regular logic, such as memories and registers, can now be achieved with greatly reduced cost, size, and weight per bit. Random logic can be realized in high density custom arrays.

Pins and packages become more important than gates.

The spectrum of available logic families has also greatly expanded, covering a wide speed and power range. A number of Metal Oxide Semiconductor (MOS) families are now available, as well as new bipolar types.

Present-day system designers must know all semiconductor technologies available, and the advantages and limitations of each, He should also be cognizant of the relative tradeoffs of standard and LSI implementation on all system requirements. _A classic example is provided by the RCA efforts on LIMAC, which showed that computers designed r for SSI optimization could not be efficiently implemented in LSI. A new design approach was shown that would result in a 5-to-1 improvement in gate-to--pin ratios, one of the most important design parameters for an LSI system, A number of system concepts have become more economical due to the availability of -a LSI: i • Replacement of analog hardware by digital • Use of semiconductor memories • Increased use of parallelism • Increased use of modularity • Microprogramming • Replacement of software by hardware • Increased fault tolerance • Reduced system interconnections Each of these concepts is discussed below.

P B1 i

a Appendix B Replacement of Analog by Digital There is a marked trend towards replacing analog computations with digital because of some of the Shortcomings inherent in analog computation, and the arrival of high- density, low-cost digital circuitry. This concept includes replacement of electro- mechanical devices by digital electronics.

The emergence of LSI has accelerated the trend from analog to digital which began a number of years ago. This is due in part to the difficulty of integrating large analog computational blocks. As a rule, analog devices require large values of capacitance, inductors, and precision resistors. These components are much more difficult to achieve with monolithic circuitry than the transistors, diodes, and resistors that form the digital circuits.

{ Advantages of digital over analog computation include: 0 Adaptability to LSI • Compatibility of the output with digital equipment used in subsequent computations • Ability to process very low-frequency signals that would require analog devices prohibitively large in size • Relative insensitivity of digital equipment to environmental conditions -Increased stability of operation • Ease of changing performance characteristics • Ability to time share logic to serve a number of inputs e Advantages in size, weight, and cost s Simplified and standardized data bussing and addressing • Elimination of long settling_ times e Ability to hold data history for longer periods of time Examples of digitai computations replacing analog are discussed below to illustrate the above described benefits.

Applied Devices Corporation is developing a LORAN airborne navi ation system for the Army. While a conventional LORAN system requires from 0. 42 ft^to 0. 84 ft 3 , the digital version is expected to be less than 0, 1 ft3.

Honeywell has designed a digital signal processing module that can be realized on a single LSIC. This device can perform a second-order digital filter computation where the bandwidth and the Q of the filter is Oetermined'by values loaded into internal shift registers. Then, one LSIC can be programmed to perform as a number of unique filters.

Thus, the first step in defining an avionics system for LSI implementation should be ; to replace as much analog computation as possible. Input conversion from, analog to digital should take place as soon as possible, and output conversion from digital to analog should be at the last possible stage in most cases. The replacement should be accoin pushed by a thorough investigation of the function to be performed, rather than just attempting a 1-to-1 substitution of analog blocks by digital.

r

Appendix B Use of Semiconductor (LSI) Memories Until the advent of LSI, using small memories throughout -a system was very expen- sive on a per-bit basis. Magnetic memories, because of the high cost, size and power requirements of the associated electronics on a per-bit basis, were only efficient if the number of words was large in relation to the number of bits. In addition to this restraint, the speed of magnetic memories was not compatible with that of the IC logic.

Before LSI, when, at most, four flip-flops were contained on a chip (in a package), the use of small IC memories was also expensive in terms of size, power, and cost.

The increased pin interconnections also posed a reliability problem, thus severely limiting the use of registers.

Memory technology, gy, vvlth its high regularity, universs,l appeal and low pin-to-bit requirements, is ideally suited to implementation in (ref, B1). As a result, many LSI memory devices are available today as off-the-shelf items. These devices, with their j high gate density, high speed, low cost and low power consumption, ran provide new system design flexibility.

In addition to the conventional read/write Random Access Memories (RAM), a large number of Read Only Memories (ROM), Content Addressable Memories (CAM), and other structured memories are available to provide even more desigi.. flexibility. To da-a, the largest influence of LSI on avionics system architecture has been the increased use of shift registers, ROM's, _CAM's, and conventional RAM memories, This trend should be accelerated in the future. The main drawback to the use of LSI memories (other than ROM' s) is the inherent volatility ( lack of binary remnance upon interruption os power) of semiconductor devices,

.,i

;Distribution of small LSI memories throughout a system can be used to • Increase computational throughput • Increase system flexibility • Reduce system overhead • Reduce software costs • Reduce system internal data transfers Rand om access memories, - Low-cost RAW chips can be used to implement scratch- pad memories in place of e single accumulator architecture, typical of some small computers. The scratchpad`memory allows the storage of machine status, privileged data, base addresses, intermediate results, stack pointers, plus a general register store for use by the program. Previously, all of these software aids had to be stored in main memory. The programmer (or system executive) had to manipulate these aids through software, which resulted in high overhead because of many main memory accesses, With microceding and these scratchpads, this hardware can be made to sup- post many macro instructions, which simplifies the software task as well as minimizing main memory access, thus increasing system speed.

Use of small LSI cache memory can also increase system throughput. Buffering the -

t . main memory with a small, very high-speed memory allows repetitively accessed words

to be read and written very fast; while minimizing access conflicts to main memory, Thus, the CPU is not strapped to the relatively slow main memory cycle time and can - effectively execute near the high speed memory rate,

i

The availability of low - cost, high-density RAM's makes multicomputer systems, each with a relatively small main memory, a viable concept.

I

Read-Only Memories _, - Advances in Read-Only Memory (ROM) have already i^ad a profound effect on system architecture. The availability of high-speed, low-cost LSIC s B3

R Appendix I3 ROM's have enhanced such concepts as microprogramming, table look-up, hard-wired subroutines, and higher-order language interpreters. Microprogram memory using LSI ROM's can be used to realize multiple functions from the same computational unit, mak- ing it an efficient special-purpose device through programming. The low cost of LSI ROM's make table look-up of common functions a viable means of saving computational time, program memory and software overhead. Some special-purpose functions, such as coordinate conversion, code conversion, or sine/cosine calculations, can now be obtained in off-the-shelf ROM's, LSI ROM's have been shown to be a viable implementation of high-speed arithmetic.

For example, by using eight Texas Instrument bipolar 256 by 8 ROM chips and three 8-bit adders, a 16-bit product can be obtained in less than 100 nsec (ref. 132).

The same 8 bit-by-8 bit multiply can be achieved using MOS chips in 1, 0 μsec, while requiring only 8K bits of ROM.

ROM's have also been used to successfully replace random logic, thus decreasing system cost. Using RO.M to implement random logic has the following advantages: Y g p g g • Low development costs as compared to custom-designed random l logic LSI 0 Short development lead time • Regular high-density logic with high yields s Increased flexibility (Universal Logic Module) Reference • Fewer chip types or die required - z s Lower inventory required By far, the greatest architectural impact of LSI ROM I s has been their influence on microprogramming. Because of the inherent speed and the decreased cost of LSI ROA -11s, microprogramming has become a viable substitute for random logic controllers. (The architectural aspects of microprogramming will be developed in a later section.

Memory with imbedded logic. - With the reduced cost per gate of LSI, a new family of memory logic devices has been born. These structures are very regular and can be efficiently_ implemented in LSI while containing the control logic that tailors them to per- forming special and more complex functions than those available through simple memo- ries. Two good examples are the Content Addressable Memory (CAAM), which is presently used to support the cache memory in the IBiAI System 370, Model 165, and stack memo- ries, which have recently been made available as off-the-shelf items.

Content addressable memories (CADJ's): CAM's can increase computational speed by eliminating sequential file searches. Rather than accessing each item in a data set one at a time, as is done in a conventional memory, a CAI can search the entire data set or any designated portion of it simultaneously. It can be used to read, write, or perform equality searches over all words in parallel.. Additionally, with the aid of microprogramming, a CAM can perform addition, subtraction, logical operations, and maximum, minimum, or between-limits searches over all memory words in parallel.

This drastically reduces the overhead of system control and scheduling, and many other computations.

Stack and queue memories: Another new form of memory with internal logic is the They are sometimes also termed as first-in, hardware queue and the hardware stack.

first-out (FIFO) queues and last-in- first-out (LIFO) stacks, respectively,. For many years, programmers have imph-.nented these structures in software subroutines at a significant overhead cost. LSI offer.. hardware implementations that give a 4-to-1 Now, speed advantage for each access to the structure, A major use of FIFO queues is the buffering' of data transmission between two devices of different data rates. This allows Additionally, for an asynchronous operation of both devices at their maximum data rates.

ORIGINATE PAGE IS B4 QUALITY OF POOR

Appendix 13 { these stacks are well suited to reducing executive scheduling and interrupt processing overhead. Burroughs has used stacks and queues to reduce system overhead in many of i their machines.

Summary of memory applications. - LSI memory technology has had a great impact on system architecture. LSI has mac ace economical and feasible small distributed memo- ries, RAM, ROM, and memories with internal logic, CAM, queues, and stacks, These memory elements can be used by the system designer to alter machine organization and I j; increase system speed, flexibility, and throughput, while decreasing overhead and to data transfers. The new memory technology forms an integral part of the concepts to be discussed in the next 1.3w sections, i Thus, in defining any rivionics system, the system designer must be aware of the advantages that can be realized through LSI memories.

Basic guidelines for using LSI memories include: s Use small RAM's to memory (scratchpads, • reduce main requests caches, stacks and queues, and registers) a Use ROM's for microprogramming • • Use ROM's for table look-up • Use ROM's for hard-wired subroutines i • Use CAM's to eliminate file searches Use queues to buffer data transfers • Use queues and stacks to minimize executive overhead • Increased Use of Parallelism The attributes of LSI make it suitable for use in system:: with a high degree of parallelism. Because LSI can result in very high gate densities, the inclusion of addi- tional hardware to increase computational ability can still result in smaller systems' than those presently in use. Prior to LSI, parallelism was a costly concept, and was used only for physically large, high.-speed computers or to achieve high reliability.

The concept of parallelism in digital systems means concurrent operations on seg- or simultaneous execution of multiple processes.

ments of a single process To achieve concurrent operations on segments of a single process, one can operate on a wore- parallel basis rather than a bit-serial basis, or can include unique functional blocks to work on different aspects of a computation. As an example, two adder units in a com- puter can simultaneously allow an address calculation and an instruction execution. The classic example of parallel operation is the parallel processor, which is suited to prob- lems such as radar data processing, where a single computation is desired on many unique data sets. In this case, a number of identical hardware units, N (whex°e N is equalto the number of data sets), can be used to realize the results nearly N times faster than a sequential machine.

Simultaneous execution of multiple, processes is exemplified by the multiprocessor or multicomputer system, In such a system, the tasks to be computed are distributed to the various system esources, on,a priorit, T or time-based criterion, for computation, As with the parallel processor, the throughput of the system is the product of the number of processors and their effective computation rate, Prior to LSI, the use of parallelism was greatly limited, In today's technology, the highest levels of integration can be achieved with relatively slow MOS circuits, In marry cases, the speed of MOS is not sufficient to replace existing equipments unless archi- tectural changes are made. Parallelism, as discussed, provides a way to take advantage of MOS and to achieve high computational rates. With parallelism, one can consider B5

Appendix B developing hardware units of a very limited capability to achieve high system throughput by parallelism. The advantage is the ability to configure a system from existing modules to more exactly match system requirements. Increased requirements can be met by increased parallelism in small capability increments, A system designer, when considering parallelism in his system, must first define the optimum basic computational unit and then define how these units are to be configured into a system. The steps that are to be followed include: Unit • Consider computation on a word or byte basis rather_ than a bit basis.

• Determine if portions of basic computations (instructions) can be computed simultaneously and economically by including additional functional blocks, System • factor total task load into independent subtasks, • Determine if nonindependent subtasks can be made independent on a time basis (predecessor relationships).

• Consider replicating hardware to compute independent and time-wise independent tasks, Maximize use of identical hardware units.

•

• Determine the cost of controlling hardware and task scheduling.

The design of any avionics system using LSI'should be accomplished with the concept of parallelism in mind. Basic guidelines for the use of parallelism should 'include the following considerations:

• -Use additional functional blocks to processindependent portions of

a basic instruction simultaneously to increase unit speed,

• Use multiple copies of the basic unit to increase system speed and

to reduce response time.

• Use parallelism to provide incremented growth capability.

• Use parallelism to allow the use of low-speed MOS in high-speed systems.

• Use parallelism to allow fault tolerant operation and increase reliability.

• Use parallel units for problems where identical computations are required on many data sets, • Use parallel arrangements of low capability devices to increase, usage of custom LSI chips, ^ ; ; B6

Appendix B Increased Use of Modularity In the past, avionics systems have been characterized by custom designs and stan- dard black-box approaches. Each subsystem used a set of unique functional units and i each system application (airplane) used primarily different units, The custom develop- ment approach to system realization resulted in very high development costs and long development schedules, The standard black-box approach usually resulted in a capability overkill, which, with standard LSI implementations, entailed a high size, weight and power penalty. Neither of the two approaches provided any flexibility to meet increased capability requirements unless it was built in at the beginning of the program, Due to the diversity of avionics equipment, production and maintenance techniques were only partially learned for any one equipment.

I

Defining a set of modular building blocks that are expandable, general in purpose, and realized by LSI technology would greatly benefit avionics systems, Such approaches could significantly seduce the cost and response time of new avionics developments.

The int.-oduction of standard microprocessors on a chip such as the Intel 8080 has provided the system designer with a powerful new approach to modularity. Ruggedized versions of such processors could serve as controllers or dedicated preprocessors in

.l

avionics subsystems.

LSI favors the concept of modularity due to the ease of including added logic for multipurpose usage and the ability to tailor a general-purpose device through the use of a read-only memory (ROM). The high nonrecurring cost of custom chip developments, coupled with the very low per-gate recurring cost at high production volumes, shows that the more a custom chip is used, the lower the overall system cost will be. The con- cept of modularity at the micro level allows the designer to minimize the number of unique custom pasts, thus reducing the nonrecurring cost of LSI development, At the macro level, modularity can provide parallel computation and functional growth by adding identical hardware blocks to implement a subsystem. A truly general- purpose module can be used in a number of subsystems within the same avionics systems, as well as in a number of unique avionics systems.

Past attempts at modular approaches to avionics systems have been largely unsuc- cessful for the following reasons; a • The technology of conventional IC implementations had a large size-weight-power to computational capability ratio; thus, the designs had to be gate-minimized and highly optimized to achieve the speed requirement, while remaining within other physical constraints.

• There was excessive programming overhead of general-purpose (GP) a implementations of the special functions. Software overhead, program storage limitations, and program development time favored special- purpose hardware- design rather than a specially: programmed general= purpose unit, • Multipurpose modular equipment had low reliability, The added pack- ages and interconnections required to increase the usefulness of a module significantly reduced the overall systems reliability while ;a increasing size and weight, ' • Standardization of interfaces was difficult with analog devices and was compounded by themany subsystem black-box contractors, _.

In the past these problems tended to limit the use of the modularity concept in the design of avionics systems, i

r Appendix B With LSI, there is an increased need for modular multi-usage equipments to meet the ever-changing avionics requirements. LSIC technology has provided the following advantages for system modularity: • A drastic reduction in the size, weight, and power consumption for a given capability; thus, the designer is not gate-limited in developing multipurpose modules.

• Combining cheap ROM and microprogramming efficiently tailors general-purpose devices to special-purpose jobs.

• With LSI, the additional logic required to make a module multipurpose has little impact on system reliability Use of common modules could be greatly expanded by increasing the commonality of performance and interface specifications between avionics systems. The avionics designer should consider the following guidelines concerning modularity: • Use existing LSI equipment wherever possible.

• Use more powerful standard equipment than required, if cheaper than custom development.

• Convert general-purpose equipment to special purpose through micro- programming.

•_ Design custom equipment to be modular.

• Design custom equipment to be applicable to other systems or subsystems.

Microprogramming Introduction. - From an implementation point of view, microprogramming is a way of removing ran.dom control logic and of replacing it with memory-oriented units. This results in a loosely bound grouping of functional units such as registers, ALU's, memories, shifters, and other special logic units. The microprogram or firmware is a then used to define the structure of the system and the data paths through these functional units. Thus, the general-purpose architecture can be optimized for special-purpose problems: This technique has made a significant impact on computer architecture in the past several years due to the availability of LSI ROM's, From a systems architect point of view, there are several reasons to use microprogramming: t • Reduced random logic, resulting in a more structured organization • Efficient emulation of man;- special-purpose devices by one general- purpose LSI module • Simplified software programming through macro instructions • Simplified diagnostics and maintenance aids The cost, flexibility, and speed advantages of firmware make it an excellent com- promise between software and hardware implementations. The following subsections will discuss firmware in light of these advantages.

u i B8

i t r l f Appendix B

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Microprogram flexibility. - Flexibility is probably the most important advantage of microprogramming over ha - The ar implementations. design is not frozen by the existence of hard-wired connections; thus, it is possible to reronfigure by simply over- writing the control memory. Specific advantages of microprogrt mming include;

t

• Provides adaptation to new applications--without redesign of hardware • Provides for an increased hardware capability without costly redesigning • Provides dynamic reconfigurability for increased reliability Microprogram cost advantage. LSI has increased the feasibility of microcode implementations by reducing the cost-per-bit of ROM; thus, replacing random control gates and their associated interconnects reduces design and production costs.. Because

ROM's are approximately six times more efficient in using chip space than are random

logic controllers, significant production costs savings can be achieved using micro

a

programming techniques (ref.B3),. Table 131 shows the power and space savings of ROM implementation (ref. 134).

TABLE B1. ROM SAVINGS IN MICROPROGRAMMBD CONTROL BITS PER GATE FUNCTION Optimistic Realistic Pessimistic Number of Dips 114 85 Saved PC Cards Saved 2 1.5 60 DIPS /Board Power Saved 12, 8W 8.5W 6. 4W Volume Saved 150 in 3 100 in3 75 in3

Through the use of microprogramming, one hardware device can be used for a

number of different applications, which boosts production runs and lowers system costs.

This advantage has been discussed in the modularity section and is especially true of the new generation of microprocessors.

Another cost advantage of microprogramming is the reduced cost of producing soft-

ware. Microcode allows software to be written in a more macrolanguage and allows

direct implementation of special functions. Alternately, microcode can provide an emulation capability to allow "old" machine software to execute on "new" machine archi- tectures without revision.

Microprogramming for avionics systems. Cost, flexibilit y, and speed make firm-

ware an excellent compromise between a software and hardware implementation for

avionics systems. Placing such things as monitoring functions and debugging aids in

the microcode significantly reduces operational software costs. Firmware, because it controls the data paths and functional blocks, can be used to implement the housekeeping functions required to support complex operating systems and executives, BQ

Appendix B Microcode has the advantage of being separated from main memory and protected from unauthorized change. This means that there is no physical way a user can destroy vita'. algorithms and status, as in the case of software implementations. Thus, it is well suited for implementing system level functions.

N Deduce random logic and expensive custom chip design by using standard LSI ROM's Q Increase flexibility of functional modules ^u Define macros that simplify software development tasks Use of Hardware to Perform Traditional Software Functions Introduction. - Avionics computing systems are continually being relied upon to per- form increasingly complex system functions, This increased complexity has drastically increased the cost of applications softwar e.

Estimates of the software-to-hardware cost of a total system range from 4 to 1 through 1 to 1, depending on system complexity.

This ratio is constantly widening as LSI technology reduces the cost of hardware (5 to 25 percent per year) while software development costs continue to rise, These considera- tions, coupled with the increased capability, complexity, and speed requirements of avionic computing systems, have hastened the repla cement of traditional software func- tions by hardware. The new technological developments described now make this transi- tion feasible and economical.

During this transition, a gray area has developed between the gate hardware imple- mentation and the instruction word software, This gray area, which has been termed firmware, has recently her>n emphasized to enable equipments to operate at the macro instruction le-el. Thus, hardware and firmware have been used both to replace` and to enhance some c^f the traditional software functions.

This transition of software to hardware is especially significant for avionics systems when volume is a consideration. Software represents a nonrecurring cost that can be made less significant by spreading it over large production runs, In avionics systems, production potential is tow, although complex software costs remain high., however, the Additionally, the application software is growing in complexity, which increases the de.

bug g ing gg' g problem and cost exponentially. For example, an avionics guidance and control system with a software package of 12K words complexity has 50 percent of the total sys- i tem' s cost in software, The Space Shuttle guidance and control software package of 64K words i°epresents 80 percent of the per s ystem cost. Thus, the implementation of soft- ware in hardware represents a great potential benefit to avionics systems.

There are basically four ways to implement software functions in hardware: j • Random logic • Table look-up • Microprogramming • Dedicated microprocessors I Random logic. - This method of implementation is a true hardware approach as contrasted to the firmware approaches that will be discussed, It is the least adaptable and also the least amenable to LSI,' but generally is considered the fastest of the approaches, Except for universal logic modules or programmable logic ;arrays, this is a custom -x B10

S yj Appendix B approach that requires some volume production to be cost effective if implemented in LSI. Functions that are often implemented, in gates are • Floating point arithmetic • Multiply and divide • Square root • Fast Fourier transform ,, I • Priority decoding-encoding • Coordinate transformations Hard-wired implementations are most economical when the function is used frequent- ly and speed is a critical requirement. For example, a Honeywell computer could execute a square root instruction in 25 to 30 μsec with a software routine; the inclusion of 64 gates of special hardware allowed this computation in 10 p.sec.

Tab look-up. - A table look-up implementation is the next closest thing to the le hardwired approach.

It has become increasingly attractive to the designer due to the availability of low-cost ROM and electrically alterable ROM. It is economical and , a amenable to LSI, while providing speeds almost equal to that of hard-wired gate imple- mentations. The use of table look-up has been used for some of the following functions: • Multiply-.divide s Code conversion r BCD arithmetic a • Character generation for displays • Trig functions • Transducer calibration At present, a number of these functions are available off the' shelf. This is a clear advantage for low production systems as no LSI chip design is required, ..

A, good example of the feasibility of the table look-up implementation is described by Texas Instruments (ref,Bl)ia their implementation of an 8-x-8-bit multiply.` Using a novel hybrid hardware and ROM approach, the multiply can be accomplished in 76 nsec, using only 8K bits of ROM. It is implemented with all standard off-the-shelf MSI and LSI parts, and could be expanded to do 16-x-16-bit multiply using 33K bits of Q s ROM in 150 nsec.

- Microproc essors. Due to LSI technology, anew type of building block has been introduced. Microprocessors are the: high-level asynchronous functional boxes, like the Intel 8080 which was discussed in the processor section. They can be considered as modularly parallel functional units that efficiently execute high complexity functions in hardware while not requiring a custom chip. They are now available as off-the-shelf - parts, thus providing a library of hardware subroutines to be used by the ;system designer.

Some functions which could be implemented using microprocessors are: _ • Memory pagers • Vector multiply B11

Appendix B IViatrix multiply • • Fast Fourier preprocessing • Digital filtering • Output formatting This implementation can be cost-effective for small production runs or developmental programs of avionics systems. It also has the advantage of being modular, and thus applicable to many avionics systems without having to redesign either the hardware or software.

An application example in ^ommunication error processors. This microprocessor would asynchronously monitor and fore at the error coding of incoming and outgoing block transfers. If an error occurred, it could initiate a retry. If continuous errors oc- curred, it could then interrupt the CPU.

Guidelines for the use of hardware to replace s oftware. - For each application, con- sideration must be given as to which functions to implement and which implementation is best, Basic considerations are: • Use hard-wired gates where high speed and/or function complexity is required.

r Use table look-up techniques for less complex functions, • Use microprogramming where recursive or repetitive steps of an algorithm can be identified.

• Use microprogramming where speed is not critical."

s Use microprogramming where compatibility across a family of devices is required, • Use microprocessors to perform dedicated parallel functions.

Increased Fault Tolerance Avionics systems have reasonably stringent fault tolerance /reliability Introduction. - requirements. LSI provides many cost-effective-means of increasing systems' reliability within size, weight, and power constraints.

While systems grow linearly in complexity, the testing and, maintenance problems grow exponentially. Even for ultrareliable systems, there exists a need for hardware aids for testing and fault diagnosis. The reduced cost per gate of LSI can provide, on many levels, aids that simplify these tasks, Two characteristics of LSI improve fault tolerant systems. The first is the de- creased cost per gate of logic. For a given pin-limited partition, there is often a signifi- cant amount of silicon area available which effectively gives "gates for free. " The second characteristic is the reduced number of pin-outs or physical connections. The predominant mode of failures for electronic devices is contact or connector failures.

Using LSI and thereby reducing the number of pins in the total system, increases reliability.

" i B12 Y

Appendix B Circuit consideration. - Due to the reduced cost and reduced physical connections, it is now feasible to use added logic to increase the reliability of a logic function. Dual gate redundancy techniques can be efficiently used for fault detection, Triple gate redundancy can be used for fault masking. These techniques, which were previously very costly in. terms of size, weight, power, reliability, and dollars, are amenable to LSI due to their regularity, A separate fault detection circuit can often be included in the chip without any penalty.

These circuits (see Figure B1) can continuously monitor f4? circuit malfunctions and can inhibit faulty outputs. Alternately, it could be used in a testing mode where it would help diagnose a complex LSI circuit during system tests.

Another technique enhanced by LSI is the replacement of random gates by microcoded ROM. This implementation of control logic increases reliability because ROM is more s„ reliable than random gates, Furthermore, the more orderly microprogrammed imple- mentation generally requires fewer interconnects, which also increases reliability of the overall control circuits.

LSI ROM's make error-correcting codes a more feasible fault tolerant technique.

Small encoders and decoders for code conversion can be included on the chip at little cost in silicon area or execution speed. These codes can be used internally (i. e. , residue code for arithmetic operations) or externally (i, e. , hamming code for data transmission), i ^i ^2 14

Appendix B Microcode considerations. - Microdiagnostics provide a real aid to built-in test and

system production testing. By dynamically performing error checks, fail - safe opera-

tions can be achieved by dynamically changing algorithms to bypass hardware components that have failed. Furthermore, microdiagnostics depend on fewer operational hardware circuits and, therefore, can be exocuted on a smaller, error--free hard core. It has been estimated that the IBM 360/30 reduced its hard core from 50 percent to around 10 percent. This means that more failures can be detected and, more importantly, can be overcome. Because the microcode is directly in control of all the system hardware, microdiagnostics can isolate failures with higher assurance to a smaller unit.

Once diagnosed, microcoding can often provide an alternate execution using sldwer, but operational hardware. For example, in the IBM 360'85 there is a low-speed multiply algorithm in the microcode that can be used when a failure is detected in the high-speed multiply hardware ( ref. B 5), S s Y tem ! s considerations. - On a higher level, LSI savings of size, weight and power, as well as cost, enhance the use of functional redundancy. Where functions can be incor- porated on a single chip, dual and triple modular redundancy can be implemented cheaply and easily, By combining stand-by redundancy with microprogrammed fault detection and re configuration, an effective fail-safe / fail - soft system can be designed.

Microprocessors provide a new tool that can econvn`ioally be used to inc r ease system

reliability, System configurations with multiple paralleled mic •roarocessors provide a

high availability, as well as a graceful degradation. As described before, mic r oproces-

sors can be dedi. - atee l to monitoring for system errors to provide a performance evalua- tion in real time.

Many subsystem functions that have previously been implemented using analog and

electromechanical devices can now be implemented i n digital ( ref, B6), Replacing

these older implementations with LSI has vastly increased the subsy,"'tern ' s reliability.

Strapdown or lase r gyros are a good example of the increased reliability of electronic

implementations over conventional implementations.

Summary. LSI provides new methods of increasing a system's reliability. LSI's enhancement of modularity and reduced interconnections have also had a significant in- direct effect on the system architecture, while increasing its overall reliability, Some general considerations to improve system reliability would include i • Use ROM's for code conversion on the chip.

• Use microprogramming to organize control and to reduce 'random gates.

x • Use microprocessors to monitor critical functions.

• Use extra silicon area for fault-detection circuits.

a Use modular redundancy within systems to provide fail-safe operation, • Use functional redundancy (i. e. , TMR, and voting) to provide reliable modules,

• Use dual redundant gates for fault detection in critical circuits, a

a • Use triple redundant gates with voting to mask failures, B14

t Appendix B Reduced System Interconnections Introduction. - Avionics systems are becoming increasingly complex interactive systems. With the increase of functional block interdependency comes a corresponding increase in communication. The traditional after-the-fact, ad-hoc method of connecting units together is not a satisfactory solution. Considering reliability and packaging, I point-to-point wiring in such complex systems cannot be permitted. Thus, for complex system architectures, a new method of bussing is required to reduce the number of connections and the volume of data transfers.

LSI systems provide several new possibilities in system interconnect architectures.

While LSI suffers from pin-out limitations, it provides solutions to better minimize and some addi- system interconnections. Many of these concepts are discussed below, tional ideas are presented in the partitioning section.

Chip considerations. LSI has increased the amount of logic on a chip to a mint where whole functions with their supporting control and buffers can be contained on one chip. This reduces the number of package-to-package interconnects to a minimum.

Additional gates can be included to form data buffers, which allow communication on a nondedicated (time division multiplexed) system bus.

Multiplexers can be included on the chip to allow the same nondedicated bus to prr - vide data, control si.gnals, or even diagnostic information through the same set of pins.

Control signaas can be encoded and decoded on the chip to further reduce the required.

transmisuions, The complexity available on a LSI chip can make serial transmission of data an effi- cient alternative. For example, consider a LSI chip that requires 350 nsec to operate on 8 bits of data. Parallel data transmission would require 8 input lines on the chip.

Serial transmission at a rate of 40 nsec/bit would allow a savings of 7 I/O ports. The chip would require an eight-bit serial in parallel out shift 'register to feed the holding register. Next, instruction data would be input during the current instruction execution.

Thus, an 8-bit shift register could be traded for 7 pins, with a resulting reliability and overall chip partioning advantage.

Using microprogramming reduces the number of main memory instruction transfers.

This reduces the contention for main memory bus access, which is often a bottleneck in systems' throughput. In view of the hierarchical instruction executionfor parallel pro- cessors previously described, this can significantly reduce bus transfers.

LSI, through the enhancement of distributed cache memories„ has also reduced the contention for the main memory data access. The localization of data path loops to a single chip has allowed for the concurrent parallel operation of several units without interference, This not only increases the overall system thoughput but also enables the use of nondedicated busses, The latter enhances the system modularity and its attendant advantage - expandability.

Avionics system considerations LSI microprocessors, working as asynchronous functional units, efficiently reduce communication between avionics subsystems, By preprocessing sensor data, a minimum amount of critical data must be transmitted to the necessary subsystems. This results in two advantages: 1) an .increase in number of sensor devi^esshat can be served by that bus, and 2) a`reduction in the computational capability and complexity in the subsystem requiring data from that sensor, A simplified centralized computer can, therefore, service many subsystems without :caving to inter- face with each sensor output. Its software complexity is reduced and modularity is enhanced due to the all -digital interfaces and the reduced amount of data flow, # l B15 i

Appendix B LSI has made feasible a modular interface unit (IU), which can reduce the overall system overhead involved in communicating on a nondedicated bus. These IU's are standard modules that can distribute the control throughout the system, thus increasing the reliability of the overall system. Furthermore, these standard IU's are a hicrh-usage module that can automatically buffer devices of vastly differing characteristics onto one common bus.

In future avionics systems, the number and width of data busses as well as the amount of data transfers must be minimized. Some LSI considerations which could be used by the designer are: • Use microprocessors at the data entry point, allowing only important nonredundant data to be transmitted.

• Use added logic to encode and decode control-command transmissions.

• Use serial transmission to minimize pins where execution time permits.

s Use nondedicated busses to increase system modularity.

• Use distributed control in bus interface to minimize overhead while increasing reliability.

• Use the multiplexing of pins for input, output, control, and testing.

Summary of Architectural Guidelines The preceding discussion has shown that many new approaches to defining system architecture are possible when LSI is to be considered in system implementation. It has also been stated that some combination of these approaches is usually necessary to opti- mize the suitability of a system to LSL Because many guidelines are presented, the designer must make a judicious selection of those applicable to a given system.

A summary of the architectural guidelines for the efficient use of LSI in avionics systems is presented below (each should be considered in terms of system requirements).

Replace Analog H a rdware by Digital i • Convert inputs from analog to digital as early as possible.

• Convert outputs from digital to analog as late as possible.

• Consider new algorithm developments to optimize digital implementation.

Us e of Semiconductor (LST) Memories • Use small RAM's to reduce main menory requests (scratchpads, cashes, stacks,; ,queues, and registers).

• Use ROM's for microprogramming.

• Use ROM's for table look-up.

,j • Use ROM's for hard-wired subroutines: •' Use CAM's to eliminate file searches.

B16

l I i t Appendix B • Use queues to buffer data transfers, • Use queues and stacks to minimize ex-cutive overhead.

Use of Parallelism • Use additional functional blocks to simultaneously process independent portions of a basic computation.

• Use multiple copies of basic hardware units to increase system speed and to reduce response time, • Use parallelism to provide incremental growth capability, • Use parallelism to allow the use of low-speed MOS in high-speed applications.

Use parallelism to allow fault tolerant Operations and to increase reliability.

• Use parallelism where identical computations are required on multiple data sets, • Use parallel arrangements of low-capability devices to increase use of custom LSI chips.

Use of 1Vlodularity • Use existing LSI equipment where possible.

with • Use standard LSI equipment excess capability to avoid custom development.

o Convert general-purpose equipment to special-purpose equipment through microprogramming, • Design each new equipment to exhibit modularity and commonality wherever possible.

r Use Microprogramming • To reduce random logic and custom chip design using standard LSI ROM's.

• To increase flexibility of functional modules.

,a j • To define macros to simplify software development, Use of Hardware to Perform Functions Traditionally Done in Software 7 a • Use hardware gates- to perform special arithmetic functions.

a Use table look-up.

i 0 microprogramming for recursive steps of an algorithm.

Use • Use microprocessors to perform traditional software functions, j i B17

Appendix B Increase Fault Tolerance and Reliability • Use ROM for code conversion on the chip.

• Use microprogramming to organize control.

• Use microprocessors to monitor critical functions, • Use extra silicon area on a chip for fault detection circuitry.

• Provide .redundant gates on a chip to increase reliability, • Use functional redundancy to provide reliable modules.

• Use modular redundancy to provide fail-safe operation.

Reduce System Bussing ♦ Use processors at data entry point; transmit only nonr. edundant data.

e p.

• Transmit data serially where speed permits.

• Use nondedicated busses (time division multiplexing).

• Distribute bus interface control.

• Use same busses for input/output and control.

Following these guidelines will not only allow a more cost-effective implementation using LSI,- but also will improve other important system parameters, I a I i i B18 REFERENCES The Semiconductor Memories Course Workbook, William Carr, Texas Instruments, B1, 1972.

K. J. Thurber, R. O. Berg, "Universal Logic Modules Implemented Using LSI B2, Memory Techniques, " Proceedings, AFIPS 1971, Fall Joint Computer Conf, , Las Vegas, Nevada, November 1971, pp, 177-194, B3. G. W. Schultz, "MOS LSI Minicomputer Comes of Age, " Proceedings, FJCC 1972, pp. 1069-1080.

B4. W, H. Davidow, "General_ Purpose Microcontrollers, Part I: Bconomic Considera- tions, '' Computer Design, July 1972.

System/360 Model 85 Microdiagnostics, N. Barton, R. McGuire, AFIPS SJCC, 36, B5.

1970.

Roger A. Urban, "An Airborne Associative Array Processor, " Proceedings NEC., B6.

Volume XXVII, October 9-11, 1972 pp. 318-321.

u I .. 3 i a' • x

j i

i

APPENDIX C i ?

a RELIABILITY OF LARGE SCALE INTEGRATED CIRCTUITS(LSIC) Introduction , One of the most widely promised attributes of LSI is that of increased reliability.

Industry has moved from the vacuum tube to the transistor to the integrated circuit to increase reliability. There are many reasons to believe that the move to LSI should also be accompanied by increased reliability: systems using LSI will consist of fewer compo- nents and will require fewer system interconnections. Thus, unless the chips them- selves are more unreliable than the chip reduction factor plus the system wiring improve - ment, LSI should result in a more reliable system.

Determining the reliability of LSI devices is very difficult, and sufficient field data is not available. The problem is complicated by the number of available technologie s and approaches to LSI, and by the different chip sizes, device count, and pin-outs used by each unique chip. Data that is available on LSI devices are taken at different temper- atures and employ different L.etest screens, further complicating evaluation of reliability.

Determination of failure rates of LSI chips is very costly and time consuming. For example ('ref. Cl), to ensure a 0. 1% 1000 hr failure rate with 90% confidence, 2303 devices would have to operate for 1000 hours (42 days) without a single failure. If one failure was allowed, 3891 devices must be tested. To ensure a failure rate of 0. 01°0]1000 hr, the number of devices would be 23, 000 and 39, 000, respectively. The number of devices can be reduced by lowering confidence levels, increasing operating stress, and increasing the time involved; however the problem is formidable for custom LSI chips.

Thus, using custom LSI on low-volume avionics systems is not compatible with standard life tests to determine reliability. The number of devices and the time required to establish the reliability of a device would extend the development cycle and perhaps exceed the total volume of chips required to implement the systems: Attempts to determine the reliability of a process or a technology would be of more value, yet they are changing at such a rapid rate that by the time reliability assurance is obtained, the processes would have been changed, and hopefully improved, For example, the standard metal gate approach to MOS LSI has been expanded to include silicon gate and ion implantation in a very short period of time.

r` The importance of technology maturity its illustrated in Figure Cl, which shows that the normalized failure rate of a technology decreases by a factor of two after one year in production. After two years, the failure rate has decreased by a factor of nearly 10.

This figure was supplied by Hughes Aircraft: Measured ana Estimated Reliability I^ Table Cl lists reliability data, measured and estimated, for IC's of various tech- nologies and complexities. The first two entries show marked improvement in Motorola MOS over a one-year period. Collins radio estimates a reliability improvement of 2. 5 after 1000 hours of operation. Motorola shows a 20 -to-1 reliability improvement with device screening, and a 50-fo-1 reliability increase of beam leads over conventional p7Lckaging for bipolar SSI parts. , For a bipolar 150 - gate array, ` they predict a 10-to-1 improvement with 168-hour burn-in. The same improvement is expected for MOS LSIC's.

Ci

i

Appendix C

Reliability Characterization of Device Alternatives

The device technologies from which the designers hav- to choose are numerous,

From the major divisions of bipolar and MOS, subdivisions such as transistor-transistor

logic (TTL), current mode logic (CML) and diode-transistor logic (DTL) can be made for

bipolar and P-channel, complementary or N-channel subdivisions can be made for MOS,

among others. The latter may be further divided into high voltage, low voltage, thin

oxide, ion implanted, silicon gate, etc.

From a reliability standpoint, some failure modes and causes are common to all

types, while others are peculiar to a particular family, Overall failure rates reflect this

mixing and other influences such that failure modes overlap from type to type and the

types are not uniquely separable on the basis of failure rate, Moreover, our interest

here is not in any one particular type of failure, but rather in the level of its complexity

and reliability as designated by small-scale integration (SSI) or large-scale integration

(LSI). Thus, rather than extremely precise estimates, we will need representative fail-

ure rates for these general categories to determine reliability of those systems using

them.

For purposes of discussion, an SSI will be defined as containing from one to 12 gates

on a chip (typically five), 14 leads, approximately 40 mils square and using single-layer

metalization, A bipolar LSI device will be Defined as containing up to 150 gates, up to

60 pins, approximately 150 mils square, and requiring multilayer metalization. A

MOS LSI device will be defined as containing 500 gates, 40 pins, and single-layer metali -

zation. The pin reduction reflects partitioning advantages of the added complexity. The

chip size will be approximately 150 mils square, A hybrid device shall be defined as

containing typically 49 SSI beam lead chips and 60 pin-outs from a 2 by 2 inch ceramic

multilayer substrate. The functional nature of the relationship between these character.-

istics and reliability is typified by the Equation given in the proposed MIL-HDBK-217B or

the RADC Reliability Handbook: i

o i

Wo 5 WW 4 ^ wz NO WN.'

za W n v LL 2 3 y 0 1 LENGTH Of TIME IN PRODUCTION, YEARS

Figure Cl, Change for Normalized Failure' Rate for a Semi-

conductor Technology versus Length of Time in

Production

C2 i _TABLE C1, RELIABILITY DATA Device %11u Hours Company Technology Temp. Complexity Data Source Failure Rate Hours

T

Motorola Aay 71 Rel. Report. SPD 9928.

PMOS/LSI 85°C 33 B. 7K Dual 100-bit 0,8.1 shift. register LSI 125C 1.5M LSI memories 0.54 Aug 72 Rel. Report 7235-2.

Motorola P 4C NS-N MOS 0. 22* Aug 72 Rel Report 7235-2.

Motorola LSI 75°C Shift registers and logic arrays PMOS-NMOS Honeywell PMOS LSI 95°C(A) 64x4 RAMI 0.68* Honeywell 0972-11188 ('9172).

256x12 ROM 600 Transistors 0. 1-1 0 1u G. L. Schnable, "MOS IC PMOS LSI 12590 600 Transistors 0.02-0.2 % Reliability, " IEEE Trans on 50 90 Rel., Vol. R-21, No. 1 Feb.

72. 12-19.

pp.

300 Gates M 0.01 R. B. Conn. "Design. of Fault- MOS Tolerant, Modular Computer with Dynamic Redundancy, " Proc. FJCC 1972, pp. 1057- 2a Z3 1067.

(new Sys) 0. 18 Working paper 2399, July 1972.

Collins MOS 106 (after 0.072* r^C 1000 hrs) LSI 40 pin 0.022* Honeywell Aero part failure Honeywell Bipolar MOS SSI 0.01 rated.

Bipolar MOS 0.001 Questionnaire data.

National moo 451C 0.35 Rel. Report 7220-1B 125"C 1.2,M Motorola CMOS (after 0.10* ,Personal communication.

Bipolar LSI 1251C(A) 150 Gates burn-in) 616 Gates 0.292 Questionnaire enclosure data.

Bipolar whole Hughes wafer 0.05 Beam lead fact book.

SSI Motorola Bipolar SSI 0.001 Beam lead fact book.

Beam lead SSI Bipolar SSI 0.001 Beam lead fact book.

SSI with screen 0.00005 Beam lead fact book.

Beam lead SSI with screen 0.105 May 71 Rel. Report SPD 9928.

75C 1.89M 2 SSI 2 MSI PMOS MSI- -Motorola 125'C SSI 0.12 Aug 72 Rel. Report 7235-2.

3. 5 A SSI PMOS -NMOS 125°C Motorola -2.

0.04* Aug 72 Rel. Report 7235 75°C SSI PMOS-NM.OS

Appendix C Failure Rate = X(rrC TrQ) for monolithics (Cl) TrP'TE where A = a base failure rate = a complexity adjustment factor Tr C = adjustment for package type Tr P = an environment adjustment Tr E = adjustment for quality grade or, for hybrids, T + P Failure Rate = ( A D + AS a- )77E (C2) where EX = the TT C for discretes using the total active area of all chips X = substrate failure rate failure rate for thick or thin-film network or substrate XT X P package failure rate 17 = environmental service factor When comparing monolithics, rrE and TrQ along with X, essentially divide out, leaving complexity and package as the main differences.

Package adjustments in both RADC and 217B seem to be influenced by package material and type of die attach rather than number of pins or wire bonds or circumferen_.

tial length of seal. Both documents consider complexity in terms of gates, but not for very large number of gates or more than one layer of metal.

Various refinements have been made in the models to 'remedy these shortcomings.

There is a circuit size and complexity factor, ac,_ given by Tr C 0. 5 + 0. 5 (A/5000)0 (C3) t where A is the active area of the chip in square mils. Assuming that the outer 10 'mils of a chip contain bonding pads, the preceding definitions give the following factors: SSI 17 = 0. 57 _ , 2 , 17 LSI Try Hybrid tr c _ 3. 59 a The package factor, Trp, is given by Tp = 1 + 0.05L for chip and wire packaging. (C4) x C4 i

i Appendix C Assuming beam leads are better by a factor of 4, it yields = 1, 0 + 0. 0125 (L) for beam lead chips (C5) Tr p i Trp where L is the number of leads in excess of ten, Adding 1 to in the case of hybrids for the ceramic substrate and interconnections, Trp becomes SSI Tr p = 1. 2 LSI TT p 3. 5 bipolar = 2. 5 MOS Flybrid Trp = 2. 62 Taking the product Trp Trc for each type, and then taking the ratio of the result with respect to SSI, shows that (according to our characterization of SSI, LSI and hybrid) bipolar LSI has a failure rate approximately 11 times SSI, MOS LSI has a failure rate 8 times that of SSI, and hybrids have a failure rate 14 times that of SSI. Therefore, on a per-gate basis, the relative reliability of the various implementation levels becomes: a Complexity Implementation Rel, Rel, /Gate SSI 5 gates , 1 Bipolar LSI 150 gates 2.72 MOS LSI 500 gates 12.50 Hybrid SSI 245 gates 3. 5 Systems that are highly digital should exhibit the reliability improvements shown for LSI, provided that the complexity used matches the assumptions and that no attempts i have been made to increase reliability through redundancy for the monolithic LSI approaches, System Production/ Deployment Reliability Side benefits from progressively seducing part count and complexity are decreased weight and increased freedom for the mechanical designer to improve structural strength and thermal design, which further improves reliability. On one I3oneywell SSI design, _ the desired thermal conditions were not achieved due to weight and volume restrictions.

- Had LSI been used such that the needed weight and space were available for cooling pur- poses, reliability could have been increased by approximately 10 percent due solely to the temperature decrease.

The multilayer boards are decreased not only in quantity but also in the number of layers and the number of plated through .-holes, The latter produces higher per-board reliability: The reduction in system complexity achieved when using LSI benefits the production line also, as handling damage is proportional to the number of modules built (given constant fragility).

The testing/ logistics questions associated with LSI systems are interesting, As far factory test of the LSI system is concerned, the same sophistication is needed as for as SSI; yet fault isolation to a board in the LSI system should be much easier than in the SSI system. Extensions of this idea might be that boards become line replaceable units ' { T C5

Appendix C (LRU I s) rather than black boxes, and more elementary depots could be established nearer the front fines to improve availability. Cost of ownership for the armed services could be significantly affected, Basic to all reliability programs is the requirement for a capability in failure analy- sis. Where possible, it is desirable to have the basic capability at the system house for quick concerted action, A semiconductor vendor is much more receptive to taking cor- rective action when proof of failure mode and mechanism is presented to him. Unfor- tunately, LSI failure analysis often requires a sophistication that strains the capability at the systems' house, particularly, for degradation-type failures. Dine to the lack of standardization of LSI, failure analysis results at one company are often not applicable tb the problems of another company.

Standard part approval, although an expensive and time consuming procedure, is an indication of reliability. While the mere listing itself does not guarantee high reliability, the procedure through which the part goes to become standard forces some degree of production maturity. The operating life and environmental testing done during qualifica- tion usually uncovers the initial part design/production incipient failure mechanisms.

If a problem occurs, the program will not only suffer a costly correction of deficiences in equipment already produced, but will also be faced with a schedule slip to keep from fielding more problem devices. The slip continues until failure analysis/ redesign can determine corrective action.

Another advantage of standardization is that the larger the quantity of orders the vendor receives, the more likely that his production lines will continue working without interruption. The number of disruptions is directly proportional to the number of pro- duction errors and inversely proportional to reliability.

The observations described are not new they were basic considerations during the initial organization of the standardization program, The important point is that they are recognized by systems designers today and that LSI is presently operating without their benefit, Maintenance Cost Analysis For most avionics systems, maintenance costs over the lifetime of the system can be many tames the initial acquisition costs involved, Results of previous studies have in Fact indicated that costratios can run as high as 10 to 1. For this reason, it becomes increasingly apparent that system implementation decisions should be made in light of their impact upon total life-cycle costs, including both acquisition and maintenance costs.` A maintenance cost analysis will now be performed for several implementation %.

approaches, assuming a simplified but representative maintenance procedure for avionics systems. Three maintenance procedures will be considered, in this analysis-, i i Discard-Upon-Failure at the System Level 1) 2) Discard-Upon-Failure at the PC Board Level 3) Repair-Upon-Failure at the PC Board Level by Replacing Subpackages A i In the first approach, maintenance is achieved by replacing the total system/sub- system after each failure. This :approach is only realistic for less complex systems, In the second and third maintenance approaches the PC board is considered as the basic repair/ replace mc y-t element. This is a realistic maintenance procedure for avionic systems of general complexity, In each of these approaches, maintenance costs are predicted by using a simplified maintenance cost model, which is shown in Fig- ure C2, This model has been generalized from AFLC/AFSC Manual No. 800-4, C6 SYSTEM LIFETIME J NUMBER OF NUMBER OF FAILURE S SPARE S DEVICE MTBF BOARD/SYSTEM MTBF TYP BOARD COMPOSITION SPARES f ACQUISITION f PER SPARE ACQUISITION f d PER SUB-PACK/AGE INVENTORY AND LOGISTICS COST 'q RATES 'ty INVENTORY AND MAINTENANCE_ S (D LOGISTICS f INVENTORY AND :3 LOGISTIC Li SPARE iC DEVICE SIZE n AND WEIGHTS LABOR f AVERAGE HOURS PER REPAIR/ REPLACE LABOR f PER REPAIR/REPLACE: j LACOSTS PER HOUR i TEST EQUIPMENT TEST EQUIPMENT f COSTS OST COMPUTATIONS INPUT DATA Figure C2, — Simplified Avionics Maintenance Model ^ '

a T Appendix C Optimum Repair Level Analysis." In the first of these approaches, maintenance entitled " board level when failure occurs. Elements of is performed by replacement at the PC - cost using this approach include: rsition cost of spares • Acqu * • _ Diagnosis and replacement 1a1bor costs • Spares inventory and logistics costs • Test equipment for a single repair location With this simplified model for board-level _replacement, a number of redundancy cost elements are ignored, including maintenance publications, redundancy of test equipments for multiple repair sites, and the actual cost of acquiring and maintaining the repair facility itself. In so doing, it has been assumed that each of these cost elements are essentially constant for each electronic package implementation approach. Thus, the objective here is to establish the relative relationships of maintenance costs for the vari- ous implementation alternatives and not the absolute costs. The maintenance costs predicted in the fcllowing analysis will likely be considerably lower than the actual.

However, the relative maintenance cost relationships between the various implementation approaches should be accurate.

The final maintenance procedure analyzes cost impacts of repairing at the PC board level, In this case, repair is actually achieved by replacing subpackages on the board and, as such, might be considered as a discard approach at the subpackage level. Typi- cal subpackages might include DIPS, flat-packs,2-x - 2 inch substrates, packaged wafers, and others, depending upon function complexity. The cost elements of this simplified maintent-Mce model are similar to those described.

Thezmaintenance alternatives described are all field level replacement or repair approaches. More complex approaches incorporating repair within subpackages would be a factory-level repair and are not considered meaningful in terms of the average avionic system. Such an approach would )be viable only in hybrid implementations using beam-leaded chips.

:x i „a i REFERENCE C1. Anon: An Integrated Circuit Engineering Report, ICE Corporation, July 1968.

r C8

i APPENDIX D EDN's SECOND ANNUAL MICROPROCESSOR DIRECTORY Because a suitable reproducible was not available, this information was not included here, See Reference 8.

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APPENDIX E MEMORY TECHNOLOCTY The rapid growth of electronic data processing over the last 20 years has been char- acterized by an almost insatiabe appetite for larger and faster memories. Memory sys- tems are now and will continue 'to be the highest single cost item in the computer hard- ware structure. Because of these reasons, continued attempts have been made to improve the speed and cost of computer memories. Although these attempts have been fruitful, memory is still the limiting area in many advanced computer system developments. For many computer applications the cost and processing power is largely determined by the speed of the various memories in that system. Any advance in memory is, therefore, of great importance for advancing the performance capabilities of a computer.

Today's memory devices can be classified into two basic categories: fast and expen- sive electronically accessed main memory and very slow and inexpensive electromechan- ically accessed peripheral memory. Between these widely diverse technologies is a large memory access gap which has persisted for a long time, even though the boundaries on either side of the gap have moved towaids faster access by about an order of magnitude (ref. E1).

The absence of a technology to bridge this gap is not due to a lack of effort. Cryo- genics, thin magnetic films, thermoplastics, magneto-optics, charge-coupled devices, magnetic bubbles, and electron beam technologies have, and are now, being investigated to bridge this gap. Some of these show great promise for reducing the access gap in the next five years.

There are a great many technologies that are suitable for fabricating memory ele- This compendium will not attempt to evaluate them all, but will be limited to ments.

those considered to be most applicable to future computer systems. This compendium ` will also largely ignore the many subdivisions of each technology area, and concentrate on the features available within that technology.

Memory technologies can be broken up into three major categories: • Semiconductor Storage - Bipolar Memory MOS Memory - - Charge-Coupled Device Memory • Magnetic Storage Ferrite-Core Memory - Plated-Wire Memory - Movable Memory (Disk-Drum-Tape) Magnetic Bubbles - - Thin-film Memory • Optical Storage Laser Memory - Electron Be am - El

Appendix E These technologies are used to implement a number of memory forms. These include: • Random Access Memory (RAM) (Fast Read-Write) • Read Only Memory (ROM) • Electrically Alterable ROM (Fast Read-Slow Write) • Block-Oriented RAM (Serial Transfer of Data Blocks) • Content Addressable Memory (CAM) Each memory form has an area of application in the hierarchy of computer systems.

This is shown in Figure E1 along with typical speed requirements. The main character- istics of the memories are that as you move away from the computer, the memory increasingly larger, slower, and cheaper.

In deciding which technology should be used, memory storage capacity versus access time is a prime consideration. This is shown in Figure E2 for a number of memory technologies. Note that RAM technology is usually limited to 10 7 bits. This is more a function of economics and the word size required to form an address than a technology limitation. Most all memory applications that require more than 10 7 bits use serial memories, where address is given to a block of data. Figure E3 shows the total time to access and transfer a block of 16K words as a function of the various technologies.

Semiconductor Storage With the advent of large-scale integration, the use of small-capacity, high-speed memories distributed throughout a system became cost effective. The first applications were in cache memories (RAM) and microprogram store (ROM). Recent advances in the CAM CAM EAROM RAM RAM BOR.AM BORAM 30-200ns 50 <600ns < 1 ms > 1 ms Cache Main Secondary Mass Computer (Scratch- Memory Storage Memory pad) u a " Micro- program < 100 ns Figure El. The Computer Memory Hierarchy E2 .r, . ^., wr...w+ :r:w..:^..a rw^r 3 '.i zW^ue^+'s^ Y^MR:5.3 .K!

sow wow n^ 1!!

I Optical ( Non-volatile) x .^ A 10 9 b CCD ai Bubbles or Semiconductor BORAMs x Serial Volatile ,n 108 ca m °' F"1 Fixed: ^Yead Disk/Drum .^ --- ------ M10 7 ----------- ------- V c.

CS U t^J d to MOS RAM Bi- Core / MOS Semiconductor for RAM polar i RAM (Volatile) CD Semiconductor 10 μsec 100 μsec 1 msec 10 msec 100 cosec 1 sec 100 ns 1 μsec 10 ns Access Time Figure E2. Access Time and Storage Capacity of Various Memory Technologies ttj CA t^ 1010 *No interleaving assumed OPTICAL MEMORIES Moveable 10 9 Head Disk Charge Semi Magnetic,, Serial Coupled BORAMs Bubbles (Non-Volatile) Devices Serial °°—r Serial Memory Serial Non- Non- Memory Volatile Volatile .^ (Volatile) Opt ical (Non Volatile Fixed Head ( U .Disk or Drum i Serial 6 i t^ Non-Volatile Bipolar Semi- P conductor MOS (Volatile) 10 5 RAM Semiconductor (Volatile) RAM or Core (Non-Volatile) -4 10 10-3 10-Z 101 1 sec t Figure E3. Transfer Time for 16K Block (including access time) • a f " a e,

Appendix E semiconductor art have moved their application into the main memory area. Technolo-_ gies in the research stage promise to further extend the application of semiconductor memories into the realm of secondary storage.

Unlike magnetic memories, semiconductor memories are fabricated with decode, sense, and drive circuitry on the chip. This results in the cost of a memory system being almost independent of memory size and greatly reduces interface problems.

Semiconductor storage is primarily divided into three technology areas: • Bipolar for high speed • MOS for low cost 0 Charge-coupled devices for serial memories Both bipolar and MOS technologies can be used to fabricate random access memories (RAM's) with fast read-write character istics-.__or read only memories (ROM's) where data is not alterable. In either technolegy,- read only devices can be programmed at the mask level or by the user in the field, with MOS technologies it is also possible to fabricate EAROM's, An EAROM is a memory that is meant to operate in a read mostly mode, but can be altered when desired. Altering an EAROM is a slow process and is seldom per- formed on-line.

Approaches are presently under development in MOS, which"may result in high-speed read-write RAM's that are nonvolatile. All currently available semiconductor RAM's will lose data if power is interrupted.

Bipolar semiconductor memories. — As in the case of semiconductor logic; bipolar technology offers highest speed in memories. Bipolar memories consume more power and have less device complexity than other semiconductor approaches and can be fabri- cated using a number of circuit forms to provide some speed/power flexibility. Pres- ently, bipolar RAM's are available with up to 1024 bits per chip and access times in the range of 10 to 125 nsec, Present-day bipolar ROM's are available with up to 16K bits per chip with mask programming and 4K bits infield programmable form. These devices operate in the 15 to 140 nsec access time range and will achieve speed and complexity improvements in the future. The power" dissipation at present is about .5 mW/bit, Because memory systems are very regular, low-cost, high-density memory systems :;can be configured from bipolar chips using multichip packaging approaches.

Figure E4 shows the lowest cost off-the-shelf semiconductor RANI technologies as a function of access time (ref, E2). This figure verifies that bipolar memories are used only where high speed is required, In addition to volatile RAM's, MOS technology is used to produce ROM's, EAROM , S, and nonvolatile RAM's. MOS ROM's of 32 and 64K bits /chip are feasible with today's technology, and field programmable MOS ROM' 's are available with capacities up to 8K bits per chip (ref, E3).

Three semiconductor approaches have been used to produce electrically alterable ROM's. Two of these, floating avalanche MOS (FAMOS) and amorphous semiconductors, have not as yet received the emphasis of metal nitride oxide semiconductors (MNOS).

An EAROM is a nonvolatile semiconductor memory that can be altered many times. Data alteration differs from a conventional RAM in that an erase is required prior to write, Most EAROM's erase on a block basis and the entire memory must be rewritten to change a single bit. The erase /write cycle is much slower than the read cycle (milliseconds versus nanoseconds), and a fatigue phenomenon limits the auinber of erase /write cycles to the range of 10 6-10 i0. The main advantage of EAROM's over RAM's is nonvolatility, over ROM's it is alterability. It is exjxx ;t^ d that EA ROM's will be used for micropro-

t

gram store, and for,g_mgra.^ and secure data areas of main memory,

e

E5 IJ Complex Bipolar I BipolarIECL I I BJILpo, ar 11 i ----goRianar I Pq U Static- MOS Al Gate W Lin'e of ^— 0.5 Dynamic 0 4 L Dynamic PMOS Al Gate-V Dynamic N-Channe-I Si Gate.:^L f* mum= I II Dynamic N - Channu I N.1, Gate

i Appendix E The MNOS and FAMOS technologies operate by trapping charge in the gate region of a field effect transistor. In MNOS, the charge is trapped in nitride; in FAMOS, the charge is trapped in the region of a floating gate. Both technologies can potentially operate as nonvolatile RAM's. The government is presently funding efforts in MNOS to achieve nonvolatility with 600 nsec read, 1 μsec write, 1 μsec erase, and 10 10 erase/ write cycles before failure. The mainproblem is pushing the technology to get high write speed.

It has been postulated that high-speed nonvolatile RAM's can be made by incorporat- ing an EAROM transistor along with a RAM cell. Although this approach would not re- quire a technology advance, it has not yet obtained contract support.

A High-speed, nonvolatile, block-oriented RAM chips are also under development using MNOS. These presently have 2K bits/chip with extensions to 4 or 8K possible.

They will be used to build large serial memories with access times of 2 to 10 μsec and data rates of 2M bytes/sec. Present block sizes range from 256 to 2048 words. Much of the emphasis on MNOS is a result of the radiation hardness inherent in this technology.

I In addition to RAM's, CMOS is being used to realize content addressable memories.

A 64-bit chip is presently available that can perform a number of search operations in 200 nsec. The large number of pin-outs required may limit growth in this area.

Charge-coupled device (CCD) memories.— Although a. CCD memory can be config- ured in a number of ways, all are basically serial in nature and, hence, are block oriented rather than word oriented. The CCD is characterized by high-packing density, low-power dissipation, and a structural simplicity that will lead to low cost.

Present-day CCD memory devices operate in a digital manner where charge repre- sents a "one" and lack of charge represents a "zero." Chips are available today with 16K bits of storage. CCD memories are stictly serial and exhibit access times in the 100 to 200 μsec range and data rates of 1 to 1OMbits/sec. Typical power dissipation is 20 μW/bit at 10 MHz and 4 μW/bit at idle speed. Because of transfer inefficiencies, repeaters (sense /inject circuits) are required about every 64 bits, Because the devices are dynamic, a minimum clock rate of 50 to 100 kHz is required to ensure data retention.

Refresh rate is a function of operating temperature.

CCD's offer significant speed, power, and reliability advantages over today's disks and drums. Because of the volatility of CCD' s, however, semiconductor BORAM's may be required in some high-speed secondary memories, despite their higher cast.

CCD's could also be used to store digital data in analog form. With analog storage, 5 to 13 bits of information could be stored in a single cell and converted to df.gital, upon readout, through a conventional A/D converter. Process problems are more: difficult _ ore than. seconds, practical analog in this approach, and if data were to be stored for m regeneration circuits must be developed (ref. EQ.

Magnetic Storage ,I For years magnetic storage has been the most common type of memory in"Use.

Magnetic storage has had the cost advantage over semiconductor approaches until just recently, and is nonvolatile and inherently radiation hard. T$e main problems with magnetic storage have been the difficulty and inefficiency in interfacing with the`^,,semi conductor devices with which they must communicate. This factor has almost completely forced magnetic memories into large-capacity applications such as main memory; and beyond.

E7 Y 1 i

Appendix E For main memory applications, the ferrite core has been the workhorse of the industry.

Where severe environments were encountered; plated wire was used. Secondary storage and mass memory applications have employed disks, drums, and tape units. Thin-film memories have been used extensively by the aerospace and commercial computer manu- facturers. The principal characteristics of thin-film memories are given in Table E1, ^Gk These electromechanical devices are slow and unreliable and will soon. be replaced in systems with high-reliability requirements. Thus,, most of the present magnetic tech- nologies may not be designed into systems in the 1980 1 s. By far the most promising magnetic technology for future memories is magnetic bubbles.

TABLE E1. CHARACTERISTICS OF THIN-FILM MEMORIES Oligatomic Film Conventional Film .F Parameter Mass Memory Main Memory 100 million Max bits per module 1 million Cost per bit 0.1¢ 4¢ to 10¢ Access time 3 μs 0. 75 μs RA 1 Drive current 30 mA 600 mA Power dissipation 98W 150W Volume 2 ft 3 0.75 ft3 Weight 90 lbs 50 lbs a J REFERENCES E1. Speliotis, D.: Bridging the Memory Access Gap. Proceedings, National Computer Conference, May 1975, pp. 501-508.

E2. Lloyd, R.: RAM Technology: MOS or Bipolar? Electronic Products, 18 June 1973, pp. 53-59.

^` t E3. Torrero, E.: Focus on Semiconductor Memories. Electronic Design, 1 April 1975, - 107.

pp. 98 t ,, E4. Anon: Analog Methods May Yield Denser Computer Memories. Electronic Design,* 15 March 1974, p. 25. 3

APPENDIX F, INTERFACE COMPONENTS AND MODULES Data Converters The booming demand for data converters has resulted in creation of a wide variety of types: monolithic or hybrid integrated circuits, potted modules, circuit boards, or rack-mounted instruments. The inherent advantages and disadvantages of each type are so different that no single , one is just right for every application, Overall system re- quirements determine the three basic criteria which influence converter selection: resolution, accuracy, and speed. Other application and budget constraints might include size or form factors, as well as-, externally required word size and speed, Digital-to-analog (D/A) converter selection criteria, - A definition of resolution, accuracy, and speed is needed as a basis for discussion of selection criteria. The reso- lution of a D/A converter is defined as the smallest discernable quantum change in the output for a single step change in the digital input, Specifying D/A converter accuracy requires a basic understanding of the more, common terminology and error contributors listed below.

• Nonlinearity or relative The deviation of the actual analog output- accuracy error from an ideal straight line drawn between the end points.

• Differential nonlinearity Deviation of the output from an ideal least significant bit (LSB) change that results from a LSB change in the digital input code, • Monotonicity The analog output remains the same or increases for increasing digital input codes.

• Glitch A transient spike that usually occurs at major carries.

The speed of a D/A converter is determined by its settling time to a desired accura- cy, Most D/A converter manufacturers specify speed for a full-scale range change in digital input codes and for one LSB change in digital input code. Other criteria used to specify D/A converters include: digital input codes; unipolar or bipolar output, voltage or current output ranges, power supply voltages, power consumption and supply rejec- tion, and packaging.

D/A converter t es. - The vast majority of D/A converters on the market today use two basic circuitsweight-resistor network and the R=2R configuration, Both terms- relate to the type of resistive ladder network used in the converter, and both types are most conveniently described for the case of a voltage-output D/A; that is, the case where a digital input yields a discrete voltage level at the output.

Weighted-resistor D/A converters: Weighted-resistor D/A converters include a I reference voltage source, a set of switches, a set of binary-weighted/precision resistors, and an operational amplifier. Each binary bit of the digital input wo ,!"d controls its own switch. If the bit value is a binary ONE, the switch closes; if it is a binary ZERO, the switch stays open. When the switch closes, the reference voltage is impressed across the weighted resistor in series with the switch, and a current flows into a summing bus, F1 s

i Appendix F li When the' currents from all of the' legs of the weighted-resistor ladder network are summed in the amplifier, the output voltage of the amplifier is proportional to the total current and, therefore, to the value of the digital input code. In general, weighted- resistor D/A converters are easier to make than R-2R converters.

R-2R D/A converters: The R-2R D/A converters also contain a reference voltage source, a set of switches, and an operational amplifier. However, instead of a set of binary-weighted resistors, they contain two resistors per bit: one in series with the bit switch, and the other, valued at one-half the series resistor, is in the summing line, such that the combination forms a pi network in conjunction with succeeding stages, In the R-2R all resistors and switches must be perfectly matched and must track each other over temperature. The R-2R is best made by monolithic integrated-circuit techniques, and its main advantage is that only two values of resistance are needed.

Multiplying D/A converters: One important type of D/A converter is the multiplying converter, which generates an output that is proportional to the product of the input digital code and a time-varying reference voltage. These converters do not include an internal reference source and can be implemented e i ther with ladder network techniques or with taped autotransformers. - Digital-to-synchro (D/S) conversion: Synchros, one of the more fundamental coma ponents of control systems, are extremely versatile, operate well over long distances and in difficult environments, and are capable of very high accuracies when correctly i applied. It is not widely appreciated that two inexpensive synchros in a simple two- speed angle transmission system are readily capable of precision to 1 part in 20, 000 a:.

a price far lower than that of a comparable shaft encoder system.

Because of their wide use in control systems, conversion between synchro and digital data is an -- essential operation. Digital computer commands must be translated into ana- log control signals and, similarly, synchro position data must be digitized for computer processing. To carry out these conversions, a variety of synchro-to-digital (S/D) and digital-to-synchro (D/S) packages is available. Some are simple converter modules; others are complete rack-mounted subsystems including sample-and-hold and multi- plexer circuitry.

Consider the simple D/S conversion circuit of Figure Fl. Weighted inputs are much as in a conventional binary D/A converter; but in this instance the load stummed r resistor plays a significant part. By correctly setting the relative value of the load resistor, the ladder network is nonlinearly loaded such that the analog output tends to flatten out with increasing digital input, with the output curve roughly approximating the first 90 degre' ;s of a sine curve. Analogously, if the .bits are switched out in reverse order starting with all switch positions on, the output curve resembles the first 90 de- Although the sine and cosine curves are relatively inaccurate, grees of a cosine curve.

the ratio of sine to cosine is an extremely accurate representation of the tangent of the Thus the network of Figure F1 can be taken as the basis for a D/S converter, digital angle.

MSB 45' MSB . 1 225' yFy E I -P Vp Ladder A.I.g NO ;wRdies network (Apprp.imate s(nd • weighted ,• - resistors -- -' LSB VR tae carrier frMeneY) N Figure Fl. Digital-Sine Conversion Network for 0 to 90 Degrees (A cosine network is identical except that the complement of the binary input must be applied) F2

Appendix F D/S converters are readily made to high accuracies such as 13 and 14 bits. The characteristic use of Scott-Tee transformers enables simpler sine and cosine voltages (90 degrees apart) rather than the 120-degree voltage phasing of synchros. By con- verting between 90- and 120-degree phasing, the Scott-Tee performs a valuable simplifi.,• cation and, at the same time, provides input-output isolation.

Although we have shown a resistance bridge as the major element in the D/S con- verter, conversion circuits frequently use suitably tapped, wound, magnetic toroids for sine-cosine function generation, These offer high input impedance, very low output impedance, essentially exact output functions, unexcelled long term stability, and very low sensitivity to magnetic noise.

Analog-to-digital (A/D) converter selection criteria. - Again the three basic criteria of resolution, accuracy, and speed a`e defined with an important fourth criterion, A/D aperture error. The required resolution of an A/D converter is determined by dividing the full-scale amplitude by the smallest desired quantum.

Errors which affect overall A/D converter accuracy are linearity errors. Initial gain and offset errors of most A/D converters are adjustable to zero leaving error com- Drift errors present in A/D converters are gain and ponents of nonlinearity and drift.

offset errors. Gain drift is more important because some loss of resolution could result if the gain is off by one or more LSB's at full scale, In A/D converters, very low gain drift temperature coefficients are very hard and expensive to achieve. Typically, 5 to 7 ppm °C represent the top of the line in mass produced A/D converters with many manu- facturers offering 10 to 20 ppm/°C for gain drift to maintain competitive prices. This specification, in addition to t1 /2 LSB linearity, contributes more than any other factor except resolution to the cost of an A/D converter.

Analog-to-digital conversion speed is defined by the Nyquist sampling theorem, which states that a minimum of 2 samples her cycle are req+aired to completely recover continuous signals in a noiseless environment. In typical instrumentation systems, noise does exist, and from 5 to 10 samples per cycle are required. For single-channel appli- cations with d-c and very low frequency signals, sample rate is usually a multiple of the power-line frequency. Most integrating A/D converters offer sampling rates at discrete multiples or sub-multiples of 50 or 60 Hz, and provide essentially infinite rejection of The minimum sampling speed required is the number of samples per these frequencies.

cycle multiplied by the highest frequency component of the data. For time multiplexed systems, the speed requirement of the A/D converter is dependent on system throughput speed and aperture; ^r•ror.

Aperture error must be examined before a final selection of A/D converter speed can be made. Aperture error can be reduced either with very high speed A/D converters or by using a sample/hold in front of an A/D converter, A/D converter !^Xpes. As with D/A converters, the vast majority of A/D converters on the market are of two basic types: the dual-slope integration A/D converter and the successive approximation A/D converter. Each takes a voltage input and puts out a digital code proportional to the input voltage.

Dual-slope integration A/D converters: Dual-slope integration A/D converters con- tain an integrator, some control logic, a clock, a comparator, and an output counter.

The unknown voltage is fed into the integrator for a predetermined period of time, as measured by the clock. Then a reference input voltage of opposite polarity is switched to the integrator. As the integrator processes the reference voltage, the output of the inte- grator decreases from the unknown voltage level to zero. The duration of the second period of integration is automatically proportional to the average of the unknown signal level over the predetermined integrating period. A digital counter then measures the v reference integration period and provides the digital code at the output.

Dual-slope integration A/D converters offer excellent noise rejection and linearity, but are fairly slow.

a F3

Appendix F Successive approximation A/D converters: Successive approximation A/D con- verters contain a comparator, D/A converter, a shift register, an output register and some control logic. The input voltage is fed to one input of the comparator, while the output of the internal D/A converter goes to the other input. Each bit line in the D/A converter corresponds to a bit position in the output register. When a conversion com- mand is applied, the converter is cleared and the most significant bit (MSB) output of the D/A is fed to the comparator to be tried against the unknown input level. The MSB output is, of course, equivalent to one-half the converter's full-scale range. If the un- known is greater than the MSB, a ONE is inserted in the MSB position in the output register. If the unknown is less than the MSB, a ZERO is inserted. Then the circuit tries the next bit in the D/A. If this bit does not exceed the input, a ONE goes into its position in the output register; if it does, a ZERO is positioned, The procedure con- tinues through to the least significant bit (LSB), at which stage the conversion is com- pleted. The procedure is similar to a chemical balance in which one weight is added at a time. The main advantage of the successive approximation A/D is speed. Accuracy is primarily determined by the accuracy of the internal D/A.

Conversion speed of the successive approximation A/D converter is based on the settling time of the MSB logic ladder network and comparator. In a single rate conver- sion unit, conversion time would be n times the time required .for one bit. Because only one comparator is used and representative hardware is limited to logic and ladder net- work, the successive approximation technique provides an inexpensive average speed solution.

Sequential conversion: Sequential conversion takes advantage of the fact that the propagation time through a chain of amplifiers is equal to the square root of the number of stages times the individual settling time, as opposed to adding up each stage. By adding a comparator for every binary-weighted network ., it is possible to take advantage of this higher speed.

Sequential conversion is used for applications requiring high-speed data conversion.

However, because of the increase in the number of comparators and the need to use an amplifier for every weighting network, the cost is considerably more than that of suc- cessive approximation. Although several products have been developed using the basic sequential configuration, they have not been as popular as modified versions of this technique which take advantage of gray code conversion to improve speed, or which use a combination of sequential and successive approximation to lower cost.

An all-parallel conversion method, developed for a 100-MHz throughput tunnel diode converter, provides the ultimate in speed but costs the most. In this configuration a comparator is used for each bit generated, and a weighting network or D/A converter increases in number of sections towards the LSB. By using delay lines to time the signal and to store the analog value between comparators, it is possible to operate the con- verter at a throughput rate of one comparator, but with a total delay of n times the number of comparators. This approach is costly as it requires a D/A converter of suc- cessively increasing complexity at each bit-decision comparator, as well as n compara- tors, and delay line storage for the analog signal, weighting decisions, and binary code outputs, Synchro-to-digital S/D conversion: To go from D/S to S/D conversion involves much the same use of feedback as D/A and A/D conversion. Typically, instead of a fixed reference, the 2-phase (Scott-Tee transformer) equivalent of the input synchro signal is applied to the two resistance bridges. When a digital input is simultaneously applied, it can be shown that the sum of the two analog bridge outputs corresponds to the sine of the difference between the synchro and the digital input angles. In effect, this sum of two analog voltages serves as a comparator output, indicating whether the digital representa- tion of the input angle is too large or too small. Suitable circuits may be devised, as in conventional A/D converters, to bring the digital angle (output) into correspondence with the synchro input angle.

F4

Appendix F An important application problem in S/D conversion relates to questions of phase shift and harmonic distortion. Depending on size and frequency, synchros may easily introduce 5- to 10-degree phase shift between the a-c line and the synchro output.

Similarly, due to bandwidth limitations, line distortion is nonuniformly attenuated in the synchro for the separate harmonics. Output and input waveforms are different, and the nonlinear properties of magnet iron introduce additional distortion within the synchro itself. Obviously, conversion means which do not take these nonideal factors into con- sideration must suffer degradation in accuracy; for example, a sample-and-hold circuit may be sampling a harmonic peak.

Digital synchro control transformers -- a special variety of converter -- are often of value in digitally controlled positioning systems.

A synchro input is applied from a standard transmitter; simultaneously, a digital command is applied. The output is a single-phase a-c signal proportional to the sine of the difference between the synchro and digital angles. Typically, this output is used as a servomechanism error signal, and is amplified and applied to a motor, which corrects either the synchro or digital input de- pending on the type of positioning transducer.

Synchro differential transmitters with a synchro and a digital input are also available. Output is a set of three-wire synchro vol- tages that correspond to the angular difference between the two inputs, Some companies offer auxiliary modules for use with synchro conversion systems. Some functions are synchro-to-d-c conversion, d-c-to-synchro conversion, precision modulation and demod- ulation, and synchro-to-resolver converters. These functions can substantially simplify system design.

The advanced state of development of S/D and D/S conversion equipment, with the well known advantages of synchros and the relatively low cost of high accuracy two-speed synchro systems, makes this approach to digital control a preferred one in many appli- cations.

Many forms of a-c-to-angle solutions are well documented in the 'literature. Six types, which form the technique's foundations use: (1) RC phase-shift networks, (2) resolver bridge or self-balancing resolver bridge, (3) linear segment function generator, ¢. (4) reference voltage generator, (5) harmor?;c oscillator vector rotation, and (6) digital resolver vector rotation. Not all of these types have been implemented, primarily due to response requirements of the analog components over the temperature range which make compensation such as capacitor trimming necessary. Several types, however, have been produced and have been used satisfactorily in avionics applications..

Miscellaneous A/D converter types: In addition to the two most widely used schemes, there are many other types of A/D converters on the market. These include single-slope integrator, triple-slope integrators, voltage-to-frequency converters, voltage-to-pulse Y rate converters, parallel-series converters, and straight parallel converters.

For slowly varying signals, either an A/D or V/F converter can produce accurate But, as signal frequencies increase, A/D 'converters cannot follow the signal, results.

and converter digital outputs may have substantial errors, V/F converters usually re- spond faster than A/D's, but they introduce their own problems -- linearity errors and temperature drifts. The linearity specification defines the accuracy with which the con- verter will change a voltage into a corresponding frequency, and the temperature coeffi- cients tell you how much the circuit drifts with temperature.

y Most manufacturers sell units that are a compromise between good linearity and temperature drift. For example, you can buy a converter that has a linearity error of 0, 05% maximum, but has a temperature drift of 100 to 200 parts-per-million (ppm) for every degree change in temperature. Thus, for a 10-C change the frequency might drift by as much as 2 kHz if you use a 1-MHz converter.

The linearity of this converter also 4 causes an inaccuracy of 500 Hz even before the drift errors are added in.

F5

*J Appendix F On the other hand, you can buy a unit that has a 0. 5% linearity but has a 10 to 50 ppm/ °C temperature drift. Here repeatability is the key. Linearity error may not be i important if you still get the same output frequency five or ten minutes later.

a Voltage-to-frequency (V/F) converters have been available in component form for only two or three years. Yet modular versions already are down in price, ranging from about $ 200 for a unit providing an output frequency as high as 5 MHz to less than $ 35 for a 10-kHz unit. Linearity error can be as good as t0. 00510 116.

The first monolithic voltage-to-frequency converter was recently introduced by the Semiconductor division of Raytheon Co., Mountain View, California. The unit contains a voltage comparator, a one shot, and a precision switched current source. It sells for only $ 3 each in quantities of 100. The full-scale frequency is resistance-programmable

t

over an operating bandwidth of 10 to 100 kHz, and linearity error ranges from t0. 0510 %, depending on whether an external integrator is used.

to t1 F M { ,' Digital Input/Output (I/O) Modules In most applications it is not enough to acquire the data; you must also send it to the processor. To do this, Analog Devices has developed the Serdex line of industrial data- acquisition and control modules. The Serdex transmitter, Model STX-1003, converts the 4 1 -digit parallel BCD code (that A/D converters can output) into two-wire, compatible, serial ASCII code. This coded output is compatible with either a. computer serial link or a data terminal serial link. The receiver module, Model SRX-1 1005, does the reverse; it converts serial ASCII to 4-digit parallel BCD for possible D/A conversion into a control signal.

T The other modules in the Serdex series include a multiplexer pair, SMX-1004 and

SMC-1007, which can combine up to 16 process lines onto a two-wire cable, and a clock module, SCL-1006, which can supply all the timing and control signals for all the other units. The clock module also supplies the operating voltages needed by the other units.

1 The transmitter or receiver costs $179, the multiplexer pair $ 214, and the clock

module $ 65.

Another recently developed system for serial data exchange is DEC's PDM-70 -- a

"I", programmable data mover with input/output slots that accept up to seven boards. The

boards accept either digital or analog data. The PDM-70 takes these data and converts them into serial ASCII for two-wire transmission. Each of the o ption boards contains a universal asynchronous receiver-transmitter that does the actual code conversion. The

t

options available include a BCD or binary input board that will accept up to a 32 bit parallel word and reformat it into serial ASCII. The BCD/binary output board does just the reverse. The analog input board can handle up to four differential channels and can convert the analog signals into serial ASCII. The converter boards have programmable gains and full-scale voltage ranges of tl. 999 V, ±199. 9 mV, and ±19. 99 mV. This board also has a mirror image board -- the analog output option.

There is still another connecting link between the sensor and the computer the

t

card and rack system. One, manufactured by Computer Products, has real-time peri- pheral cards and racks that can be assembled into any type of data-acquisition or control system. The RTP 7400 series of subsystem cards includes such functions as A/D con- version, sample /hold, and low-level multiplexing control carps. Computer input /output interface cards for almost any manufacturer's computer are available from Computer Products. The input/output expander card, which differs for each computer, controls all the cards plugged into the system chassis. Each expander board can handle up to eight peripheral subchassis, which can hold up to 16 circuit boards to perform any desired function.

^w F6

Appendix F Analog Input/Output (I/O) Modules Operational amplifiers. - Mixed linear processing continues to influence monolithic operational amplifiers. With its ion-implantation technology, National Semiconductor has succeeded in producing a line of operational amplifiers that have bipolar outputs and matched junction-FETs at their inputs. National, which calls its new process Bifet, is also using the technique for a line of analog switches and analog multiplexers. The operational amplifiers offer input offsets of 3 pA and 1 mV, and an offset drift of only 3 μV/ °C.

Quad operational amplifiers, offering the advantages of low cost and high functional package density, can now provide perform;+ance comparable to single units. Input bias currents are down around 500 nA, and output slew rates are slightly greater than 1 V/μs.

Frequency performance is also impressive, with a sma11-signal bandwidths being 1 MHz or more and large-signal bandwidths ranging from 20 to 40 kHz. Moreover, chip designs have been improved such that crossover distortion is no longer a problem when the opera- tional amplifiers must drive a grounded load while operating from a split supply„ Sample and hold (S/H) amplifiers. - To freeze rapidly changing inputs, S/H circuits are often used in front of the A D converter; however, this does not completely solve the accuracy problem. The S/H circuits introduce other errors that are not always mentioned on manufacturers' data sheets. A pedestal error occurs in S/H circuits each time the circuit switches from the track to the hold state. This stems from the capacitive transfer of residual charge across the turned-off switch onto the holdita.g capacitor. The same switch signal that controls the S/H circuit causes a small voltage spike when the circuit switches to the track mode.

Modular S/H circuits are available from many companies. Most of the larger manu- facturers of A/D converter modules, such as T ele dyne -Philbrick, Analog Devices, Hybrid Systems, Burr-Brown, and Intech, also have modular S/H circuits that include the holding capacitor. Also, some companies offer S/H modules with pinouts for an external holding capacitor. Burr-Brown, for example, has a hybrid IC S/H circuit that requires onl a holding capacitor to function. The voltage droop of this amplifier is a low 0. 1 mV)msec, and the capacitor determines the rest of the hold characteristics.

This unit, Model SHC-23, costs $45 in singles and is housed in a TO-8 metal can.

Several companies have fabricated pairs of amplifiers with the necessary FET switches as single-chip circuits which they sell as general-purpose S/H ;amplifiers.

Multiplexers. - To collect many channels of data and to combine them onto a single line, you-need either a multiplexer or relay scanner. Of recent advances in multi- plexers, the single-chip, 16-channel analog IC dominates; older modular circuits are slowly giving way to this new unit. Relay scanning circuits are advancing too, with better thermal design, isolation, and shielding methods, but scanners will be used less as solid-state multiplexers move in to replace them iri all systems except those that involve extremely low-level signals (below 10 mV).

Problems faced when analyzing multiplexer specifications include thermal and vol- tage offsets, contact resistance, switch resistance, contact bounce, switching time, and level matching.

Solid-state swi thes should be used to preserve signals buried in noise, especially in semiconductor materials often overrides low-level analog low-level signal;'. Noise signals. Mercury- vetted reed relays with switched ground shields offer the best solution.

Because low-level analog signals are usLially of very low frequency, the slowness (100 operations/sec) of mercury-wetted relays should not pose any serious problems.

F?

Appendix F For low-level transducer signals, signal conditioning at the sensor location usually allows the most accurate data acquisition. If many low-level points are grouped near each other, a low-level signal scanner or multiplexer can minimize the number of amplifiers needed. The signals are first multiplexed and then fed through a single amplifier. In this single-amplifier approach, crosstalk within the multiplexer, band- width limiting of the amplifier, settling time of both the amplifier and multiplexer, and other factors can destroy the signals. Other problems, like the need to run a line to ttG the sensor to supply power for the conditioning equipment, must also be considered.

w Optical coupler - In optical couplers, performance seems to be leveling off.

Manufacturers are concentrating more on refining technologies. For an imput current of only 1 mA, minimum current transfer ratio can be guaranteed at 10016 for a phototransistor coupler, and at around 20016 for a photoDarlington coupler. The maximum data rate of logic,-gate couplers is typically around 5 MHz, but speeds of up to 10 MHz can be realized with optimum circuit conditions. Guaranteed minimum isolation voltage for a single de- vice in a dual-in-line package can be as high as 5 kV.

Coupler prices should continue to decline for the next several years, dropping eventu- ally to the $1 level for high-performance devices that are now $ 2 or more. New types of couplers are also beginning to emerge - couplers whose switching threshold can be programmed by means of external resistors, and multichannel couplers intended for analog applicatipns. In the near future, there may be couplers having a phototriac output, or couplers whose input and output remain linearly proportional to each other.

Input/Output Components ^r Thin-film resistor networks. - Thin-fi lm resistor networks traditionally have been expensive, selling for from $3 to close to ^40 each, even for off-the-shelf standard parts.

By applying the high-volume automatic processing techniques that are used for IC I s, the Resistor Products division of Analog Devices is producing thin-film resistor networks in hermetic packages that in some cases sell for half as much as previous devices, with no degradation in performance.

National Semiconductor has announced a line of thin-film resistor networks packaged in plastic that are intended to compete with standard thick-film networks in ceramic National aims to get prices down to less than 35 cents each in lots of 100, 000.

packages.

Capacitors. - Ceramic capacitors, both chip and packaged versions, have been the Prior to 1975, unpackaged ceramic fastest growing segment of the capacitor industry.

chips were strictly fixed-value devices; now Vitramon Inc, of Bridgeport, Conn., has a line of ceramic chips whose capacitance can be adjusted incrementally without adversely affecting device performance.

Another significant step in ceramic capacitors was the successful transition from a precious-metal system to a base-metal system by USCC/Centralab of Los Angeles. The company is using a nickel alloy to make the internal electrodes and the terminations for its capacitors, permitting price reductions of at least 30o, and even 5016 in many in- stances.

x t F8 t.

APPENDIX G COMPUTER INTERCONNECTION STRUCTURES: TAXONOMY, CHARACTERISTICS, AND EXAMPLES Reprinted by permission from ACM Computing Surveys, Vol. 7, No. 4, Dec. 1975, pp. 197-213. Copyright 1976, Association for Computing Machinery, Inc.

Computer Interconnection Structures: Taxonomy, Characteristics, and Examples GEORGE A. ANDERSON and E. DOUGLAS JENSEN Honeywell, Inc., Systems & Research Center, 2600 Ridgway Parkway NE, Minneapolis, Minnesota 66413 This paper presents a taxonomy, or naming scheme, for systems of interconnected computers. It is an attempt to provide an implementation-independent method by which to. identify designs, and a common context in which to discuss them. The taxonomy is based on interprocessor message handling and hardware interconnection topology, and distinguishes ten basic multiple-computer architectures. Various relevant attributes are identified and discussed, and examples of actual designs are given for each architecture.

Keywords and Phrases: distributed processing, distributed computers, multiprocessors, multicomputers bus structures, computer networks CR Categories: 3.51 4.32 6.20 paper is an atteMpt to begin filling this need.

INTRODUCTION In it we present a naming scheme, or taxon- Currently, one of the most active areas in omy, for identifying various systems of computer architecture is the interconnection interconnected computers, and we discuss of computers to form systems which are design decisions and system characteristics called "distributed processors," "distrib- which we believe are germane to these uted-function computers," "computer net- architectures.

works," and similar names. These systems The authors know of only one other range in organization from two processors general taxonomy for interconnected com- sharing a memory to large numbers of rela- puters and that is a brief one (having differ- tively independent computers connected ent dimensions) with few system characteris- over geographically long distances. A dis- tics and no nomenclature [StEw74]. Some couraging aspect of this activity, however, is interconnection topology issues are also the almost total lack of published informa- considered in [CHEN74] and [Txux72]/ al- tion describing the rationale for various though these are primarily concerned 'with designs, or comparing the results achieved the next lower level of the intercone,ection by various approaches. In part, the authors design—control and communication. '' One believe this condition exists because there level beneath these are a number of papers has been no common context in which such dealing with the design of "explicit" discussion could take place, no set of design switches, such as crossbars [PiPp75] and issues, no list of system characteristics to be permutation/sorting networks [THUR 74].

traded off, and, in fact, not even a common nomenclature for system identification. Our In addition, there is a wide variety of digital Association for Computing Machinery, Inc. General permission to republish,' Copyright © 1976, but not for profit, all or part of this material is granted, provided that ACM's copyright notice is that reference is made to this publication, to its date of issue, and to the ,fact that reprinting given and privileges were granted by permission of the Association for Computing Machinery.

Computing Surveys, Vol. 7, No. 4, December 1975 c PRECEDING PAGE BLANK NOT FH"

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I 198 George A. Anderson and E. Douglas Jensen CONTENTS fer of information between processes in different PEs. We call this transfer a "mes- sage transmission," and do not distinguish between instances of message such as data blocks, service requests, semaphores, etc. In the interconnection structure itself we dis- tinguish two functional entities—paths and switching elements.

INTR DUCTCISI A p ath is the medium b which a mess a ge e Y DESIGN DESIGN DECISIONS—THE TAXONOMY ^ g SYSTEM CHARACTERISTICS is transferred between the Other system ele- SYSTEM DESIGN TYPES merits. Some examples of paths are wires or DDL—Loop busses, radio links, common-carrier data- DDC—Complete Interconnection DSM—Multiprocessor transmission facilities, and memories. The DSS—Global sus transmission of a message over a path results ICDS—Star in no alteration of the message.

ICDL—Loop with Central Switch ICS—Bus with Central switch A switching element is an entity which may IDDR—Regular Network i^ .

be thought of as an Intervening intelli- IDD I—Irregular Network IDs-due window gence" between the sender and receiver of a FUTURE DIRECTIONS message. A switching element affects the CONCLUSIONS destination Of a message in Some way —by ACKNOWLEDGMENTS REFERENCES altering the message (e.g., changing Its destination address), by routing it to one of a number of alternative paths, or by both actions. These notions of message, path, j and switch are basis; to the approach we s have taken.

Our taxonomy thus describes configura- a tions of three hardware archetypes: PEs, paths, and switching elements. This small data communications literature pertaining number of types leads to several simplifica- multiplexing, tions which serve on one hand to make tv queueing, routing, etc.

[MART72j ; much of this is relevant for certain system organizational issues clear, but on computer interconnection architectures and the other, admittedly obscure the noninter- connection aspects of system design. For implementations.

For the. first step toward developing a example, we do not distinguish between a computer and its interface to the rest of the common nomenclature for system identifi- cation we have restricted ourselves in several system—both are part of the PE. Neither l do we make a distinction between circuit significant ways. First, we are concerned solely with interconnected hardware units in switching and message-switching—both are accomplished by the switching entity. Per- which "processes" can execute. We use the } haps the most significant issue that is not word process in the conventional sense, and designate the hardware units as Processing treated is interprocess communication strate- n.

gies and problems, such as message ad- Elements, or PEs. By this definition we j dressing, specifically exclude single-instruction stream, deadlock, etc. By these omis- p such as sions we do not imply any relative im- multiple-data stream machines portance, but rather, we stress that we have ILLIAC IV and PEPE. We further limit our- selves to systems in which any PE can taken a limited step in but one of several t important areas. It is our hope that this step communicate with any other through the system interconnection mechanism. will stimulate similar work in such comple- mentary areas as interprocess communica- Our method for identifying the intercon- a system is to isolate the tion, as well as encourage improvements in nection structure of our taxonomy.

major hardware units involved in the trans- Computing Sutveys,'Vol. 7, No. 4, December 1975 u TRANSFER INDt ECT DIR CT STRATEGY.

TRANSFER CONTROL METHOD TRANSFER PATH PATH PATH PATH PATH PATH PATH STRUCTURE OCDS) OCOL) (ICS) (IDDR) (IDDI) (IDS) (ODU (DDC) (DSM) (DSB) SYSTEM REGULAR IRREGULAR COMPLETE CENTRAL GLOBAL STAR LOOP BUS BUS LOOP ARCHITECTURE MEMORY BUS WITH WITH NETWORK. NETWORK WINDOW INTERCONNECTION CENTRAL CENTRAL SWITCH SWITCH FtavRF 1. The taxonomy., determine whether control information is DESIGN DECISIONS—THE TAXONOMY contained in or sent to the intervenor (e.g., An interconnected computer system is the address transformation tables). Decisions result of a series of design decisions, and the made by the sender (for example, which decision space can be considered to be a tree.

port to transmit on) and decisions made bar Our model for this interconnection design the receiver (such as whether to accept .Q; process, shown in Figure 1, is a tree of four given message) do not affect the directness of levels with alternative system architectures communication.

represented as leaves. The root of the tree is If indirect communication is chosen, a the decision to interconnect a number of further decision concerning the switching computers for complete intercommunication.

method must be made. This is shown at the Below this are decision levels representing second level of the tree. The alternatives are choice of message transfer strategy, the centralization, in which a single entity method of controling transfers, and choice of switches all messages, and decentralization, in the type of path over which the transfer is which a number of intervenors are used.

to be made. The first two levels are con- The third level involves the choice of cerned with strategic (policy) issues, and the dedicated or shared message transfer paths.

third and fourth levels with tactical (imple- We define a shared path as one which is mentation) issues.

accessible from more than two points. In The first strategic choice is between direct reality, there are at least three alternatives transmission of messages from source to at may be distinguished: paths that are destination, and indirect transmission in unidirectional point-to-point; paths that are which an intervening operation is required.

bidirectional point-to-point; and paths that , taxonomy, our criterion For purposes of the I.

are bidirectional and visit more than two for distinguishing between these is the exist- points. In the first case no contention can ence of one or more switching entities which occur; but in the second, a rudimentary s make decisions for every message. Thus, sharing exists, and hence contention can intervening repeater circuits or storage ele- occur. In the third case, however, contention ments are simply instances of paths, and becomes a major consideration, so we define dd not affect the directness of the com- it as the "shared" path case and classify the munication; but an intervenor that alters the other two as "dedicated" connections. We message (e.g., address transformation), or an reiterate that the notion of "path" does intervenor that routes the message onto one not imply an implementation, and that both of a number of alternative output paths, is busses and memories can be. appropriately effecting an indirect communication. An- used as message transfer paths. It should other way to make this distinction is to also be noted that paths which are redundant a Computing. Surveys, Vol. 7, No. a, December 1975 wY 200 George A. Anderson and E. Douglas Jensen ms for fault tolerance or bandwidth reasons are Another measure of modularity is the here considered logically singular.

degree to which the location and function of The final level of the taxonomical tree the incremental element is restricted. For comprises the leaf nodes representing specific instance, in a given design there may be system designs.

particular places where a resource (processor, Before discussing the characteristics of the switch, or path) could be easily added to we system types, digress digress here to explain the produce a specific performance increase, and ^x various attributes which we feel are most other types of performance increase which significant, and to define our nomenclaWre.

are difficult or impossible to obtain in a Our emphasis will be on the implementatic'n- modular fashion. Again in this case, decisions independent issues, and on the qualitative made in the progression to the third level of characteristics of systems. We avoid quanti- the tree have affected modularity. For in- tative measures such as bandwidths and stance, this place-modularity characteristic of throughputs because they can only be Indirect Centralized (ICx) systems is poor representative of rapidly changing tech- with respect to the central switch. Replica- nologies and therefore, must be evaluated tion of the central switch to achieve an in- within the constraints of a specific applica- crease in throughput changes the basic archi- tion.

tecture to Indirect Decentralized (IDx). A For brevity, we will use sequences of place restriction can also occur in any non- capital letters to describe paths down the homogeneous Indirect (Ixx) architecture, tree, with lower-case "x"s denoting "un- since a special-purpose processor which must made" decisions. A direct, dedicated-path be added to the system usually cannot oc- system is thus DDx, and so on.

cupy a place that must perform a switching function.

SYSTEM CHARACTERISTICS to modularity, must be considered for Ixx architectures. In Dxx architectures, the Nlodularity, the ability to make incremental decision to add a processor requires no changes in system capability, is a major deliberation on the method of connection; it characteristic to be considered in the design is fixed by the system type. For architec- of a computer system. In instances where a tures allowing indirect communication, there specific design is to be configured for a can be alternatives with different costs. For variety of applications, it isoften desirable example, in a geographically dispersed sys- to vary the number of processors according tem, the cost of adding another processor at to the computational requirements of the the location of an already existing one is particular problem. This requirement occurs significantly affected by whether the incre- both in homogeneous systems (.laving only a mental processor must have its own paths to single processor type) and in nonhomogene- the rest of the system, or whether it can ous systems. One measure of system modu- share the paths already installed.'

larity is the incremental cost of adding an Another important design characteristic element, such as a processor. If this cost is is the cost of fault tolerance and the method simply that of the element, then the system by which a system is reconfigured to mast: is indeed modular; but if the addition of the faults in processors and intercommunication nth processor requires the addition of n-1 paths. The first measure of goodness here is interconnection paths, then the system is the effect of a fault. In designs where specific not €o modular. At the third level of the elements are shared (DSx, ICx, IDSx), a tree, some decisions involving this cost- single failure of the shared element can com- modularity measure have already been made.

pletely halt system operation. In other de- For instance, selection between Direct signs the structure is such that failures have (Dxx) and Indirect (Ixx) paths involves less catastrophic results. In addition to this tradeoffs between the poorer cost-modu- failure-effect aspect, it is also necessary to larity of dedicated paths and the vulner- ability of shared paths to bottlenecking. determine the costs of alternative methods Computing Surveys. Vol. 7, No. 4, December 1975 Computer Interconnection Structures Y t x of masking faults to allow operation in a done is to make relative rankings for systems degraded mode. (We maintain that a system Y under consideration. In Ixx systems, the operating in the presence of a fault is func- method by which the switching information tioning in a degraded mode, regardless of is communicated is a major logical. com- whether or not the effect is observable using plexity issue. A "chicken and egg" puzzle a performance measure.) Design decisions pertains; the switching information that r, allow this failure-reconfiguration measure to must be communicated (from somewhere in range from excellent in systems requiring no the system) to the switching resource com- overt reconfiguration and having minimal prises a message, but messages cannot be spare hardware, to very poor for those re- sent unless information for switching them quiring that the entire intercommunication exists in the switching resource. The magni- system be made redundant. A reconfigura- tude of problems arising in the communica- tion may even change the system's basic tion of switching information depends both architecture. For instance, an ICx architec- on the system's type and on its operating ture that experiences a failure of the cen- environment. ICx systems are better in this tralized switching resource may reconfigure regard than IDx systems; the more dynamic to allow decentralized communication (be- the processing environment, the more com- coming IDx) and thus avoid the cost of plicated the problem.

replicating all or part of the switch. This is In addition to the characteristics just an obvious area in which a hardware/soft- listed, which are largely determined by ware tradeoff exists, since a dynamic recon- strategic decisions, there are a number of figuration from one taxonomic architecture characteristics that are the result of imple- to another has significant software ramifica-

t mentation decisions. Among these are the

tions. physical dispersibility of the system, com- Inherent performance limitations, and the patibility with commercial communication cost incurred in overcoming them, must also paths, message transfer , delay between

I

be considered in the choice of an architecture.

(tender and receiver, and this cost of the The problem here is one of in bottlenecks iiAerconnect•ion paths. These, together with resources, due either to a nonuniform flow of the strategy-dependent characteristics, are communication within a system, or to

I de6tiled in the following sections describing

saturation of a shared resource. At the third the architectural alternatives.

level of the tree, DSx, IDSx and ICx archi- SYSTEM DESIGN TYPES tectures can be seen to be limited (i.e., to

I

have poor cost-modularity for increased In, the following paragraphs we discuss the communications rates), since increasing their significant features of each of the system performance in areas served by the single species in our taxonomy. Our first attempts shared path or switch requires significant at these descriptions were made from a com- hardware changes.

pletely implementation-independent view- The nature and number of decisions that point, a perspective which we found unten- must be made to effect communications able unless important design issues were to within a system are an important considerate be omitted. Because of this, the discussions tion. 'vV a call this attribute logical complexity 1 represent a compromise and certain observa- and use the term to refer to the totality of tions are made both from a strict taxonom- decisions made during communications, it ical viewpoint as well as from research and whether made by source and destination experience with actual designs. We also processes, or by switching entities. Logical identify particular implementations of each J% complexity is a characteristic that is signifi- interconnection type.

cantly affected by the architecture, but its major effect is on software cost. ,From the DDL—loop standpoint of the architect, this makes logi- Loop architectures (Figure 2) have evolved cal complexity an almost unquantifiable from the data communications environ- element in tradeoffs, and the best that can be ment., and consist of a number of individual 4 ; Computing Surveys, Vol. 7, No. 4. December 1975 if 'I George A. Anderson and E. Douglas Jensen failure-effect and failure-reconfiguration characteristics of DDL systems are poor, however.

A single failure in a path or a PE DIRECT INDIRECT interface causes intercommunication to stop (at least between I'Es separated by the failed DEDICATED rt,^ resource). If reconfiguration to mask the S"ARED fault is necessary, there must be a fully re- dundant path structure and sonic type of by- LAPCOMPLETE pass Switching In the PE interfaces. Recon- figuration from DDL to another structure is not an obvious option either, since the paths are unidirectional andtthe interfaces are rela- PROCESSING ELEMENT tively simple. The lugical complexity of com- munications in a DDL system is low; a,PE must only relay messages, originate messages -Z_ • COMMUNICATIONS and transmit them to a single destination, P AT" recognize messages destined for itself, and strip off messages according to the discipline.

The bandwith of the single loop is, of course, a potential bottleneck as communication FICIUm. 2. DDL (Loop).

rates increase. In addition, some loop disci- planes have the weakness that a singlo user, processing elements (PEs), each of which possibly with malicious intentions, can satu- is connected to two neighboring processing rate the entire available bandwidth.

elements,_; The traffic in a loop could, in DDL architectures that have been pro- . principle, flow both directions. In practice, posed or implemented have almost all used the complexity of bidirectional traffic has bit-serial data links as the communication constrained. all. the loops (of which the paths between PEs. This, together with the authors are aware) to only unidirectional delay involved in relaying the messages,. has traffic. In a unidirectional loop, one neighbor resulted in significant increases in message of a PE can be regarded as the source transit times around the loop. In general, neighbor and the other as the destination these systems have been designed for appli- neighbor. A given PE receives messages only cations where reliability and performance from its source neighbor and sends messages constraints were not stringent. The primary only to its destination neighbor. Messages goal of most designs has been the intercon- circulate around the loop from source to nection of geographically dispersed mini- destination with intermediate PEs acting as computer systems to allow file and resource relay or buffer units. DDL systems may sharing. Thus, reconfiguration after failure allow one [FAat^i69] or more [REAnt75] mes- has not been performed, nor has the message sages to circulatesimultaneously, and .

problem.. delay-time been. a messages are of either fixed or variable length c^ na The best-knownexample of a DDL com- [WEST72]. Some systems which have been puter system is the Distributed Computer referred to in the literature as loops contain Sys tem at the University of California, a centralized , switching function, and thus Irvine [FAxs72]. This system originally de-, appear as ICDL in our taxonomy. Other velo ed out of an interest in data communi- - systems are coupled loops with decentralized cations rather than from a concern with dis- control, which we classify as IDDI.

tributed computing, although that emphasis Both the cost-modularity and the place- was reversed early in the history of the modularity of DDL systems are very good.

project. The Distributed Computer System An additional PE can be inserted anywhere currently consists of five minicomputers and in the loop with the addition of a single com- a number of peripheral looped munication path, and the flow of messages is devices not significantly affected by its presence. The around the Irvine campus, The loop (or Computing Surveys, Vol. 7, No. a, December 1975 ^ _ I I I A

a

Computer Interconnection Structures 203 "ring") is bit-serial and operates at a data i rate of 2.3 Mbs. A multiplicity of variable-

rr/^

length messages can circulate simultane- DIRECT INDIRECT a ously. Fault tolerance is provided by a redundant loop and bypass switches.

/^/DARED DEDICATE The already good place-modularity in- herent in loops has been enhanced in the Distributed Computer System by the incor- LOOP COMPLETE poration of "soft" or "associative" address- ing of `messages. RAther than sending a mes- sage to `a physical processor, it is sent to a logical pro"?ess; the "Ring Interface" corre- sponding to: the processor in which the destination process currently resides recog- nizes the address and accepts the messages.

This allows communication to be independ- ent of the number of processors in the system, and of process/processor assign-

ments. This idea has also been incorporated i

into other distributed architectures.

3. DDC (Complete interconnection).

FIGURE – A loop version of the CAMAC data multi- lexin s ystem has been defined for both p g y maximum size of the system. Alternatively,

i

bit-serial and byte-serial transfers [AEC73].

it must be possible for all processors to 'Originally designed for nuclear laboratory accept extra connections when the number instrumentation, the CAMAC loop is appear- of PEs must be increased beyond the number ing distributed computing schemes, in of available ports. Place-modularity of DDC although its protocol is not well suited for .

systems is good, as are failure-effect and such use.

, \ failure-reconfiguration characteristics. The DDC architecture is one which can be easily

t

degraded in the event of a failure without DDC—Complete Interconnection changing' its interconnection class—a failed The DDC architecture is perhaps the con- processor, or one of the two processors

z

ceptually simplest design type in the taxon- ''terminating a failed path, can simp!;y be omy. In it (Figure 3), each processor is con- disconnected from the system. In addition, nected by a dedicated path to every other reconfiguration to an Ixx system could be messages used in event of a failed path if the software processor in the system,, and between processors are transferred only on cost ana increased message transit time the connecting them. The source incurred were acceptable. DDC systems path processor must choose the path to the destin- have no obvious bottlenecks, aria their ation processor from the alternative paths logical- low. It available, and all processors 'must be should be ndted, though, that the architec- equipped to handle incoming messages on a ture forces a location-addressing policy on interprocess communication, since switch- multiplicity of paths.

The most significant characteristic of ing within the processors and message DDC systems is their poor cost-modularity. relaying activities would put a design into The addition of the nth processor to a DDC the ICDx or IDDx categories.

R system requires not only the addition of n-1 DDC systems may be geographically ei- paths between it and the other processors, ther localized or dispersed, although there are but also, all processors in the system must fees examples of either case. The best-known have facilities for accepting the incremental instance of a localized DDC architecture is M PE as a data source. Thus, their interfaces a fully connected version of the ' IBM At- must have at least M-1 ports, where M is the tached Support Processor System [IBM], Computing Surveys, Vol. 7, No.

4, December 1975 George A. Anderson and E. Douglas Jensen -.c size of the memory. The cost-modularity of DSM systems depends almost completely /11'\ DIRECT INDIRECT on the path structure by which the proces- f sors access the memory system. If each processor is provided with a direct path, DLDICATED SHARED their cost-modularity can be poor, since an incremental processor can possibly bring \ the total to greater than the number of avail- MEMORY BUS able memory ports. Alternatively, if the memory is accessed through a single bus with a suitable allocation mechanism, cost- modularity can be very good. A DSM system is quite vulnerable to a bottleneck in which the memory's bandwidth becomes a MEMORY restriction on comnnu pication rates. Cost- modularity is poorer in this case, as it is ex- FtGURF 4. DSM (Multiprocessor) pensive to increase bandwidth of the memory or the access path. Logical complexity of in which up to four System/360 or /370 DSM systems is quite low. The failure- computers may be linked through I/O effect and failure-reconfiguration charac- channel couplers.

teristics of DSM systems are good in the Virtually all extaift examples of geographi- case of processor failures, but poor in the cally dispersed DDC systems are small event of failure of the central memory unit PEs), and appear to be ad hoc inter- (<3 (or of a shared access bus). There is also a connections of formerly existing computer software failure-effect problem because installations, as exemplified by the fully processors normally have unrestricted access MERIT connected configuration of the to the central memory, thus faulty or ma- system (BECx721. MERIT consists of two licious software can prevent or damage IBM 360/67s and a CDC 6500 located on message transactions to which it is not a three separate Michigan University cam- party.

puses, and connected by common carrier Almost every implementation of a DSM system design does have lines. The MERIT system has occurred because the designer(s) the potential for less fully connected con- wisbed the memory to be shared as a storage figurations (such as IDDI) to reduce com- place for programs and data--use of the munications costs.

memory as a communication path has almost been a side effect. In implementing this mul- DSM — tipurpose sharing, it has been found that Multiprocessor the systems' performance has increased more Certainly the most common way to inter- slowly as the number of processors incremed connect computer systems is the DSM or and, in general, systems consisting of more multiprocessor architecture (Figure 4), in than about four processors have not been which two or more processors communicate cost-effective. The reason for this has been by leaving messages for one another in a the extreme contention for memory band- width when the (functionally) single memory commonly-accessible memory. The key characteristic of DSM architectures is that must serve for all purposes. The bandwidth the memory is, or can be, used as a path required for communications alone is, how- ever, unlikely to cause bottlenecking in a rather than solely as storage.

The place-modularity of DSM systems is memory solely dedicated to this function, very good, it is possible to add processors An example of a contemporary multi- processor is the Carnegie-Mellon C.mmp arbitrarily (since the processors are not topologically distinguished), and it is also (Wur.F72], which allows up to 16 processors to share up to 16 memory modules through a possible to increase the in-transit message capacity of the path simply by increasing the crossbar switch. Currently, five PDP-11/20 Computing Surveye, Vol. 7, No. 4, December 1975 Computer T iterconneetion Structures 205 respect to the processors, and poor with respect to the bus. For PE failures, the

Ir/^

INDIRECT DIRECT DSB architecture requires no overt hard- ware reconfiguration activity to continue operation as a DSB system. Given reaso>ix- DEDICATED^ RED able care in the design of the bus interfaces, processor failures will have little effect on system operation. Failures of the bus, how- MEMORY Sus ever, are inevitably catastrophic, and repli- cation is required if the DSB architecture is to be retained after configuration. The global bus is, of course, a potential band- width bottleneck.

Much of the current interest in DSB

F^ F^

systems has occurred in the aerospace en- F IGURE 5. DSB (Global bits).. vironment, where both serial and parallel paths are being used. In these applications, the place- and cost - modularity characteris- processors are operating with negligible tics of DSB systems are particularly advan- interference.

tageous, and allow flexibility in configuring The surveys of Miller, et al. [MILL70], and systems for specific applications, including Enslow [ENSL74] include a wide variety of both homogeneous and nonhomogeneous both commercial and aerospace DSM instances of the same basic system. The machines. failure reconfiguration characteristics of the - DSB architecture are useful for these ap- plications, too, because most aerospace ap- DSB—Global Bus plications are of a real-time nature and, The DSB architecture, shown in Figure 5, therefore, excessive reconfiguration delays comprises a number of processing elements must be avoided. Serial bussing for the com- interconnected by a common, or global, bus.

munication path seems to be the more popu- Access to this bus is shared among the lar approach, primarily because the system processors by some allocation scheme, and applications tend to have high costs associ- messages are sent directly from the source ated with physical wiring, a need for phys- PE onto the bus, to be recognized and ac- ical dispersibility over electrically long cepted by the proper destination(s).

distances, and relatively low data rates.

Both the cost- and the place - modularity Replication of the communications path is of DSB systems are good with respect to the the predominant technique for mitigating PEs. Depending on the choice of bus alloca- both the bandwidth restriction and the fault tion scheme, it can be possible to add a vulnerability of the shared bus.

processor to the system in any position with Most of the aerospace DSB-like architec- little or no effect on the other PEs. Cost- and tures have been hybrids with respect to our place-modularity of the communications [ SyNis72], [ANDE73]. However, the taxonomy path are poor, however. It is not possible to military services are beginning to establish increase the bandwidth easily as needed, nor data multiplexing standards [ USAF73] that is it often possible to increase performance will require the use of DSB approaches in only where needed. Rather, to increase per- future aerospace systems ( although these formance it is usually necessary to change initial standards leave something to be de- the implementation of the entire bus or to sired, from a distributed computing stand- replicate it, alternatives which have signifi- point).

cant design impact on the bus interfaces of A pure DSB architecture is typified by one all PEs in the system. Similarly, the failure- utilizing woid-wide busses [JENs75], and a effect and failure-reconfiguration charac- philosophical derivative of it ( using a bit- teristics of DSB systems are very good with Computing Surveys, Vol. 7, No. 4, December 1975 z 206 George A. Anderson and E. Douglas Jensen respect to the cemtral resource. Similarly, failure-effect and failure-reconfiguration DIRECT /JINNDDIIREECCT characteristics are good for the PEs, and eo poor with respect to the switch. Bottleneck- ing in the switch is a potential problem. The CENTRALIZED D\ ECENTRALIZED connection flexibility of ICDS systems is poor because incremental PEs must always be provided with individual paths to the cen- DEDICATED SHARED tral switch. The logical complexity of ICDS systems is moderate. Sufficient information STAR LOOP (e.g., routing tables) must be provided within the switching resource to allow com- munications to take place, but the fact that there is only a single copy of this (usually dynamic) information simplifies its handling during reconfiguration. The poor failure- effect and failure-reconfiguration character- istics of the central resource are extended to one of the PEs in the system if switching ^.w information is maintained outside the re- source (i.e., where the switch uses address translation to accomplish message routing, FIGUia, 6. 1CD5 (Star).

and the mapping registers are under control of one of the PEs). ICDS architectures are serial bus), which has been constructed by quite common. One example is IBM's Net- the authors for the US Navy (for which work/440 [MCKA70], in which remote there are as yet no public references).

System/360 user nodes are connected over DSB is also a popular line-sharing disci- ,a leased lines to a 360/91 central controler.

pline in industrial and laboratory automa- tion applications [AxoN71], as exemplified by the CANIAC [CosT72] and IEEE standard ICDL—loop with Central Switch 458-1975 (originally Hewlett-Packard [I1NOB In a manner analogous to Direct, Dedicated 75]) data-multiplexing systems.

path (DDx) systems, the direct connections required for ICDx architectures can be ICDS--Star implemented either in the ICDS star pattern ICDS systems (Figure 6) consist of a central or in a loop, which we call ICDL (Figure 7).

switching resource to which a number of In such a system, messages are placed on the processors are connected, each by a func- loop by senders, removed for an address- tionally single, bidirectional path. Messages mapping operation by a central switching are exchanged among the PEs using the element, then replaced on the loop properly central switch as an intermediary; it is the addressed to their intended destination.

apparent destination and source for all ICDL systems share characteristics with messages. The function of the switching re- both the ICDS and the DDL organizations.

source is usually seen as "insulating" the Their failure characteristics are those of processes running on a given PE from DDL with respect to the data paths, and physical knowledge of the system, and pro- those of ICDS with respect to the central tecting them from each other. resource. Connection flexibility is improved The ICDS architecture has most features over the star in that the incremental PE in common with the DSx architectures be- need be connected only to its physically cause both have shared message transfer nearest neighbors, not to a possibly remote facilities. Its cost- and place-modularity are control element. As in DDL systems, bottle- good with respect to the PEs, and poor with necks and vulnerability to malicious users Comput, rg Sttr-eye, Vol. 7. No. a. December 1975 ^: a Computer Interconnection Structures 207 to access it. Thus, when a PE wishes to transmit a message, it must first acquire the DIRECT /JINNDDIIREECCTT bus, then transmit the message to the. switch.

From the switch, the message is retrans- mitted over the (functionally) same bus to its CENTRALIZED 000\ DECENTRALIZED proper destination. (This retransmission is the characteristic by which ICS systems can DEDICATED SHARED be distinguished from DSB organizations and from DSM systems using a single bus to memory.)

STAR LOOP As might be expected, the characteristics of the ICS architecture are similar to those of ICDS systems. By the failure-effect measure it is poorer, since the access path is no longer replicated once- for each processor.

The existence of the shared path to the switch need not contribute significantly to bottlenecking, however, since it is quite feasible to balance its performance with that of the switch. Then, as long as the two satu- rate at the same time, or the switch saturates first, the bottlenecking risk is not increased over the ICDS organization. The cost- FIGURF: 7. ICDL (Loop with central switch) modularity of the ICS system is influenced positively by the fact that the incremental are potential problems, but since these are processor need only be connected to the risks inherent also in the centralized switch- shared bus, not directly to the (possibly ing of the ICx approach, they do not neces- remote) switch. As mentioned in the discus- sarily weaken the system over ICDS. The sion of direct, shared bus (DSB) systems, logical complexity of ICDL systems is certain bus designs make this connection moderate, though slightly increased over cost very low.

ICDS due to the additional demands the The low popularity of ICS systems may be loop discipline places on the PE interfaces.

inferred from the fact that there is no com- An example of the ICDL architecture is SPIDER, an experimental data communica- tions system interconnecting eleven com- puters at Bell Laboratories in Murray Hill, INDIRECT DIRECT N. J. [FRAS75]. In this system, multiple fixed-size data messages circulate over 1.544 Mbs common carrier lines; currently DECENTRALIZED CENTRALIZED there are three loops, but only one is in use.

The central switch for all loops is a mini- • DEDICATED SHARED computer. Any computer in the loop (except the central sN%:itch) can be switched to

I

receive-only 1

in case of failure.

E3 Is ICS—Bus with Central Switch The ICS architecture shown in Figure 8 is functionally equivalent to ICDS, with the major exception that the processors are not

ff F^

individually connected to the switching re- S. ICS (Bus with centrai switch), source but, instead, share a path by which FIGUIM Computing Surveys, Vol. 7, No. 4, December 1975 George A. Anderson and E. Douglas Jensen mon name for them. The designs that do Fxist, however, use processors as the switch- DIR ing resource, with processors dispersed over geographically short, but electricafly long distances. Although nothing intrinsic to the architecture prevents the use of hardware (such as a crossbar) for the switch, tb.e speed implications on the bus, if balance is to be achieved, probably preclude its use as a practical matter. As mentioned previously, REGULAR IRREGULAR the shared bus is not normally available from commercial carriers, so ICS systems are restricted geographically.

An ICS system has been designed by Hughes for the US Navy [RoWA74]. The centralized switching resource is a special- purpose processor called the Network Manager, which interfaces with a number of functional nodes over one or more shared busses. In addition to handling interpro i c- essor communication, the Network Manager also provides a variety of other executive services for the nodes. Because the system is FIGURF 9. IDDR (Regular network).

physically localized, the bus(ses) to the Net- work Manager are bit-parallel.

tively affected by the requirement for abso- The ALOHA system [ABRA73] is a unique lute regularity. It is not possible to add only ICS computer network which uses a radio a single PE or path; rather, the size of the "bus." Hardwired and incoherent light links increment depends on the number of PEs in are also accommodated. A 24K-baud full the system, the number of neighbors per PE, duplex radio channel connects the central and the interconnection pattern. Thus, IBM 360/65 to remote terminals, which in- both cost-modularity and place-modularity clude a number of minicomputers.

are extremely poor. There is no connection flexibility. Logical complexity of the design is moderate; although many switches exist, IMP—Regular Network the regularity of connection simplifies The IDDR organization (Figure 9) com- routing. The failure-effect measure of IDDR pr^lses a number of PEs interconnected with systems is moderate-to-good, depending on dedicated paths and having identical neigh- the method by which message routing is per- bor relationships (except, perhaps, at the formed. A single PE or path failure does not boundaries). In the figure, each PE has stop communication entirely in any case, "left," "right," "above," and "below" nor need it stop any messages to which the neighbors, although other geometries have failed element is not a party. Failure- been proposed. Messages are routed through reconfiguration of IDDR systems is ex- the network from source to destination with ceedingly poor, with 100 % sparing of PEs each intervening PE determining which of and path- being required if the basic struc- its alternative neighbors should be the next ture is to bt unaltered after reconfiguration.

recipient of the message. (It may be noted If reconfiguration to an irregular structure that DDL is a special IDDR case in which (IDDE ) is acceptable, however, this short- each PE has two neighbors and there is no coming is eliminated.

switching decision to be made.) The elegance of IDDR structures has The modularity and failure characteristics caused significant academic interest but, of IDDR systems are significantly and nega- to the authors' knowledge, their practical Computing Surveys, Vol. 7. No. 4, December 1975 Computer Interconnection Structures 209 difficulties have prevented actual imple- with both processors and paths added as, and mentations. Paper designs have usually where needed. Cost-modularity is similarly been for four-neighbor (rectangular) sys- good, with incremental PEs being archi- tems, with either busses or memories pro- tecturally required to have only one (or two posed as paths. One nonrectangular IDDR in loop-oriented approaches) connections to the rest of the system. Connection flexibility system is TREE, designed at the US Navy Postgraduate School [GOOD73]. This machine is another advantage, with connections comprises a number of PEs connected as a allowed to any PE in the system. The more tree. A PE may communicate with its irregular the interconnection pattern, the superior or any of its subordinates in the more the system's failure-effect and fail- hierarchy; because there is only one path ure-reconfiguration characteristics can be between any two nodes in a tree, the logical enhanced by providing a multiplicity of po- complexity of the message routing is not tential paths between PEs. Likewise, ir- severe. TREE was envisioned primarily as regularity improves the extent to which re- being physically centralized, but could in- configuration can be performed without stead be implemented with common carrier departing from the IDDI category. The logi- lines for greater dispersal. cal complexity of IDDI systems is usually very high; at each switch, routing decisions must be based on knowledge of the overall IDDI—Irregular Networks system topology. Due to the good place-mod- ularity, bottlenecks are not a likely problem.

The distinction between IDDR and IDDI The dominant current application of IDDI (Figure 10) systems is si iply that consistent interconnection is to geographically dis- neighbor relationships are not required for persed computer networks. In such systems IDDI. Thus, a given PE may have from one the paths are supplied by a common carrier to an arbitrary number of neighbors with and the switching is done by processors which it communicates. Many of the system dedicated to that function. The (significant) characteristics vary with the degree of inter- cost due to logical complexity, and repre- connection regularity. Place-modularity of sented by the switch processors, is incurred IDDI systems tends to be extremely Food, to minimize the nun: ^)er of high-cost inter- connection paths required. Routing al- gorithms are usually inelegant, especially for the less regular systems, and ad hoc solutions are apparent. It is the authors' feeling that hardware switching facilities are ruled out by the complexity of the de- cisions to be made, and that the current practice of using processors for this func- tion must necessarily continue.

Most systems commonly called "computer networks" are IDDI structures. These are IRREGULAR REGULAR diskussed in the surveys by Schneider [SCHN73], Abramson [ABRA73a], and Rustin [RuST72], and in the bibliography by Blanc, et al. [BLAN73].

A more regular sort of IDDI system is represented by the coupled loops of Pierce [PIER72], [COKE72], [KROP72], intended for telecommunications. A number of inde- pendently controled DDL "local" loops are coupled together, directly and/or by FIGUM 10. IDDI (Irregular network) "trunk" loops (which may themselves be .

Computing Surveys, Vol. 7, No. 4, December 1975 A George A. Anderson and E. Douglas Jensen their PLUntBUS Imp [H]Enx73] (which we DDL). A variety of alternate, redundant, classify as a hybrid, as discussed in the Con- and bypass-switched loops is proposed to clusion of this paper). All of these units provide failure protection.

r.

provide a bidirectional path between the busses of two minicomputers. Blocks or .

t- IDS—Bus Window segments in the source-address space are N 'r 1 translated to the destination-address space.

In IDS architectures, an example of which is A number of these interfaces may be used shown in Figure 11, access to the switching to construct hierarchies of processing ele- resources is via a path shared by multiple ments. Simulation and programming ex- PEs. Switching is performed by more than perience by users of all three mechanisms one resource, and messages may be retrans- indicate that the logical complexity of this mitted onto the path from which they were approach grows rapidly as the number of received, or onto another.

translation levels increases, and as the trans- The modularity characteristics of the lation binding becomes more dynamic. This IDS architecture are similar to those of the type of interconnection is also subject to IDDI structure. The failure-effect and deadlock [BELL731, [CHEN74], unless de- failure-reconfiguration characteristics are signed and used with great care.

poorer, however, because multiple PEs and switches can be affected by the failure of a single path. Also, systems of this type are FUTURE DIRECTIONS not easily dispersible due to the shared Current activity in distributed architectures busses.

Digital Equipment Corporation manufac- is undeniably more on paper than in hard- tures a device called the DA11-F Unibus© ware, but there do seem to be trends emerg- Window to facilitate the implementation of ing in designs for several application areas.

IDS architectures [FiTz731, [DEC751. Similar DDL organizations seem to predominate mechanisms have been designed at Carnegie- in designs where their excellent modularity Mellon University for their Computer and compatibility with common-carrier data Module System [FuLL731, and at BBN for paths can be used to advantage, and where their poor failure characteristics and long message transit-times are not a problem.

l

Typically, the DDL designs are used to con- DIRECT INDIRECT nect multiple minicomputer systems, dis- rrg, persed over electrically long distances in university, research laboratory, or industrial CENTRALIZED DECENTRALIZED automation environments. The individual PEs are usable both as stand-alone systems and with other PEs for resource (file, periph- DEDICATED SHARED Y';lT eral) and load sharing.

The DSB organization with serial bussing BUS is becoming the dominant architecture in p•k-^ real-time control environments. These ap- plications typically have a number of itera- tive, sampled-data control loop functions loosely connected by a requirement for in- ,Tg formation exchange and centralized monitor- ing. The environment occurs in both the conventional process-control type applica- tion and in aerospace applications such as integrated avionics processing. In such sys- tems, the good place-modular ity for proces- sors in DSB organizations is particularly Fwutu, ll. IDS' (Bus window) Computing Surveys, Vol. 7, No. 4 December 1975 Computer Interconnection Structures valuable. DSB is chosen over DDL. because municate large messages quickly by use of simple redundancy of the global bus allows pointers. (They will undoubtedly continue to fast and almost automatic reconfiguration exist for their other advantages, which are after failures, and because of the reduced not related to communications.) IDDR and message transit-time.

IDS organizations both incur significant In environments where sophisticated inter- logical complexity with few compensating process communication is a requirement, the advantages. Further, IDDR has the poorest ICx organizations are a common choice. modularity and failure characteristics of Compared to IDx, the lower logical com- any of the organizations.

plexity of centralized switching is believed to outweigh its failure-effect and failure-re- configuration disadvantages. There is a CONCLUSIONS

r

great variety of system designs, particu- The notion of a taxonomy requires both that larly in the ICDS category, with varying all species be clearly identified, and that the levels of performance in the central switch methods used to make distinctions be clear

a

area. It is the feeling of the authors that as and unambiguous. Our discussion here has understanding of interproeess corrimunica- failed to achieve either of these goals com- iion matures, movement toward IDx pletely, but has, we hope, been a worthwhile structures may occur.

a

beginning. All species (systems) are not The fourth "dominant" system is IDDI, clearly identified; there are many hybrids which is uniquely suited to applications re- using combinations of our leaf-node archi- quiring interconnection of relatively large tectures. The PRIME system at the Uni-

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computers over geographically long dis- versity of California, Berkeley [QuAT721 is tances. In such systems, the high inter- physically a combination of DSM (multi- connection cost necessitates that only large processor) and ICDS (star), although logi- computers be involved. Furthermore, sig- cally it is purely ICDS since all interprocessor nificant processing power should be dedi- communication goes over the External cated to the switching function in order to Access Network, rather than through the minimize those interconnection costs. At shared memory. Honeywell's DP/M system this time, such applications have used al- for the US Air Force [ANDE73], with its most exclusively ad hoc solutions to con- global and local busses, uses two levels of troling the complex IDDI structures, with DSB. Tile BBN PLURIaus I M P for the the majority of the efforts going toward ARPANET [HEAR731 is structurally an amal- more fundamental problems of intercom- gam of DSTN7 (although by convention there munications protocols and experiments in load sharing. It is hoped that future work in is no interprocessor communication using such areas as routing algorithms and re- the local memories), IDS (for accessing covery techniques for IDDI structures will shared memory), and ICS (the Pseudo-In- complement interprocess communication terrupt Device).

research currently being conducted with Neither are all distinctions crystal clear; ICDx structures, to the ultimate benefit of we have classified systems on the basis of both.

"dominant" features, and to some degree In our opinion, the remaining five system even on our understanding of the intent, as types each have one or more significant well as on prima facie evidence. Our goals weaknesses not sufficiently compensated for in attempting to construct a taxonomy will by strengths that are useful in real-world be satisfied, however, if two effects occur.

applications. DDC systems have poor modu- larity and high interconnection costs, to the First, we hope to stimulate a refinement of extent that large systems are impractical. this approach or the development of a DSM architectures, from an intercommunica- better one. Secondly, we hope to haw, con- tions viewpoint, have little to offer over DDL tributed to a common ground for discussion or DSB structures except an ability to com- in the meantime.

Computing Surveys, Vol. 7, No. 4, December 1975 212 George A. Anderson and E. Douglas Jensen [ENst,741 E NSLOW, PHILLIP (ED.), Multi- H.

ACKNOWLEDGMENTS processors and parallel processors, John Wiley and Sons, New York, The authors gratefully acknowledge the 1974. (Survey) valuable comments and criticisms of the [FARB721 FARBER, DAVID J.; AND LARSON, KENNETH C. "The system architee- Editors and the referees Of COMPUTING ture of the distributed computer SURVEYS. We are also indebted to many system—the communications sys- colleagues who informally refereed this paper.

tem," Proc. S ymposium on Computer- Communicatioazs Networks and Tele- Special thanks go to Kenneth J. Thurber for traffic, April 1972, Polytechnic Press, his suggestions regarding the figures, which Brooklyn, New York, 1972. (DDL) [FARM69) FARMER, W.

substantially improved the readability of O.; AND NER'HALL, E. F.

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puter hardware of the MERIT C O m- AFIPS 1993 National Computer Conf., IEEE Trans. Com- puter Network," AFIPS Press, Montvale, N. J., 1973.

l ^„ munications, June 1972. (DDC) (Hybrid) !

[BLAN73] BLANC, ROBERT P.; COTTON, IRA W.; (IBM] IBM, IBM System/360 and System/ PYKE, THOMAS N. JR.; AND WATKINS, 390 Attached Support Processor Ver- Annotated bibliography SHIRLEY W. sion. 3 Asymmetrical Multiprocessor of the literature on resource sharing System: general information manual, computer networks, National Techni- GH2O-1173. (DDC) COM-73- cal Information Service, [JENS751 JENSEN, E. DOUGLAS, "A distributed 50750, September 1973. (Bibliography) function computer for real-time con- ' #, [CHEN741 CHEN, ROBERT C., Bus communica- trop," Proc. Symposium on Computer University Microfilms lion systems, Architecture, January 1973, IEEE, Dissertation 74-20493, 1974. (Control N. Y., 1975. (DSB) and Communication) [ K NOB751 KNOBLOCK, DARYL E.; L OUGHRY, H., "Ail experimental [COKE72] COKER, C. DONALD C.; AND VISSERS, CHRIS A.

interconnection of computers through "insight into interfacing," IEEE Bell a loop transmission system," Sys- Spectrum, May 1975. (DSB) tem Tech. J., July/August 1972. (KROP721 K ROPFL,' J., W. "An experimental (IDDI) data block switching system," Bell CAMAC—a mode- [COST721 COSTRELL, Louis, System Teck. J., July/August 1972.

lar instrumentation, system for data (IDDI) revised description and fMART72] MARTIN, handling; JAMES, S ystems analysis specification., National Technical In- for data (rartspzission, Prentice-Hall, formation Service, TID-25875, July Englewood_Cl,iffs, N.J., 1972. (Digital 1972. (DSB) Data Communication) p [DEC751 DIGITAL EQUIPMENT CORPORATION, [ M CKA701 MCK,J'j D OUGLAS B.; AND KARP, PDP handbook, 1975. -11 peripherals DONALD P.

"IBM Computer Net - (IDS) work/440," Com puter Networks—Proc.

Computing Surveys, Vol. 7, No. 4, December 7475 °t ^k tit This appendix deals with the concepts of modularity, higher-order language (HOL), and software verification, validation, and support. The first sections, M deal with a bottom-up approach. Latter sections deal with a top-down approach.

Each of these concepts represents an essential consideration in the design of an ,^.

effective and reliable software system. The major thrust of this study is an ' avionics application. Concepts are discussed, however, from a more general point of view whenever possible. Honeywell recognizes that avionic software has the most demanding standards of reliability. Additionally, in some en- vironments avionic software may have demanding real-time, event-oriented requirements. Generally, however, the software runs in a very fixed itera- tive environment without demanding real-time events driving the system.

DEFINITION OF THE BASIC TERMS Modularity is a term for a programming philosophy where the total sys- tem is organized by partitions. A well-defined partitioning of a system will ensure system modularity. This partitioning begins with identifying the pro- ject tasks.. Each task results in a separate and distinct program module.

Each module should have well-defined inputs and outputs, and should have clean interfaces with the other modules of the system. Modules can be inde- pendently debugged and validated. System errors and deficiencies should be traced to individual modules to limit the scope of error analysis.

A ?nigher-order language (HOL) is a computer language with relatively '- powerful primitives oriented to specific applications. The traditional level of programming, especially in avionics, has been at the assembly-language level. This approach usually requires that the primitives of the assembler used by the programmer , map nearly one-to-one to the primitives of the hard- ware implementation of the machine. An HOL relative to this basis, then, includes languages such as FORTRAN, PL/I, CMS-2, etc. However, each OPI of the contemporary HOLs differs in the degree of being a true HOL. This - is because of structural properties, as well as the requirement that an individual HOL be compared to a specific, intended range of applications.

The avionics applications are such a range. An avionics HOL offers primi- tives oriented to the functions natural in sys7tem design and implementation..

Verification and validation of systems involve testing the system to ensure that it performs as specified. Often this process is associated with exercising the implemented system. Rigorous tests of programs are not feasible because of the large numbers of combinations. Hence, verification and validation involve analyses of system behavior to arrive at meaningful testing situations.

Fit RELATION OF MODULARITY, HOL, AND VEIIIFICATION AND EVALUATION The sections below _separately discuss modularity, language, and verifi- cation. However, the three areas are very closely related. This dependence is evident in later sections. Modularity relates to language structurally.

Modularity relates to verification and validation because of the structural influences on the debugging and testing problem. Finally, language relates to verification and validation because of the support level and because of the level of the program source description in the implemented system.

C APPROACH DIS DISCUSSION Wherever possible, the study will be approached as follows. In each of the sections, existing methods will be described and/or evaluated. Then the state of the art will be discussed and -recommendations made on procedures which appear useful in the avionics environment will be made.

MODULARIZATION Z'he major concepts of modularization discussed are: Work division • Functional building blocks Also discussed is the problem of modularity and its relationship to HOLs.

Work Division and Assignments, It is traditional practice "chat when software systems are designed and implemented, the staffing of the project is aligned with the system structure.

Modularization is thus at least necessary for giving pieces of the system to individuals or groups for implementation. For extremely large software sys- tems, this practice is necessary to manage the total project. In smaller sys- tems, the primary reason is to divide the labor. Thus, in smaller systems, .

modules may not be well defined. Considerations in the larger systems tend to force a somewhat manageable division of work.

The end product of the initial design phase of an avionic system is the

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functional specification. The functional specification describes what the sys- tem will do, in terms of expected inputs, desired outputs, and a top-down definition of the chosen algorithms. Often, a functional specification will break the system down into various functional modules, along with elaborate descriptions on how these modules will fit together to fulfill the system's H2 , .

k function. Ideally, this organization would be functional., but occasionally a functional specification will be limited to certain subsets of the system en- vironment. When this happens, the interfaces toward the outside system can become arbitrary, weakening the functionality of the specification.

Under any definition of modularity, intermodule communication is extremely important. If a division of labor exists in the system implementa- tion, then interpersonal relationships are also involved. Modularization decisions often produce modules which share data with other modules, thus producing complex and subtle dependencies between modules. The usual method of managing a project is to precisely define the limitations of mod- ules and the acceptable methods of information transfer between modules.

However, more often than not, especially in larger systems, the initial specifications of -a system do not remain intact throughout the development period. This usually results in the rules for module-to-module interface being compromised and, thus, less precise.

Almost all software systems use a functional hierarchy concept; for example, avionic systems have monitors or executives. In such cases, a kernel within the system supports the basic functions upon which the remain- der of the system is built. The fact that such organizations are considered a hierarchal basis relates to the idea that an executive, etc. , is usually con- sidered to be "closer" to the hardware and, hence, a lower level module in the hierarchy. Within given levels of a system element, certain hierarchies w may also exist. Few contemporary software modules embedding major sys- tem elements define such elements homogeneously. Accordingly, avionic systems are structured layers comprising a hierarchy. However, the rela- tionships between layers or,elements are often indefinite. Different modularity criteria may have beer. applied in one module than in another. Larger sys- tems can have the if-tended hierarchy so completely fragmented that no hier- archy or ordering c',n be recognized. This is especially true of systems a subjected to a large ;number of design alterations, or having been frequently changed and patched during the debugging phases.

Functional Building Blocks As mentioned above, a criterion of modularization in many specifications is based on functionality. Each component or module is associated with spe- cific functional duties within the total system. At the lowest level, such spe- cific functional operations can be considered primitives to the system above them. To the extent that the components of the system exist at various levels, it is possible to consider the modules or primitives of lower levels as building blocks. This concept of using modules as building blocks can exist both at the language-source level (for example, in a higher-order language), and at the object level (machine code).

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A method of system decomposition, directly dependent on a source code convention is a property of a particular source language. The modularity implications of using an HOL and vice versa are discussed later. However, the notion of identifying specialized :sections of source-language code can be considered as modularization as it involves using such source-code sections as building blocks. This usage can be based on some functional or decom- positional convention. The usage may simply be to decrease source verbosity to obtain a more compact program source while maintaining access to all features of the particular HOL. Examples of such source-level building blocks are macros, and addressable data and procedure blocks.

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A macro is a parameterized prototype for a string of source characters.

The capability for defining and using macros exists in many of the contempor- ary assemblers in commercial software. When used along with assembly language coding, the macro provides the capability fora programmer to in- voke extended code sequences through simple statements asking for macro expansions. The ability to do this is equivalent to having a source module r (the macro prototype) which performs a given function (produces the extended code sequence).

An addressable data or procedure block is an element of an HOL which can be retrieved from a library of such blocks. An example of this in a commercial application might be the existence of a standard library of COBOL data divisions pertinent to a class of applications. Obviously, this type of source-level modularity is closely related to the syntactical structure of a particular HOL. In a block-oriented language such as ALGOL or PL/ 1, procedures and structures global to the outer block constitute building blocks as if the source existed in a block containing the program. Such a concept can be used as a basis for specialized applications where the specialized program has a set of global procedures or structures available.

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Object-level modularity is the traditional approach to breaking down an avionic system. An object code is that code upon which the physical machine operates. Modularity at this level results either from program development directly at the object level via very low-level languages, or from a mapping

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directly from source-level modularity, such as FORTRAN. The functional decomposition imposed on the avionics system is carried down to a ,partition- ing of the object program along the same lines. Certain common functions

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need not exist in parallel if there is the concept of a library of object modules.

Library object modules imply an off-the-shelf capability for these soft-

ware modules. After all new source codes have been compiled to object- code, T

a binding process is invoked which references the library as necessary to build a completely bound system. However, the notion ofbinding actually implies a dual-level program construction. The first is the construction of

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object modules; the second is the binding of the object modules to arrive at the total system. Because this process implies that the module definition z exists at the machine level,- the organization aspect of the total system con- struction is, at best, primi^ive.

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f Modular' also exists ' avionics s s rty xi msystems in the form of executive func- tions. Program modules at object time have available a set of functions with- in the executive portion of the system.

In this respect, any service mod,- ules in the executive end available to the supported program modules are available to these modules as library functions. Examples of this type of feature would be interrupt, routines, input/output service routines, or con- trol exchanging functions. Because these facilities are eac^ernal to the source module produced by the programmer, these facilities cor;x-espond to object- level library functions.

Problems In a highly modularized system exhibiting hierarchy, the actions of a specific module at a specific functional location within the total system must be carried out via manipulation of its local data structures and via demands to other modules. In this respect, then, a structure imposed by a particular modularization scheme also imposes a range of functional operations upon individual modules within the structure. The problem often occurring in systems subject to evolutionary development is that the available operations are insufficient to accomplish the desired task r%atching or violating the overall functional structure create a system in which modules are not clearly distinguishable at either the source or object level.

Because modules depend on the execution of other modules, changes in one module will affect the execution of others. This problem is difficult be- cause the interface definitions may be too imprecise to identify dependencies.

Usually this happens when the dependence; is too loose. In effect, this means modules share these data structures, and changes in one module can have subtle, but disastrous effects on other modules.

To summarize, modularization can introduce rigidity into the functional structure of a system and create interdependencies between system elements which make execution unreliable. Proper modularization can minimize these A partitioning of the system must recognize both current and two effects.

Module interfaces must be made explicit and data potential requirements.

structures should exist as entities local to specific modules.

Relationship of Modularity to HOL As discussed above, modularity is the partitioning of an Gvionics system Furthermore, this partitioning into various functional pieces or elements.

usually allows individual modules to reflect both functional and structural This implies that the modularization actually embodies the evolution designs.

As an avionics system is imple- of the system conceptualization or design.

mented, it is documented and described in terms of the basic modules of the Depending on the level of the description and the modularization, system.

modules may be considered functional primitives of the system.

H5 Because modularization relates closely to the system concept it is impor- tant to consider how modularity relates with the use of higher-order languages E (HOL). This involves how the concept of modularity relates to language struc- t ire, z,nd the concept of a library in terms of language and modularity. (An actual description and evaluation of most HOLs is presented later. ) Most HOLs consist of a set of statement prototypes, which represent language primitives. In addition, HOLs contain conventions dictating pro- gram and data structures. For example, several HOLs embed the concept of a subprogram, in terms of a function, a subroutine, or a procedure.

Withii such subprogram units, provision exists for internal and external t: data associations, in addition to a capability of formal parameterization.

Other HOLs imply a block-oriented structure, either instead of, or in addi- tion to the subprogram concept. These structures allow locality of data structures to individual blocks in order that programs can be structured as hierarchies of modules.

The structural capabilities of a chosen HOL influence, to a large degree, the modularization considerations of systems implemented in the HOL. The capabilities of an individual HOL in the areas of data structure and associa- tion to local program elements as well as interface conventions between program elements help define the eventual modularity of a system. In considering potential HOLs for the avionics application, the prime consider- ation must be how well the modularity natural within the candidate HOLs fit:; the avionics system requirements. On the other hand, once an HOL is Pstablished as the language for an avionics application, the final design and implementation should exploit the capabilities of the HOL. Modularity based on language constructions is essential to ensure an efficient and comprehensible system.

A library consists of a set of modules compatible with a given language P.. t and functional system basis. In the avionics application, a library would consist of functional modules with interfaces compatible with the individual language employed in the system implementation. This modularity can exist either as structural entities implying object time modularity or as source structures implying source time modularity. In either case, a library is characterized by functions which can be concisely and precisely defined.

Using a library increases economies in implementation and development.

Assuming that an HOL and library are properly matched, the actual source` which must be provided for a new avionics mission can be minimized because of the use of library modules. This provides benefits in terms of reduced costs and increased reliability due both to tested library modules and fewer new sources.

The library concept does have its disadvantages. Perhaps the most serious is that library modules must be very precisely.. defined. In a spe- cialized application such as avionics, it is essential that module interaction H6 with the total system be completely predictable. Thus, the library concept YP y p has the disadvantage of a less exacting functional specification and documen- tation. To the extent that library modules represent natural constructions within a particular fOL, this problem can be simplified. For example, if a particular HOL provides clean module-to-module interfaces with established communication protocols, then modules from a library could be specified in terms of such a protocol. This would eliminate the need to document those details embedded in the HOL.

The Notion of Optimal Modularity Many of the concepts noted in the recent literature represent a new conceptual viewpoint as to one functional and physical structure of programs.

This material is applicable to more general systems than avionics systems, but certainly applies to them as well.

Optimal modularity is considered in terms of vertical and horizontal modularity, in terms of code and data structure dependencies, and in terms of the concept of a useful abstraction.

The concept of vertical or horizontal modularity relates to the ordering of a hierarchy of modules into a tree of dependencies. The depth of the tree represents the degree to which the hierarchy is vertical, while the width of the tree represents the degree to which the hierarchy is horizontal. If we assume that a system consists of P primitives and is organized into N mod- ules at a single level, then Figure H1 represents a plot of the structural complexity of the system. Here we assume structural complexity to be a function only of the number of primitives, N, in a given module.

As shown in Figure H1, considering the entire system to be one module of P primitives is equivalent to considering the system to be P modules, each with one primitive. If we assume that the total system complexity results from N modules as primitives of the global system and from P/N primitives within individual modules, then the total system complexity, TSC, is TSC = F(N + P/N).

If the function F behaves monotone increasing with its argument, then the total complexity would be minimized for N = P. Such models do not apply to more realistic problems but even then the behavior of the TSC func- tion must be considered. In general, the payoff in the modularization of a system is significant only if the degree of modularity is not to either of the extremes of vertical or horizontal modularity.

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COMPLEXITY- OF MODULES NUMBER Figure H1. Complexity versus _Modularity A module can consist of a combination of code and data structures.

Depending on the criteria used for module defintions, the code of a module will interact with data structures local or global to the module. Data struc- tures which are local to a module are those accessible only from within the module. Data structures not local will be considered global. As we have discussed above, the degree of global data referencing in a modular system is a function of the formality of the interface conventions between modules.

In a rigorously interfaced modularized system, for example, the only global data structure references allowed might be via a formal parameter mech- anism.

Recent papers by Parnas (Ref. Hl) and Haney (Ref. H2) show the impor- tance of the relationship between the code and data structures of modularized systems. Work reported in these papers indicates that intermodule depen- dencies, because of shared structures, contribute to system complexity.

Parnas deals with the criteria of module selection and concludes that good modularity must be oriented about the data structures of the system.

Individual modules should reference only local data structures. All data structures of the total system should ideally be hidden within specific modules.

Such a criterion would imply that the modularity of the system would not necess- arily follow the lines of functional decomposition.

H8 Haney deals with the statistical dependencies between modules in the presence of corrections being made in individual modules. His analyses ' show how changes in a system can cause ripples to propagate throughout the system. The key to a well-modularized system is to minimize the ripple and to make modules as independent as possible. This relates to the criterion proposed by Parnas, as hiding data structures within modules minimizes intermodule dependencies.

Liskov (Ref. H3) introduces a design methodology for software systems.

This is the concept of a "useful abstraction'', and demonstrates how such constructions can be embedded as modules in a hierarchal system. Accord- •a ingly, this methodology represents a criterion for modularity. The criterion consists of a. system structured as a hierarchy of partitions, each level depen- ding on the useful abstractions (modules) of the next lowest level, with the total connections between modules minimized.

Notice that what Liskov proposes does not necessarily coincide with the } criterion of Parnas. The useful abstraction of Liskov may, for example, be a global data structure. However, all schemes emphasize the idea of mini- mum connection. Selecting modules should be based on a scheme which allows each module to be independent and which formalizes intermodule con- nections.

ource Level Modularity S d^ The concept of source level modularity has been mentioned above as a convenient way to economize in producing a program source. Also, the relationship between modularization and HOL was related to the formal binding of program and data structures. The issues of modularization and HOL arise because of the need to transform a specification for program behavior into a working avionics system. Modularization is a tool for break- ing up a very complex system into pieces which can be handled more easily.

Parnas (Ref. H1)has suggested that the modularity used in system construction need not exist at the final implementation of the system. This section discusses how modularity might be maintained at the source level, and outlines advan- tages and disadvantages of various levels of source definition.

Modularity can exist only at a source level if a suitable HOL is used.

Because compilation of the HOL source must result in the integrated and deployed state of the system, the HOL must include those constructions necessary to describe the desired application system. Among the features most desirable are facilities in HOL for exploiting architectural character- istics of the hardware. However, in recent years there has been a growing interest in developing machines designed to execute specific HOLs, both

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indirectly and directly.

H9 t A second requirement to facilitate modularity at source levels is for a reliable implementation of the HOL compilation tools. Errors resulting during the compilation or assembly of the system are as damaging as those - contained directly in the source code of the system. Furthermore, if the use of source-level modularity with HOLs is to provide optimized (in some sense) object systems, the resulting object code will be very difficult to test independent of the structural organization of the HOL. This is due to the difficulties of exhaustive testing programs.

rigid standards to ensure

Avionics systems have been subjected to very

system reliability. It is common practice to perform binary comparisons of software modules to verify correct avionics programs. As the debugging process produces various patches to fix errors, these patches are cemented into the module because of the binary-verify. Needless to say, this produces software modules which are not cleanly constructed. The problem with this }- type of approach is that system reliability and validity are tested and main- tained at the object level. In the case of source-level modularity, changes during the debugging phase must be based on the functional behavior of the system and verified on the same basis. The result of source-level mainte- nance is a total system which retains more of its original functional charac- teristics.

HIGHER-ORDER LANGUAGES This section discusses the attributes and capabilities of HOLs.

Discussion o f HOLs and Avionics A programming language represents a computer program design in a form capable of being converted into machine language. The language is used to describe the data and variables which will be used during the execution of the program, to define the procedures which will act on the data and to con- trol the intermediate translation and loading activities which transform the source code into the machine code.

There are many modes of communication which could be used to pro- gram a computer. Console switches, patch boards and two dimensional CRTs are examples of methods used for special purposes. However, for general purpose programming, sequential input devices employing a fixed character set are the normal mode. Sequences of these characters specify the design which is to be communicated to '-:-e machine.

Two distinctive aspects characterize a programming language: syntax and semantics. A language is usually considered to consists of a character set and a set of grammatical rules which define the syntax of valid state- ments in the language, if the syntax rules apply. A programming language H10 V f :_ also ha.s associated with it a set of semantics or meanings associated with valid syntactic statements. For example, the FORTRAN statement GOTO 234 obeys the FORTRAN language syntax rules, but to be valid semantically there must be some other statement with the label "234".

A third important aspect using programming languages is the prag- matic implementation of the language compilers. These characteristics are related to the convenience and naturalness of using the programming language. Pragmatic characteristics are dependent as much on the imple- mentation of the programming language compiler as they are on the syntac- tic and semantic definitions. These characteristics can also be subjective in that they are colored by the user's preferences and habits and can be hard to qualify. Yet, pragmatic characteristics may play as important a part in determining whether a programming language can be used successfully in a specific application as the technical syntactic and semantic characteritics of the language.

Honeywell's approach to programming language for avionics is twofold.

First, we will discuss some constraints placed on the use of programming languages in avionics applications ana list general language characteristics required. These requirements can then be used as a filter to eliminated. non- responsive programming languages. Some technical characteristics of the most eligible languages will then be tabulated to show similarities and differ- ences.

Programming Language Levels One gross way of separating programming languages into classes is to assign a notion of "level' to them. A low-level language implies a direct- source code to object-code translation, and forces the programmer to work at the level of the machine instructions of the computer which he is using.

A Higher-Order Language (HOL) allows the programmer to communicate more in terms of the natural language of the application area.

Low-level programming languages are machine oriented and usually have a very simple syntax. The following are examples of low-level lan- guages: • Binary or octal - The programmer directly codes the object- program i pa terns. There are no constraints or formalisms.

This is the most primitive form of programming, but is still used even with high-level languages for the presetting of data in tables.

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s Assembly language - Some constraints are imposed. Symbolic operations and addresses and minimal syntactic and semantic Hil I I checks are provided to help the programmer. In simple assembly languages, one source statement translates to one object machine instruction. However, macro- and meta- assemblers can be extended to be very machine independent and produce one source statement to many object statement translations.

• Special Purpose Languages and Processors - There are low- level languages which are oriented owar special application areas. They are low level in that there is a very direct corre- spondence-between the source code and the object code. Seman- tically they may be as powerful as some higher-level languages.

Examples of such languages are string- and list-processing languages. Symmetric List Processor (SLIP), for example, ^J is FORTRAN-based and uses the syntax of the FORTRAN CALL statement. SLIP can be considered a low-level language in that only a very restricted set of FORTRAN statement types need be written by the user. Another example is Bell Telephone Laboratory Low Level Linked List Language (L 6 ). In terms of capability, L 6 is about equivalent to SLIP, but has its own special syntax.

High Leve 1 Languages Following are some of the characteristics which distinguish high-level languages from low-level languages: a In a high-level language, a compiler is involved in translating the source code into the object code. In low-level languages, the translation usually only involves a simple replacement of } symbols for their numeric codes.

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x • In high-level languages, the symbols used represent and have associated with there the attributes of more complex objects.

E In low-level languages, symbols usually only refer to simple values, or to addresses holding the attributes of the complex objects. For example, in a high-level language, the fact that a symbol represents a matrix va.,ia.ble can be directly commu- nicatud to the language compiler, 1,=rhereas in a low-level lan- guage only the address is communicated and the programmer must mentally (or through comment cards) keep track of the fact that he is working wit1 a matrix.

• In high-level languages, one source statement will usually be x translated into many object code instructions.

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In high-level languages, extensive transformations ma y

be performed on the source code to optimize the object code. For a low-level language, the translator usually only performs direct one-for-one translations.

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• Programming in high-level languages forces program structure and discipline.

What can and what cannot ` be done is controlled more rigidly in a high-level lan- guage. As a result, programming errors and program- ming costs are reduced. However, if the control is so rigid that the programmer has to use tricks to get around a language restriction to get his job done, or if not enough control is left to the programmer to allow him to generate a sufficiently efficient code, the high-level language can ' become a great enough burden that it becomes more cost- effective to use a low-level language.

General Language Requirements Before getting into details about the specific requirements placed on H programming languages used for avionics applications, we can list a few general characteristics which are not technical in nature, but which impact the relative succe s of programming languages.

Some of these characteristics and their relative importance may have to be evaluated subjectively. For example, relative ease of modifying is a .. characteristic influenced as much by the compiler and file support system for the language as by the language itself. Furthermore, if two users have two different types of changes to be made, the ease of making them may vary ! for the same language and support system. Also, one language may be speci- fied such that relatively few user-initiated changes have to be made as com- pared to a second language. Therefore, the relative importance of the lan- guage characteristics defining ease-of-making-modifications varies.

M With the above caution in mind, some general programming language characteristics are listed below which are important to avionics applications: ^` • Commonality of Use -- The extent to which a programming language is to be used is a very important characteristic.

For example, FORTRAN is used very widely, and, therefore, retraining programmers for a FORTRAN project is minimized.

Also, there is a large data base of programs which may be usable in the project. Commonality of use can compensate for that a language may have. many other shortcomings H13 r

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• Consistent -- Applying the same language rules for all similar source cases is very important. Otherwise, the programmer has to be more concerned with the consequences of exceptions than t in getting his problem solved. For example, in standard FORTRAN an array index may only be of the form c*v+c, where c is a con- stant and v is an integer variable whereas any expression which, evaluates to an integer could be accommodated.

• Generality -- The language should be sufficiently general to be applicable to a wide range of avionics programming problems.

This characteristic must usually be traded for compiler effi- ciency and for developr^ierst costs. If the language is not general enough, dialects and extensions have to be used, thereby violating the commonality-of-use characteristic. If, on the other hand, the A language is too general, compilation efficiency may be degraded to an extent that it is no longer practical to use the language. If a switch to another language is required, the commonality-of-use characteristic is again violated.

• Efficiency balance -- A programming language can be evaluated for efficiency in at least four respects: writing speed; reading convenience; compile speed; and execution speed of the compiled code. Writing speed refers to the relative speed with which the programmer can write the code. If a language forces the use of long key words and identifiers, the preparation of the code J can be slow. Reading convenience refers to the ease with which the original or another programmer can extract the meaning of the program from the source code. Compile speed refers to the relative speed of converting the source code to the object code. Compile speed is most directly related to the implemen- tation of the compiler for the language, but may also be influenced by language characteristics which force the compile algorithms to be slow. The execution speed of the compiled code is again more a function of the compiler implementation than the language. How- Aj ever, there may be restrictions in the language which make opti- mization impossible to perform, or at least sufficiently difficult so that they are not cost-effective to include in the compiler.

• Ease of creating re-usable modules -- If a frequently used function can be programmed and parameterized so that it can later be re- used rather than reprogrammed, software development costs can be significantly reduced. The ability to re-use previously pro- grammed modules and the desire to do so depends strongly on the support software systems on which the compiler is implemented, on the compatibility of the compilers (if a number of installations are used), and on the political and pricing characteristics sur- rounding a development effort. The language has to be able to support modularity and have good parameterization and parameter passing capabilities.

ryrx • Transferability of code -- The ability to transfer a program written for one machine to another is an important character- istic for avionics applications. Even though the programming language may be machine independent, programmers must often use data and program structures in the source code which they know will result in efficient structures in the object code.

If this is done extensively and without discipline, the resulting source code may be tied very strongly to one object machine.

w Ease of making modifications -- The relative ease of making changes to the source code may be important. But this cLiaracteristic is also associated more directly with the compiler support system than with the language. The source code struc- ture and macro preprocessing capabilities of the language do affect the relative ease of making modifications.

• Comprehensibility of code -- A Ian I quaga with an easily under- stood code is also o imp -g iant. The 'program source represents the final authority for the problem spcccification. Insofar as this source provides direct documentation, problems concerning the communication of programs can be removed.

Avionics Environment Implications Since a programming language is to communicate. a program design, it is important to match the language with what is communicated, within what context it has to be communicated, who communicates it, and to whom it is communicated.

What is communicated -- In the avionics environment a program- ming language represents primarily the operational software which will be executing on the avionics computer during mission time. Following are examples of the types of operations and functions which must be represented s in the programming language: • Mathematical functions - Real number operations (floating point and fixed) - Trigonometric functions - Coordinate transformations - Vector and matrix operations (these can often be simplified) - Integration functions • Conversion, sorting, list processing H15 } • Data packing and unpacking (bit picking and packing in particular) • Executive, low-level I/O and digital communications control Note that the following types of functions are specifically excluded: • Support software related functions - compilations, file operations formatted input/output • Complex number operations (perhaps these functions will be used more extensively in the future).

In what context are designs communicated -- To reduce software development costs during deployment, the tools and languages must be speci- fied so as to be optimally matched to the tasks during the various phases of system deployment. But, before this can be done, we must identify and ana- lyze the activities during a deployment which contain software development activities.

A set of deplo3r'nent phases was postulated with the intention that these would represent typical sequences of steps which will be traversed before an avionic data processing system is fully deployed.

The phases in the deployment are shown in Figure H2. Each will be briefly described and discussed regarding its software implication.

• Systems Requirements Definition - The required functions and major constrains on the avionics system are specified.

At this stage in the system design only rough data processing requirements are formulated. No approach need be specified.

It is assumed that no software tools or languages are used in this phase since the req.;airements are expected to be in English or mathematical equations.

• System Feasibility Stud The requirements are studied and system solutions postulatel. High-level system analysis tools are used to evaluate the alternatives to determine the feasibility of the approaches.

It is assumed that high-level simulation languages and other system analysis tools are available to the developers.

• Detailed System Functional Design - During this phase of developing the deployed avionics system, detailed solutions are developed for the data processor configuration and software. Designs are also developed for the environment simulator, which will be later used to verify the system and for the interfaces to the non-data process- ing components of the avionics system.

H16 y ► r s i a_ s., r 3 A 3 ,i. ., i SOFTWARE MODULE \ DEVELOPI-ENT SOFTWARE } IMPLEMENTATION DATA / AND INTEGRATION PROCESSING HARDWARE ONFIGURATION PROCUREMENT I N w AND INTERC^lNNEGTION ESIGN / AND BUSSING) \\i SYSTEM NA OPERATIOL AVIONICS MAINTENANCE SYSTEM / DATA SYSTEM DETAILED FEASIBILITY VALIDATION SYSTEM PERFORMANCE —^ PROCESSING REQUIREMENTS-- ► —^ SYSTEM AND PERFORMANCE- STUDY EVALUATION SYSTEM DEFINITIONFUNCTIONAL AND IMPROVE- ENVANCEMENT EVALUATION (SYSTEM VALIDATION DESIGN MENT ANALYSIS) (ARCHITECTURE ; I AND SOFTWARE) ENVIRONMENT PHY CA L SIMULATION ENVIRONMENT ( ' DESIGN SIMULATOR DEVELOPMENT I MAJOR CHA GE MA OR DENSOIGN OF SCOPE SUBUNIT DEFICIENCY IMPROVEME?JTS NON-DATA CORRECTION ADDITIONS REPLACEMENT PROCESSING O ^°+J HARDWARE f DEVELOPMENT/ t in PROCUREMENT II b 0-4^ Figure H2. Anticipated Deployment Phases M

r

The development of the configuration and software module designs will involve iterating through a sequence of solution refinements.

At the start of the detailed design only a rough, high-level picture of how'the system operates is known. Through the sequence of refinements, the developers will eventually arrive at a configuration and software design in which the data sets are partitioned, the pro- cessing functions allocated, and rough data rates known.

The tools which will be required include high-level system simu- lators, processor simulators, code generators for the processors, and tools to extract performance and timing characteristics from code samples. Ideally, only high-level languages should be re- quired in the detailed design; but some low-level code generation will have to be used, at least during the development of timing characteristics.

• Software Module Development -- More than likely each deployed system will have at least some unique functions. Specific sub- systems for which this may be true include display processing, weapon control, and electronic warfare. The software modules required to implement these unique functions can be programmed in a high- or low-level language. If no future use of the modules is seen beyond the system for which they are being implemented, generality and concurrency can be sacrificd for lower develop- ment costs of the modules.

• Configuration Dew - This phase of the deployment of the system involves the selection, specification and design of the specific busses and processing element components which will be inter- connected to realize the data processing system.

It is assumed that code generators for the selected high-level language will be available for all processing elements, and that code generators or at least macro-type capabilities will be avail- able in the support software systems so that new functions can be adequately programmed and integrated into the rest of the system.

Adding a new hardware functional unit implies that there must be a parallel effort in software development to guarantee programm- ability and compatibility with existing system communication con- ventions and procedures.

• Software Implementation and Integration - The modules developed for the specific system an tRe moT Ns from the library are inte- grated according to the specification of the system configuration.

Included in this integration process is the functional testing of the modules at the various levels of integration.

l I I

Implicit in this phase of software development is the presence level interpreter and some convenient means of at least a high- of specifying integrated. module tests. As more and more mod- ules are brought into the test cycle, the need for automatic integration tools and a simulated executive become inar+*p nounced. The functo.n_of the integrati on tools at this stage is to eliminate unnecessary computations and, therefore, make the testing more efficient, The simulated executive is required when the integration of the modules arrives at a point where actual executive functions are required in the simulated system to realistically test, Vhe integrated modules.

Environment Simulation Des' n - The purpose of this phase is to develop environment Simi rs which will be used. in non- real-time and in real-time simulations of the avionics system.

These simulators are viewed in our context primarily with the intent of validating the data processing system, and in deter- mining realistic performance characteristics of the system.

wu Initially, a software simulator of the environment is required, but this simulator need not run in real time. This simulator is used to drive high-level simulations of the avionics system, - and is used to simulate external responses during functional software module tests.

Later in the deployment cycle, a real-time environment simu- lator is required to drive the prototype system at real-time speeds.

System Performance Evaluation - The software modules have • been integrated and testedunc Tonally. Now realistic physical processor implementation characteristics must be applied in a simulated environment in order to get an initial validation of the system performance.

During the detailed functional design of the system, performance assumptions had to be made to arrive at a first design. This phase represents the first opportunity to verify that those assump- tions were in the right ball park. If they were not, corrective re- designs are still reasonable, since the system has not yet been.

committed to hardware. It is expected, though, that the system developers will become proficient in their design of later systems.

Eventually the results of this preliminary system performance evaluation should indicate the need for only minor design improve- ments k, J11 H19 This phase requires further use of the compilers, integration tools, and executive functions. Also, the simulators of both the environment and the processing elements and performance measurement tools will be required. The developer controlling the performance evaluation runs will need to know only external physical process characteristics.

• Data Processing Hardware Procurement and Interconnection - This phase of the deployment of a system includes the procure- ment of a prototype of the designed hardware and the intercon- nection of the components. No software tasks are included in this phase.

• Data Processing System Validation - The data processing system hardware has been implemented and the software for the data processing system developed and validated. This phase brings these two together and performs a validation under what appears to the data processing system as real-environment conditions.

Any critical interactions not accurately reflected in the simulators or functions which were not properly specified (but perhaps accu- rately implemented as specified) will be caught at this phase of the deployment. (Note it is assumed that deficiencies uncovered here are those of system designers, and those resulting from inaccu- racies in the software simulators. ) During this phase of the deployment, the developed software will be handled extensively but will not be altered functionally. Per- formance monitoring will be done during the validation, implying the need for software hooks.

• Avionics System Validation and Improvement - During this phase, the entire avionics system is validated. It is assumed that neither the data processing hardware nor software will require much atten- tion at this stage (other than possibly monitoring).

Explicit software tools required at this phase of the deployment are the software hooks needed to monitor system performance and support software to analyze the results of this monitoring.

• Maintenance and Enhancement - This assumes the normal opera- tional mode of the avionics system containing the data processor.

Diagnostic tests are required for two purposes: to verify that the components within the system are functioning properly; and to diagnose and isolate a detected error. The latter requirement can be further subdivided into the diagnosis of errors to initiate real- time recovery procedures, and the diagnosis of errors during non- operational periods to repair the system.

H2O I Who communicates the design -- The `tools and languages required for use in the deployment of an avionics data processing system must be designed so that information flows between the support system and the user as freely as possible. This can only occur if the tools and languages are matched to the background and functions of the developers.

Table H1 lists a postulated range of developers, their functions, their backgrounds and the kind of tools and languages which they will probably use as they develop a specific avionics system. Though the list is not neces- sarily complete, it already shows a requirement for a wide range of language levels and tools which the language must drive.

An objective in the specification of the support software tools should be to exploit commonality in the development of the tools and languages when feasible. Flexibility and level ranges must also be associated with the lan- guages so that the developer with a rich theoretical background can communi- Cate with the tools at a high level, and at the same time the developer who has a less complicated function to communicate is not forced into learning symbol definitions and concepts not required to perf orm his function.

Sum mary of information communication: what; b y whom; to whom -- The characteristics of the avionics system to be deployed and the characteris- tics of the processors being used are the basic factors determining what infor- mation has to be communicated to successfully implement the avionics system.

How the information is communicated depends implicitly on who generates the information, on who receives it and on what is being communicated.

The deployment characteristics pr--sented previously v.°ere reviewed and some of the more important items identified which had to be communicated.

For each of these items it was then postulated who would communicate the item, who would receive the communicated information, and, finally, how the communication is accomplished. The results of this exercise are tabu- lated in Table H2. The contents of this table are not claimed to be compre- hensive as to what has to be communicated, nor complete as to how it is communicated. Because of the subjective nature of communication, the entries in the table may very well be controversial. Hcwever, the table does present at least a basis for discussing communication and language require- ments during deployment.

Programming Language Candidates This section discusses some of the major programming languages which are contenders for avionics applications. By discussing structure and capa- bilities, an adequatc.^ technical comparison can be made. Possible extensions of programming language capabilities which are within the state of the art but which are not yet incorporated into the languages discussed here will be covered in the next section.

H21

x

N N TABLE F?, PUSTULATED FUNCTIONS AND BACKGROUNDS OF DEVELOPERS Software Language Deployed System Functions Background Tools Used Level Used Developer Category

_T

• Avionics systems • Manuals from related None or very high

• Avionics system Analyze requirements

• systems

designer Postulate solutions experience

•

• Develop high level models Problem projections • Specify system constraints

O

• • • - level languages High

• System architect / Synthesize specific Technology capability High

• system description)

analyst solution Computer architecture (

experience • High-level simulator

• Performance projection

• Software experience • Analysis packages

• Sensitivity analysis

^a

• Analytic capability • Executive control • Define architecture • Synthesis capability languages • Specify softwa: a/hardware

y

• a Experience with develop- • Language processors High to low

• Program developer Develop module code - program designer- • Integrate code ment language • Optimizers • • - program coder • Optimize code locally Theoretical background Low-level simulators • • Develop verification tests in assigned area (high Debug and verification • Develop diagnostic tests schoolto PhD) tools integration tools • Execution control lartg age • • Develop simulation data • Experience with simu- Code timers High • Performance lators. performance i • Instrumented simulators analyst and statistics • Develop benchmark data instrumentation, statis- I • Hardware instrumen- tation equipment and statistics tical packages • Execution control language

• Special avionics areas • None

• Operator Manual procedure External reference executors • pilot manuals • • other flight crew Simulators (external) • maintenance super- visor No knowledge of internals of system d *tutor+ i *Awakw. w m. n r idpwrrr+ r rto" .400 7000 *00 i 0ow imew TABLE 112, COMMUNICATIONS DURING SOFTWARE DEPLOYMENT How Communicated

By _ T To Whom

What is Communicated Deployment Phase • Existing algebraic languages System feasibility High-level simulation models Avionics system Analysis tools • Simulation language Algebraic system models designers study • Algebraic manipulator Other designers • Block diagrams • Algebraic models • English-language descriptions Problem constraint specifi- Data processing Analysis tools • Algebraic language Detailed system • Simulation language functional design cation system designers • High-level functional specifi- Partial solutions Hardware and software module cation language • Procedural language external specification Data flow descriptions Other designers • English function descriptions Module external character- • System equations istics • High-level function specifi- High-level inter- action system cation language • Irteractive solution refine- ment language • Procedural language Software module Software module implemen- Module • System t programmer designers • Low-level language development tations based on previously defined library of modules • Compiler O • System inte- 1:4odule classfication: grators • algebraic functions • High-level language • decision, display, r Command-oriented, procedural command and control with minimal algebraic capa- bilities • Executive, 1/0, data s Command-oriented, procedural compression and low-level language C~!1 • New functional modules Architecture Unique module hardware Hardware system Logic designers • Logic design diagrams design design designers • Logic design equations •Register transfer language Hardware module inter- Hardware system Hardware system •Block diagrams (2-D inter- connections designers builders active language) • Interconnect language x N W TABLE H2. COMMUNICATIONS DURING SOFTWARE DEPLOYMENT (concluded) x What Is Communicated By To Whom How Communicated Deployment Phase Software implemen- During build tasks: tation and integration • Interaction of functional Data processing • System integra- o High-level interactive system designers tors language (rule and event modules *Interrelation of data • Other designers driven) • Interconnection of pro- cessors • Implementation decision control During verification tasks: • Monitor point control Software verifica- Test monitor and • High-level language (test tion programmers simulator and debug oriented) • Consistency checks • Low-level language (programmable) • Test drivers (programmable • Status display Hardware test • High-level language oriented Data processing Acceptance tests for new Hardware-oriented hardware procure- hardware programmer monitor toward automatic testing ment and inter- • High-level language oriented Diagnostic development for Hardware-oriented Diagnostic- connection toward diagnostics new hardware and inter- programmer oriented compiler • Low-level language connects • GO/NOGO operational tests • Comprehensive fault detec- tion/isolation diagnostics Diagnostics for dynamic recovery System perfor- Monitor point control System designer • Simulators High-level language Statistics gathering control • Test monitors • Event-driven mane evaluation (programmable) • System integra- • Algebraic Data analysis (programmable) tors Data/ result display (pro- grammable) Simulated external environ- ment control Data processing Monitor point control Validation team • Hardware High-level language system validation Statistics gathering monitors modifications • System integra- tors Maintenance and Error isolation procedure Maintenance Test monitor and • Function buttons selection (non-programmable) technician controller • Special language enhancement Programmable diagnostics: • Modify diagnostics • Special language • Add new diagnostics • High-level language oriented toward diagnostics M 3 $. x A brief genealogy of the major general-purpose, high-level languages is shown in Figure H3, The languages within boxes will be discussed in detail.

The number shown below the languages is the year in which the language was introduced. The actual dates may be contested but they do give an indication of relative maturity and timing. Each of the high-level languages will be dis- cussed briefly first.

The Navy's new language (CMS-3) currently under, development for Ad- vanced Avionic/All Application Digital Computer (AADC) and Houston Aero- Space Language (HAL) were no'• considered in this study. CMS-3 is just in the definition stage, and HAL, although implemented for the IBM4n and used on the space shuttle program, has no user history to support claims. Jovial J73 was only included because it is an extension of a lot of experience and effort on Jovial J3 and PL/I. We have tended to be conservative in the lan- guage area due to the following factors: It is arbitrarily easy to define a language, but arbitrarily hard 1) to define a "good" language Benefits of language can be argued, but the proof of goodness 2) is in the use 3) Languages need time to be refined and tested to prove their effectiveness KnutN s study on programming habits showed that simple 4) assignment statements are what is mostly used Many of the newer languages, CMS-3 for example, do not 5) support 4) without a log of external clutter Avionics problems appear constrained and well-defined 6) enough that a language may be selected from the set available today that should be adequate mula TRANslator (FORTRAN) is an algebraic, FORTRAN -- FOR procedure-oriented, scientific, formula-translation language. The language was first developed by IBM for the 704 series of computers and gained rapid recognition. An improved version, FORTRAN IV, was introduced in 1962 and this version has been adopted as the ANSI 1966 standard FORTRAN. Since then, it has become the most widely used general-purpose, algebraic program- ming language. A revision of the 1966 FORTRAN standard is now being pro- cessed by the American National Standards Institute.

The greatest benefit of FORTRAN is its wide acceptance. Because its use is so common, there are many programmers who have a very good working knowledge of the language and programs written in FORTRAN can have a re- latively high degree of transferability. The language has a fair number of H25

v

x

a^ FORTRAN II ALGOL COBOL 1958 961 FORTRAN IV ALGOL 60 COBOL 19 0 NELLAC JOVIAL PL/'I JOVIAL J3 t CMS-1 SPL 197?

r 1969 CMS-2I I JOVIAL J73 1970 1973 CMS:-3 197?

Figure H3, Major Programming Language Genealogy inconsistencies, some of which will be corrected in the new standard. Its greatest short-coming for avionics use is its inability to control for a fine enough granularity, and its lack of controlled fixed-point operations. FOR- TRAN is also weak in the definition and control of data structures.

COBOL -- COmmon Business Oriented Language (COBOL) is a procedural language for business programming applications. It is very English-like and wordy compared to FORTRAN, and is not a convenient lan- guage for programming algebraic computations. COBOL is definitely not a candidate language for programming aircraft avionics computers.

However, COBOL is mentioned because it is one of ANSI standard lan- guages and has influenced the PL/I language. The method and extent of structuring data in COBOL is COBOL's strongest technical advantage for use in avionics.

ALGOL -- ALGOrithmic Language (ALGOL) is an algebraic, pro- cedure-oriented language which has served as a publications reference lan- guage for algebraic algorithms and as an international standard programming language. The language was specified and improved in the late 1950 1 s. ALGOL 58 was the first version which was defined and ALGOL 60 is the final, stan- dard which still holds today.

In the early 1960's, ALGOL was used relatively extensively and many dialects, some of which were for aerospace applications, were developed.

The use of ALGOL seems to be declining because of improved capabilities in other languages and because of a lack of interest by computer manufacturers in supporting the language. Also, ALGOL programs tend to perform less cost-effectively than FORTRAN programs. An updated and radically different version of the language, ALGOL 68, has been defined and is being worked on at universities, but has not received much acceptance as yet.

The greatest advantage of ALGOL was that it was the first language to be very rigorously defined. ALGOL has very powerful and convenient procedure- specifying capabilities. It does not have a standardized I/O specification and it is very deficient in controlling precision and in packing data as r!quired for avionics applications.

NELIAC -- Navy Electronics Laboratory International Algebraic Compiler Language (NELIAC) is an algebraic, procedure-oriented language and is an example of a successful ALGOL 58 dialect developed for a special application area. NELIAC has been used successfully and documented, but has not been widely accepted. NELIAC also is missing important capabilities which other, more modern languages have..

PL/I -- Programming Language/One (PL/I) is a general-purpose, procedure-oriented programming language designed by IBM to replace ALGOL, FORTRAN and COBOL. The language is very large and capable, but its size H27 s^ and complexity has restricted the implementation of compilers to relatively 1 few large-scale computer families. There are many large computers which do not have PL/I compilers.

Many subsets and dialects of PL/I have been defined and used. There do not appear to be any subsets of the language oriented specifically for avionics applications.

Jules' Own Version of the International Algebraic Lan- JOVIAL -- guage ( JOVIAL) is a general-purpose, algebraic, procedure-oriented pro- grax-nming language. It was initially defined as a dialect of the ALGOL lan- guage and consequently contains many of the capabilities and characteristics of ALGOL. There are many dialects of JOVIAL; the two which we are most interested in are JOVIAL J3 and JOVIAL J73.

The JOVIAL J3 language was developed for the Air Force primarily as a command-and-control programming language. It has been adopted as a standard Air Force programming language.

JOVIAL J3 has many of the features required for avionics application programming tasks. It is weak though in the specification and control of data structures, and does not provide for adequate load-time control and linking. The latter characteristics tends to make it expensive to use.

The JOVIAL J73 language has been specified and is being proposed as a standard Air Force programming language. JOVIAL J73 uses 60 characters, as in PL/ I, and contains a modern set of capabilities. The data structure defining and control capability are particularly appropriate for avionics pro- gramming.

JOVIAL J73 is Still in the definition phase; no compilers have been built for it. It is expected, though, that it will be a widely accepted language.

SPL -- Space Programming Language (SPL) is an algebraic, pro- cedure-oriented programming language for developing software for computers used in space applications. SPL is basically derived for JOVIAL and, there- fore, is structurally very similar to JOVIAL.

SPL is a very capable language technically, and satisfies most of the requirements for avionics applications. The acceptance of SPL for space programming application.' has been very limited thus far.

CMS -- Compiler Monitor S1vstem (CMS-1 and CMS-2) computer programming systems used by the Navy primarily for the development of tactical data systems. CMS-2 is the improved and currently used program- ming system. CMS-2 is also the Name of the high-level programming lan- guage used in the CMS-2 programming system. The language is procedure- oriented, and is derived from features contained in the languages ALGOL, FORTRAN and JOVIAL.

H2S ____y__ JL_. _..._ 1 The CMS-2 language has many of the technical characteristics required for avionics applications. One of its unique properties is that even arrays are passed into procedures in a call-by-value mode. A problem with the language is that its acceptance has been restricted to the Navy.

Technical Characteristics Summary -- This section presents some of the key technical characteristics of programming languages and compares some representative languages according to these characteristics. If a pro- gramming language is to be chosen or developed for a particular avionics application or range of applications, these technical characteristics must be evaluated and weighted according to the requirements. These technical characteristics must then be added to other non-technical factors which affect the choice.

The technical characteristics of FORTRAN, JOVIAL J3, PL/I, SPL, CMS-2 and JOVIAL J73 are shown tabulated in Table H3. In addition, one column compares the characteristics of a representative assembly language with macro capabilities. For SPL, the J6 dialect of the language is described.

Most of the languages have many alternates for specific statements; only some of these are included. Also, some languages have capabilities which are not included in the table.

The languages are described in terms of the following four major headings: syntactic characteristics; compiler and loader directives; executable state- ments; and subprogram characteristics.

The syntactic characteristics of a language basically describe the input format and structure of the source code. The lexical properties describe the minute detail of the language: its character set; separators and punctua- tion; identifier formats; source code representation of constants; and literals and formats of comments. The source code structure aspect of the syntactic characteristics describes more the large syntactic units: how programs are formed; whether block structure is used; and how the scope of identifier defi- nitions is defined.

The compiler and loader directives contained in a language describe to the compiler the characteristics of variables and programs and also control the_ execution of the compilation and loading. The directives are only dis- cussed here in a very general sense since they are very dependent on the compiler and loader implementations.

Declarations are, a specific form of directive to the compiler. Declara- tions basically describe to the compiler the properties of the variables and data structures which are used in the generated object code and the execution properties of the code itself when these properties cannot be deduced by the compiler. Of specific interest are the various methods of declaring variables and the specific data types which are handled by the languages. The relative capability the language has for making data structure declarations is also important in avionics applications.

H29 '_ _,_____._ TABLE H3. TECHNICAL CHARACTERISTICS OF HOLs aIJ ( rI ( Representauyr i.anguage PORT RAN ^IOVIAL J3 FL/I ( SFL 0115-2 JOVIAL .173 Assemhl} I l'rchnical Lang—ce I C 'b:u :rctr rist^rs Syntat • tir charmcteristics of ^0 - Lexical properties ' V Ma 60 48 48 60 48 • Character set 48 48 Continuous line; Continuous line; Continuous line; Continuous line; Fixed field: one instruc- • Input format 72 column cards, Continuous line: free field, blanks free field; blanks free field; blanks free field; blanks free field; blanks Lion per line continuation cards, free field, blanks are separators are separators are separators are separators are separators ignored • Reserved words No Yes No No No Yes Yes • Separators. Blanks are not Blanks are separa- Blanks are separa- Blanks are separa- Blanks are separa - Blanks are separa- Blanks are separators )wnctuation separators tors; "$" for state- tors; for state- tors; no statement tors; "$" for state- tors; is state-

H

ment separation ment separation separators ment separation ment separation • identifiers (first 1-6 alphanumeric I character, names 1 and up alpha- 1 and up alpha- I and up alpha- 1 character names .Same as FORTRAN character is alpha- reserved; 2 and up numerics with numeric numeric reserved; 2 and up alphanumerics with bet ic) alphanumerics with underscore (-) for prime ( ) for separ- separation ($) or (') for sepa- ration ation • C'Mmtunts and literals Numeric • Integer Decimal number Decimal, octal, hex- Decimal, binary Decimal. binary, Decimal string Decimal string, bit Decimal. ortal string pattern status string; character adecimal number string octal, hexadecimal constant string string • Fixed point - Decimal with point. Decimal with point. Decimal with point. Decimal with point. Decimal with point. Not provided Not provided scale exponent exponent exponent exponent • Floating point Decimal with point. Same as fixed Same as fixed Same as fixed Same as fixed Same as fixed Same as FORTRAN exoorient • Logical Integers 0,1 Integers 0,1 Boolean .TRUE.,.FALSI-. 1.0 '1'13. '0'13 'TRI'E'. 'FALSE' 1.0 or 'ON' , ' OFF' Symbols defined as Symbol equivalency - Status Not provided Symbols defined as Not provided S•vmpols defined as Symbols defined as V(RAINY), RAINY'. V(RAINY).

'RAINY' V(C'LOVDY ), 'CLOUDY' , 'CLOUDY', V(CLOUDY), V(SII NNY) 'SUNNY' 'SUNNY' V(SUNNY); treated as integers +Literal strings Hollerith strings Hollerith strings Single or repeated Strings allowed Called Hollerith Called character Character constant constants constant - Character CIISTRING- GIRSTRING) 'STRING' Strings allowed 'STRING' IBSTRING) Restricted use, or transmission STRING' or machine-dependent strings 6T(STRING) (1)'STRING' code.

- Hit Not provider! Bit pattern, octal Binary hit string Binary octal or Not provided Bitpattern Octal, hexadecimal or hexadecimal B 111111'13 111111 113'111111' constant constant 313'7 i O' 77 0(771 S' 31' 1413'3 F' • '4stffim2,^9eaae^r S^S^£nsa.a•.w^S^gnw_::m^ ^u - ,an.,.,....»....:e.:^...b,,.....A.^,.o._.: _.^.: V, TABLE H3. TECHNICAL CHARACTERISTICS OF HOLs (CONTINUED) Language Representative Technica FORTRAN JOVIAL J3 PL/I SPL CMS-2 .fOVIA I. .f73 Assembh Language C'ha racteristics • Comments Separate lines with Quoted strings; legal Bracketed string Quoted strin gs; Quoted string where Quoted strings where Asterick in Column 1 " 'c fn column I where blanks are where blank is COMMENT blank is legal: blank is legal; legal "COMMENT" lega COMMENT state- SOME COMMENT", MMENT'/ ment semicolon termi- nates comment - Source .rode structure • Code division Division not en- Recommended but Division not Data declarations Data designs and Natural division: None enforced forced. Recommen- not enforced: data enforced hefore use procedures; data procedure declara- tions; data declara- ded - data declara- declarations before defined before procedures Lions; statements tions before execu- use.

table statement.

Each subroutine, o c) function compiled O separately.

Very extensive as None • Block structure None below sub- Extensive for pro- Very extensive; Extensive for pro- None below pro- cedure level in PL/I routine levels; sub- cedures; limited for used primarily for cedures; limited control of scope of for data.

routines, functions data.

treated as code identifier defini- blocks. - tions.

• Static scope Data declarations 3 absolute scopes: Data and procedure Statement labels System declara- 4 absolute scopes: COMPOOL, exter- hold for entire sub- COMPOOL is global declarations hold have program as tions hold for pro- nal. main, proce- routine, function or scope; main, and for inner blocks; scope; data names cedure scopes.

have local and block dure declarations main program procedure. external scope for structured scopes. hold for inner blocks; addrese linking.

scope further speci- fied by block structure ^ Compiler and loader directives - Directives Macro prepro- Macro string sub- Macro string sub- Macro string sub- Macro instruction: • High level Data structure Macro string sub- stitution; data cessor with stitution: low-level stitution; compile stitution; data struc- sequence substitution equivalence;. no ture OVERLAYing; listing control; structure OVER- ex#ensive compile code insertion; time variables.

- level code LAYing: low - level time capability; concurrent process- conditional compil- no low ation; optimization insertion: not ex- code with DIRECT; concurrent pro- ing control.

directives; low-level tensible.. COMPOOL and cessing control.

code with DIRECT.

procedure library calls.

Not provided External defini- No provided External defini- Extensive external Control sections similar • Loader directives Implicit in definitions and refer- to COMMON. external COMMON state- lions tions and refer- ences for linking references for linking ment; EXTERNAL ences for linking loader loader.

subprogram refer- loader ences.

x

W

x

W

N

TABLE H3. TECHNICAL CHARACTERISTICS OF HOLs (CONTINUED) language Representative Technical FORTRAN JOVIAL J3 PL/I SPL CMS - 2 JOVIAL J73 Assem blc Chu rarterislic Language • Compile time None None Integer. claracter Declared variables Identifiers defined No. but has compile Yes: can be used in variables string ( in prepro- can he made con- by EQUALS direc- time formulas assembly time express - . cessor); can be starts live icns used in compile time evaluations • Load. time COMMON groups None Externalized None System procedures, Externalized (DEF) Externalized address variables EXTERNAL sub- address variables EXTERNAL defini- variables and names variables routine names tions - (ENTRY names) - Declarations • Program structure SUBROUTINE ... PROGRAM..-START PROCEDURE_... STAR ' r... TERM System, system COMPOOL declara- PROGRAM declarations END; FUNCTION ... ... ' PERM $ END P ROC. .. EXIT data, design. sys- tions: program END END; PROGRAM ...

PROC... BEGIN... Data declarations CLOSE... EXIT tem procedure, declarations; pro- Entry definitions END data declara- END $ should be defined Variables must be local data design, cedures can be Lion and executable CLOSE... BEGIN...

before being used. declared before used. procedure, and defined within pro- statements may be END $ function declara- cedures.

intermingled. Variable names must tions are allowed.

be declared before Example: they are used. SYSTEM... END- SYSTEM • Variable declara- tions methods i - Implicit Yes; first letter in MODE directive Similar to FOR- Same as JOVIAL J3 MODE directive None None identifier deter- specifies default TRAN; partially specifies default -;. .. or fries type; F. J. K. declaration mode declared variables declaration mode L, M are integer. have default values set to remaining attributes - C'ontextual. Integer labels ( in Labels; loop Labels; loop Labels and contex- Labels Statement names; Labels columns 1 to 5) variables variables tual items loop variables - Explicit -INTEGER, REAL In item declarations In variable decla- In variable declara- In variable decla- In variable decla- Symbol definitions etc.. type decla- ( I=interger, A= rations ( FIXED. tions ( FIXED. rations (I, A, F. rations ( U=unsigned rations. fixed. F=floating) FLOATING, etc.) FLOATING, INTF.- and B = Boolean • fixed and integer, GER) Ii=Hollerith. S = Srsignal fixed and status) inieger. F=floating• C=character) - Multi-variable Many vnriahles per One variable per Many variables per bike in PL/I Many variables per Many variables per One declaration per declaration attribute; one attri- statement; all attri- statcm^ . nL' all attri- statement; all have statement; all have line formats bute per statement. butes in statement; bates in statement; same attributes. same attributes_ no factoring, factoring allowed: i arv._5nanb.Yr_r^ "^uLRN443i2Ai>`J- "^Y.KNFAUaroM^ca^Y .k:WJ¢ati.r:.prs"Mtakpxswer,anf^+^ua —.... _.^,^.^._._^.

Language Representative FORTRAN .JOVIAL J3 PL^I SPL CMS-2 Technical JOVIAL J73 Assemhlc Characteristics Language • Simple variable a declarations - Data types allowed e Integer X X Use fixed X X X Only addresses are used; programmer must X Fixed X X X X • point - associate address with X X X X data type held in addressed • Floating point X X location X - X X X Equivalent • Logical. X (Boolean) • Status X No X X X Na • Complex X No -' X _ No No

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Equivalent Equivalent Equivalent Equivalent Equivalent • Double X precision - • Label No No X - No No No X - X No No • Vector No No X No No • Matrix No No 1--1 • Alphanumeric Yes - machine X X X X Character dependent - Equivalent - integers, No Equivalent X X Equivalent tattles •alit strings tables No No X • Pointer No No X Yes Yes, (DATA state- Yes, in declaration Yes, INITIAL Yes, with PRESET Yes. in declara- Yes. but restricted - Presetting of to class of variables; ment) attribute attribute tion or DATA variables - statement similar to 17ORTRAN - Allocation modes Default Default Default Default Default *At load time All variables Default allocated required space z Variables with For local variables No. variables are Can be controlled No • At procedure No Yes AUTOMATIC in recursive and permanent until with environmental entry - specifier attributes re-entrant proce- explic;ily changed dures Not controlled Similar to FORTRAN Controlled Not controlled Not controlled Controlled: perma- • Permanence Variables are per- pence can be keyed manent until. expli- to outer level pro- citly changed cedures: default is similar to FORTRAN

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W W x w TABLE H3. TECHNICAL CHARACTERISTICS OF HOLs (CONTINUED) Representati Language FORTRAN JOVIAL J3 PL/1 SPI. C'MS•2 .IOCIA I. ,i 73 Assembly Trclunc-d C h. v:cctcri sties T zr)guage • Data strur lure "— dcrlarations - Arrays • Maximum 3 Any number Any number Any number 3 (special table Any number 1 dimensions type) • Subscript Restricted: Integer'' Any integer valued Any expression; Any expression; Any expression, Ised in address expression expressions Constant + Constant expression converted to inte- converted to inte- converted to inte- ger ger ger Provided but fixed Can he passed into Controlled through No • Adjustable Can be passed into Not provided subroutine as argu- at allocation time subroutine as argu- allocation incre- dimension ments meats ments - Tables Not provided Not provided Not provided Any dimension plus • Organization Provided Provided 3 dimensions plus fields, words Vertical (serial) Serial and Tight • Cot.t roi. (serial Serial or parallel Serial and parallel and horizontal or parallel) (parallel) NONE, MEDIUM, Same as JOVIAL • Packing options No packing, dense, Same as JOVIAL J3 DENSE J3; medium is sys- medium tem dependent Static or automatic Static Flexible allocation • Allocation Static increments cont rol Not provided Very flexible; Less flexible than Tables, fields, Compound structures Not provided - hierarchical. Not provided structures variables, arrays PL/I. words provided; referencing may be elements less flexible than PL/I Arbitrary depth SCR-TABLES Flexible overlay •Structure Variables and arrays with allow overlays control of tables equivalencing and items EQUIVALENCE Arrays allocated Structures allo- Default., Allocated Structures alloca- Structures alloca- Structures allocated Not provided - .Allocation. con- i nt compile and cited at compile at compile and load ted at compile and ted at compile according to perma- trol for strue- tures load time time time; AUTOMATIC load time and load time nonce level of name; structures alloca- very flexible control.

ted at procedure entry; programmer ha: -control.

Switch statement Label vectors Switch declaration; Label switches; SWITC11 statement Indexed jump • Switch declarations Assigned G provides a more more convenient procedure switches; provides a little instructions t convenient label than FORTRAN very flexible. more flexibility switch than than FORTRAN.- computed GOTO FORTRAN y TABLE H3. TECHNICAL CHARACTERISTICS OF HOLs (CONTINUED) Language- •. Representative Technical FORTRAN JOVIAL S3 PL/1 SPL CMS-2 JOVIAL .J73 Assembly Characteristics Language • Executable statements - - Computational expressions • Arithmetic (scalar) - Operators +- Similar to Similar to Similar to Unique machine v/ absolute Similar to Similar to FORTRAN FORTRAN FORTRAN FORTRAN FORTRAN instructions must remainder be coded - Mixed Not allowed Allowed Allowed Allowed Allowed Allowed expressions.

- Scaling Not provided Automatic conver- Automatic conver- Automatic or con- Automatic or con- Automatic and con- sion to floating sion to floating trolled scaling trolled scaling trolled scaling: very point point flexible evaluation control Not provided Not provided • Arithmetic. Not provided Not rovided imple element- Vector at _y. matrix (array) opera- by-element operations pro- operations pro- vided tions vided LT, GT, LTEQ, • Relational . LT., . LE., . EQ.. Complete set Complete set Complete set Complete set GTEQ. EQ, NOT operations GE., .GT.

(= complete set). equal AND, OR, NOT AND, OR, NOT. AND, OR, AND, OR, EQV, XOR, • Boolean AND. , AR. ,.. NOT., AND, OR, NOT EQUIV COMplement N01' operations Not provided C) Boolean bit vector Boolean bit vector Bit and CHARaeter Concatenation • String Not provided Bit and byte extrac- tion operations are operating co--.ca- operations bit and extraction operation provided tenation; bit and byte extraction left and right shift byte extraction Infix Infix Infix ' I nfix Infix Infix with evaluation • Format control Normal precedence • Execution Normal precedence; Normal precedence; Normal precedence: Normal precedence strict left to right rules left to right; reord- strict left to right e ring allowed t

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- Environment +I!

altering - statemLnts - Variable = Variable = SET variable TO Variable = Unique machine • Assignment Variable = Variable = expression expression expression formula instructions must be statements expression expression coded Conversion auto- Conversion auto- Conversion auto- Conversion auto- Conversion auto- - Simple Conversion auto- matic matic matic or controlled matic or controlled variables matic matic Arrays. hier- Arrays Not provided Not provided - Structured Not provided Not provided archical struc- variables tures Allowed Multi-word Multi-variable.

Not provided Not provided Allowed - Multi- assignments multi-formula variable Not provided Scalars and arrays SWAP... AND... Scalars only - Not provided Scalars only Exchange statement M C.0 Cn x W TABLE 113. TECHNICAL CHARACTERISTICS OF HOLs (CONTINUED) Representall- Language Assemble PI1l1 FP I. I CMS-2 ,IO\"IAL .173 "Technical FORTRAN I .)OVIAL .J3 I.anculge C'ha ractc ris[ics • Control state- ments GOTO label, close COTO label COTO statement, sump instructions - Unconditional GOTOlabel COTO label, close COTO label name label jump name, program name COTO switch index SNITCH statement In s exed lumps Computed COTO Index switch list Label array Index switch array - Selective or switch.-list jump .lump to register COTO switch Not provided Not provided Assigned COTO COTO switch COTO label - .Jump to label specified address variable (index) or switch variable variable To labels within To local or outer Anywhere in program To labels within sub To local or outer To local or outer Anywhere in the - Scope of scope scope scope program program or pro- jumps routine program cedures Basic IF:.

• Conditional state- Arithmetic IF: Basic IF: ment IF le THEN ss $ IF le ; cs Conditional lump IF Is $ s $ IF le THEN s ; IF le ss - ae = arithmetic IF(ae) Lt, L2, L3; instructions expression IF DATA FOUND IF le ; cs ELSE s Alternative IF: IF le THEN s IF le THEN s - le = logical Logical IF: ELSE s END; THEN ss $ ELSE s ; 'rxp rosion = label IF (19) ss IFEITH le $ s$ - L Alternative IF: Validity decision: ORIF le $ s$ IF le THEN s IF table VALID - s = statement ...

THEN ss $ ORIF le THEN s ORIF le $ s$ - ss = simple statement ORIF le THEN s - cs = compound ELSE S END statement - a Looping control statements WHILE le VARY v FROM FOR v (WHILE le) Conditional jump - Basic control DO L v = L 1, incr FOR v=L 1. incr$ DO WHILE le: DO - TO I. BY UNTIL le f THRU I FOR v (ae BY ae instructions clause/state- UNTIL v=ae) finer FOR v=f BY BY incr < ment incr UNTIL 1 v = variable I = first value I > last value incr = increment END statement First statement 1._ ement with First statement END statement END statement - Termination after FOR is label L after FOR is repeated; can be repeated; can be compound - compound No restriction Any level via Any level: END's t Any level: END's Any level; END's Any level - Nesting Any level compound match control match control match control statements No rest rit-tion - Parallel loop With added FOR Not provided Provided with ALSO; Provided with AND With added FOR Not provided extension to VARY statements statements FOR a = variables ALSO eb = ... statement END TABLE H3. 'TECHNICAL CHARACTERISTICS OF HOLs (CONCLUDED) Language I. Representative Technical FORTRAN JOVIAL J3 PL/I SPL .. I CMS-2 JOVIAL J73 Assembly Characteristics Language Subprogram characteristics - Macros Statement function; Not provided Provided through Not provided but Provided through Provided through Provided with macro restricted use - preprocessor closed statements EQUALS and MEANS "DEFINE" substi- definition capability (open subprogram) are nearly equiva- substitution scheme tution scheme lent Closed subprograms - • Restricted scope Statement function Closed statement; Procedures can be Closed statement; Not provided Same as PL / I Not provided is equivalent no parameters; used in context of same as J OVIAL block structure J3.

only usable in program where it such that their is defined. scope is restricted to a limited number of blocks in a pro- gram Procedures and Independently assembled • Independent scope Subroutines and Procedures Procedures Procedures Procedures FUNCTIONS functions subroutine Name No restriction - CalIing format CALL name Name CALL name Name Name INPUT i.... (il.....

(ri.... rn) viy =vl... in: vl..... vn) (ri.... rn) Vni. ... im =vl •.:.. im-vI.

UT^ )1 EXIT °1 Name USING index INVALID statement INPUT it... OUTPUT d r,...$ Simple of tr y Simple entry only Can be declared Can be declared Recursive capability Can be declared No restriction - Entry mode ctJ only as _-_ :-sive as recursive not specified as recursive Arbitrary - Parameter Call by reference Call by value is Call by reference CAI by value is Call by value only; Call by value is b call by reference normal mode; call passing normal mode; call normal mode; call by reference for can be achieved by reference for by reference for arrays. but with inconven- arrays.

arrays.

ience.

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Names defined in Local to entire All names are .Names defined in INTERNAL names LOCAL names have Local names are - Local variable restricted scope restricted to pro- procedure are assembly scope local to the sub- procedures are are local cedure in which local program in which local they are defined they are defined COMPOOL vari- Not explicitly Main program vari- Variables from Same as JOVIAL COMPOOL and sys- - Global variable Variables in provided ables available to outer blocks are J3 tem data designs ables available to Use COMMON are are globally defined; all procedures; globally available subprograms. accessible to inner external variables outer scope vart- in subprograms COMPOOL variables block procedure.

are accessible to in- ables available to w ;ere C 1 3MMON available to all. EXTERNAL vari- 1 + le dep^rdently com- inner scope.

name is dofined ables are accessil to all procedures piled procedures.

where the variable is declared exter- nal.

Permanently Very flexible allo- Permanently Permanently Automatic alloca- Permanently - Memory allocation Permanently allocated allocated at load cation control allocated allocated allocated tion on entry and time with "permanence" permanent allo- cation optional for attribute procedures; con- . trolled allocation available.

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W Executable statements handled by the languages are presented in terms of their capabilities for evaluating computational expressions, and in terms of the statements altering the environment. The latter category is further subdivided in terms of assignment statements which change values held in variables, in terms of control statements which determine the execution sequencing, in terms of conditional statements whose execution is data de- pendent, and in terms of looping control statements which control the repe- titious execution of code segments. The control statements, conditional statements and looping-control statements are environment-altering state- ments in that they control the program execution pointer, one of the state variables in an executing program.

One important class of executable statements has been omitted; the input and output statements. In avionic systems these are very system dependent and would be the most likely functions to be programmed in a low-level language. Also, most of the input/output statements in high-level languages are oriented toward character handling I/O peripherals. This type of I/O has little use in operational avionic systems.

The subprogram characteristics of a programming language were made a separate category because of the importance of modularity in avionics applications. All of the described languages have good subprogram definition and call capabilities. The main differences are in the parameter passing modes and in the treatment of the use of local and global variables.

HOLs versus Assembly Languages -- The main advantage of assembly languages is the fact that the programmer may access the details of the machine's structure and, thus, may write codes slightly more efficient than those generated by a compiler. However, assembly language program- ming tends to be less structural, less understandable, more machine- dependent, and less communicative of programmer intent, etc. , than a high- order language.

Probably the best approach now available is to code the programs in an HOL (avoiding as much as possible any assembly-language coding), com- pile the code, and test it. If the compiled code does not run as fast or takes more space than desired, alter the HOL source to tune it up. If necessary, the programmer may have to go into the assembly language on some routines but this should be kept to a minimum.

The disadvantages of assembly language compared to the advantages of HOLs cause us to feel that, with the nominal loss of efficiency attributable to modern compilation, assembly-language coding should be avoided as much as possible.

H38 I New Concepts in Higher-Order Languages The preceding sections have discussed the current state of the various languages applicable to avionic applications. However, the problems en- countered in developing and implementing avionic systems are not unlike those found in the more general software areas. Accordingly, we now will address some more global issues concerning the relationship of HOLs to the general software dilemma. In the following sections we address some of the more controversial and recent concepts.

Data/Program Structure Relationships -- A higher-order language definition implies a set of conceptual construe-ions to by used in designing and programming an avionic software system. These constructions form the basis for the data objects and the program code for manipulating these data objects. The role of an HOL in designing and implementing avionics systems is much like that of a mathematical notation in solving analytic problems. This point is illustrated by the notation introduced by I-verson, which has become a popular and powerful interactive language called APL.

In this case, the organization aspects of APL, along with the availability of operators to deal into the complex data structures, make APL a powerful language for mathematical problems.

In the avionics environment, the construction of software programs involves basic operations and structures. An HOL which facilitates the representation of specialized constructs within avionics systems is an im- portant tool. Additional benefits of such an HOL would be realized in the areas of modularity and program validity, as discussed above. Finally, another advantage of such an HOL would be that it would provide a conceptual basis for thinking about, designing, and implementing the system. The im- portance of the tool in this respect is relatively new and controversial (Ref. HQ.

The concepts of an HOL have been used in most commercial systems, both in the construction of user programs and in the operating system. An example of an operating system in an HOL is the MULTICS system (Ref. H5).

Such systems based on an HOL are designed using data structures as provided by the host HOL. The disadvantage now of°this approach is its inefficiency.

The machine code produced by translation or emul^.%,tion from an HOL is sel- dom optimal. However, the advantage of easier management and control of large systems provided by an HOL will offer a necessary future compromise.

Extendable Languages An HOL which is extendable provides the capability for incorporating specialized primitives in a natural way into the HOL. An HOL is not extendable by virtue of its modular°ization. The key concept of extending an HOL is an ability to modify or specialize existing primitives and features, to serve a specific purpose. For example, ALGOL or PL/I can be extended in system-provided procedures because any pro- cedure can be redefined globally to arbitrary blocks of code.

H39

A specific system usually evolves from certain basic primitive functions.

The role of an HOL in providing several such basic primitives was discussed above. However, a general-purpose HOL cannot effectively provide all things to all applications. By providing for extendability, an HOL allows those primitives specific to an application to be incorporated as necessary.

Accordingly, application can be developed with all of the advantages of a complete consist,:mt HOL. The orientation of the HOL to the application resulting from its extension provides for a convenient framework of work assignments during the implementation of the avionics system.

An HOL designed for individual application is often not suitable for other uses. Such an HOL contains a set of primitives which lend themselves very well to the intended use. These primitives are formulated and described in a notation natural for the application. Thus, using this HOL for a differing application is difficult. Accordingly, different languages with different standards have come into existence. Many differing HOLs have thus been specialized for individual applications, resulting in a suitable HOL for each area.

In the avionics environment, the range of applications is far less diverse than the general commercial field. However, differing thrusts within the avionics environment will require an HOL adaptable to differing orientations.

The extensibility of an HOL can be an advantage, ^-ihile the HOL itself remains to provide a system standard. This is accomplished by basing the system on constructions inherent in the HOL and ensuring that specialized applications are proper extensions from this base.

Source Level Modularity -- This section explores the concept of source-level modularity as it relates to HOLs. Source-level modularity implies that the modularity requirement need not be carried to the object or machine level. The deployed system will not require the degree of modularity that would exist with all required modularity within the deployed object system.

The advantage of an HOL is that the potential organizational and management considerations of modularity need not exist within the deployed system. The disadvantages are increased costs for system generation, and a technique which is displeasing to a machine-oriented programmer. Three aspects of source level modularity make it an attractive approach to such high-require- ment applications as avionics: the ability fir system integration in source before compilation; the possibilities for conditional inclusion of source; and the possibilities for optimization based on source-level aids.

In the previous sections, the notion of a total :system description was compared with '6he data and program structures of an HOL. There, the advantage of an HOL was in its ability to form a basis for the total structure of the system. To a lesser degree, organization based on an HOL consisting of modules can be designed and implemented at the source level. This is wbat happens, for example, during the compilation and loading (linking) H4 0

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phases of FORTRAN-object program generation. However, the load-link philosophy implies that the modularity at the source level will be retained at the object level as well.

The notion of a program construction consists of creating subsystems by combining smaller modules. In the process of constructing a subsystem, the individuality of the combine; modules may be lost. This results in a more efficient or compact subsystem. Because the basis for the design of a system is a source-level modularity, the blending of modules into a homo- geneous object package does not lessen the original advantage. An additional advantage is that the homogeneous object package can be optimized as desired.

Conditional compilation is a feature within the source level of a language which exists in contemporary assembly languages. It allows including source characters, conditional on certain flags or relationships, in the source at compile time. The advantage is that source characters may be placed into a program and removed by simply altering a conditional variable. In applica-

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tions involving changing configurations, the differing software configurations can be established by simply specifying the appropriate constants. Debugging constructions can be included in the source in the form of tracing tools and software redundancy. Once a program has been satisfactorily debugged, these constructions can be removed via the conditional exclusion of source characters.

The third aspect of source-level modularity within an HOL is that of optimization. At the source level, module behavior, interfaces, and data dependencies are more readily available. With this type of information, the problem of meaningful optimization is more easily dealt with. Information can be exploited to perform the optimization processes and then dropped during the translation of the source program to object code. The advantage of source-level modularity here is that the resulting object code is free from redundancy and information constructions which apply only to program con- struction.

Source-level modularity implies that the construction of the object sys- tem is automated via the HOL compilation. This fact implies that all manipu- lation of the system code by a programmer must occur within the framework of the source code. in the avionics environment, this will represent a signi- ficant change in practice. However, we should emphasize that the primary function of a good HOL as discussed here is to provide a structural basis for the system. Within the structural basis, individual modules can be designed and implemented. Program generation will produce an object code. With sufficient debugging constructions, errors in object behavior can be related to the appropriate source constructions and the repairs made at the source level.

H41 Structured programming increases Structured. Programming -- program reliability. As described by Liskov (Ref. 3), structured program- ming is characterized by two rules. The first is that structured programs are developed from the top down, in levels. Each level is a collection of components or subsystems. The components of a level are themselves structured programs, which consist of components at yet a lower level.

The decomposition of components ultimately leads to the basic primitives of the language used. A second rule of structured programs dictates the way in which components can be combined into control structures. Only the following control structures are permitted: concatenation; selection of the next statement based on the testing of a condition; and iteration. The significant structure not allowed is a transfer of control via the goto state- ment.

Structured programming limits program control structures to those which lend themselves to proofs of correctness. The process of proving correctness consists of examining each level of the program and asserting that the level meets its specifications, if the components from lower levels do. This form of inductive reasoning down the levels of the program even- tually leads to components which are basic primitives of the implementation language. These primitives meet specifications to the extent that the imple- mentation language does what it is supposed to do.

The proof process depends in two ways on the control structures allowed in structured programming. First, the allowable structures ensure that con- trol enters and leaves an individual structure in a unique fashion. Only a single entry and exit is permitted. Control always leaves one structure and "falls into" the next. This limits the reasoning to the flow of control as it pertains to the component being analyzed. The second dependency is that each of the three control structures is associated with a well-known rule of inference. Concatenation is associated with linear reasoning, iteration is associated with induction, and conditional selection is associated with analysis- by-cases. These rules allow each of the components of the system to be easily understood.

The discussion to this point has examined structured programming as it facilitates analytic proofs of program correctness. Because of the restric- tions imposed by the three allowed control structures, certain application programs may be much less than optimally implemented. It would seem that a compromise situation exists. A system designed with structured program- ming (hence attempting to minimize control structures not one of the above three), would have greater reliability. This requires that designers and programmers accept the above discipline.

H42 i SOFTWARE VERIFICATION AND VALIDATION There are three main steps in testing software: 1) Selecting test cases 2) Evaluating their execution results 3) Estimating correctness (inductive leap correctness assuming test cases were good choices and executed properly).

While this testing process is well known, the complexity and inexactness of software precludes a good validation procedure. Such new techniques as program provers are not yet feasible since they are only applicable to very small programs and are impractical. The only practical way now to have confidence in the test cases is proper construction. This means modularly structured programming with interfaces. However, the current state of the art is such that no established procedures exist for ensuring that system developments result in well-built systems. Nevertheless, it is reasonable to assume that such current research areas as structured pro ramming and modularity analysis will produce the needed procedures.

BOTTOM-UP CONSIDERATIONS Introduction An alternative way to solve portions of the software dillemma is to provide hardware support to various software functions, This approach has some advantages: • May enforce clean interfaces • Enforces standards • Provides a faster execution Provides a lower level of detail to software • There are a number of disadvantages to this approach: Loss of flexibility • Implementation difficulty in implementing special functions • Increased size, weight, power, gates, etc.

• H4.3 Some of the areas in which hardware may be used to support software are described below.

Hardware/ Software Interface Primitives One of the key software areas that can be implemented in hardware or assisted by hardware is that of executive functions (Ref. H6).

Typical functions that one might support are described below. These functions have been taken from Reference H6, and range from I/O support to memory hierarchy support.

Basically, any multiprocessor or multicomputer system can benefit from hardware supporting executive functions. Typically, the most common and useful piece of hardware is the associative memory (AM) or its deriva- tions. The AM can provide several orders of magnitude speed-up in several functions, thereby making a significant impact on system throughput. Asso- ciative logic is regular, thereby providing a high-density, powerful system.

The time taken to search tables and lists, and the required indexing and link manipulation hardware and software are not required when a search memory is available. This cuts down overall system complexity, overhead, and execution time. The executive programming cost is also reduced and the programmer does not have to worry about the impact of the selected data structure on his program's execution speed.

Hardware associative memory aids can be applied to executive functions in the following areas: • Virtual memory - - Translation tables, replacement algorithm hardware (see paper by D. Jensen, COMPCON 72), etc.

• Interrupt processing -- Priority interrupts, processing of interrupts of same level of priority (see paper by D. Jensen, 1970 FJCC), etc.

• Resource allocation -- Determination of available resources, determination of resources in test (see paper by D.C. Gunderson, WESCON 1966), etc.

• Scheduling -- Determination of next job, assist to deadline (variable priority) scheduling (see paper by Berg and Thurber, NEC 1972, Thurber and Jack, COMPCON 73) etc.

• Monitoring -- General statistic collection, high-speed resource monitoring, etc.

• Tables -- Any functions which require multikeyed searches over lists of parameters, status, or capability can be easily supported.

H44 • Mappings/other arbitrary functions Any functions which require a dynamic translation mapping, a logical or physical binding, or a translation of any sort can be readily supported.

• Relocation -- Functions which deal with the difference between a logical and physical location, such as relocating a program, can be supported.

Memory map - - Even if a virtual memory is not used, memory maps must be kept. Easy access to I/O buffer location and usage, entry points to code blocks, allocation and deallocation of memory space, etc. , information is readily provided.

• Protection -- Dynamic protection schemes.

Sharin -- Sharing of files and data.

• • 1/0 -- Chained 1/0 can be simplified and new requests can con- ceivably be chained to existing lists without a large real-time penalty, since a list would not have to be searched to insert into the middle of an I/O chain.

• Semaphores -- Semaphores can be supported as a two-way index; i. e. , one operation can clear the semaphore list of all processes waiting on that single event, additionally, the correct fields of processes waiting on multiple events can be easily cleared.

• Time Outs -- Time-out manipulation is relatively easy so that one can afford to use a fast clock routine and keep close track of time to run, etc.

• Reentrant code Data pointers are easy to construct and maintain.

The advantage of irrnplementing these functions in hardware is that they provide an, efficient interface between the hardware and applications software.

Also, the software functions which were replaced can be thoroughly checked out, as can the reliability of the associated hardware block.

The other main area of inquiry is the 1/0. Since 1/0 is very well defined, its functions may be put into hardware, thus giving the attendant, advantages of fast execution and reliability.

Architectural Functions There are a number of functions that could be implemented in hardware which would support the system functions and ease system implemen- tation. A detailed list of these functions was constructed (Ref. 116). These functions are described as follows: H45 , o Enqueue/dequeue: These would be useful, particularly for an operating system built around conventional system balance concepts in past operating systems.

• Procedure call.: (Stack or equivalent) Would be useful for re- entrant and recursive procedures, especially if the program- ming language is CMS-2 or PL-1.

• Wait for: (a or b, a and b) Allows tasks to synchronize their activities.

• Hardware protection: For example, the MULTICS software gatekeeper can cost milliseconds to permit ring boundary traversal.

Tag interpretation: Evaluate tags in context of operation, for

•

example, an operand may be the name of a process or a pointer to the actual operand (e, g. , B5000 EVAL operator, R-2 machine), • Test and set: To allow multiple processors and/or processes to use a common code together (READ LOCK instruction in B6500, test and set in UNIVAC 1108).

• Dynamic linking: Static link resolution prior to allocation and execution of a program is a big OS task. Hardware support for dynamic linking (e, g., MULTICS) would be advantageous.

• Process creation: This primitive is fundamental and should have a very clean interface to the rest of the OS.

• Load and unload primitives: There must be mechanisms for loading (portions of) a program into a PE and for transferring new data from TM into RAMM; these mechanisms can be viewed as primi- tives. It would then be possible for the executive to send a LOAD instruction to a PE, which would cause the loading of a kernel page.

(This implies that the processor is in a "ready to receive" state when it is not executing. ) Similarly, an UNLOAD instruction could be executed by the PE to transfer data from TM to RAMM.

• Wakeup and block: The ffirst changes the execution state of a pro- cess to logically ready, t ine latter to logically block.

o Request and release: Primitives suggested by Weiderman for resource synchronization.

The main use of these functions is to implement cormunication schemes in multiple-processing element systems. 1Vore detailed descriptions of some of the communication functions typically implemented in current sys- tems are given below.

H46 The Concept of Semaphore -- Semaphores allow processes to synchronize themselves. Basically, semaphores allow processes to act relatively inde- pendently of their environment. The primitives used by Dijkstra are P(sem) and V ( sem), where sem is a system semaphore. Sem consists of a variable and a list. Sem may be a binary variable ( 0 or 1) or, more generally, an integer variable. Assume sem is an integer variable. Then, the synchroni- zation primitives appear as given below: -P(sem): Decrement by 1, sem. Then if sem < 0 put the process on the blocked process list for sem. -

+V(sem): Increment by 1, sern. If sem 3 0 remove a process

from the blocked process list.

One notes that a semaphore must be accessed by only one process at a time; if two operations are invoked on a semaphore, they are executed in an undetermined order so that they should be logically indistinguishable and the semaphore operation must be completed before it can be interrupted.

Processes are potentially blocked on a P ( 5e ) operation and reactiVated only when a V(sem) operation occurs. V sem) removes some form of road- ( ^ block, which allows a process to continue its execution on same, programmer specified condition.

•I IBM OS/360 Primitives -- IBM provides four basic macroin,- - truction syn- chronization primitives: ENQ; DEG; WAIT; and POST. ENQ and DEQ are analogs of P and V, while WAIT and POST are analogs of block and wakeup instructions, ( See Lampson, 1969 FJCC. ) d, ENQ(DEQ) operates on an eight-character parameter string (alphanu- meric) called a resource. Each resource has a list of ENQed objects which represents both blocked processes waiting to use the resource and processes which are using the resource. A process can specify whether it wants shared or exclusive use on a conditional or unconditional request, thus ENQ is more general than P.

The status of the request is as follows: 1) If grantable, process is, 'queued on the last and remains, logically active Unconditional and not grantable, process is quc°: c" and 2) becomes logically blocked Conditional and not grantable, process is told that the 3) resource is unavailable I are in some sense more restrictive than P and V because ENQ and DEQ they must be paired, i. e. , every ENQ on a resource must be followed by a DEQ and no DEQ can occur (in execution) before an ENQ on the resource.

Therefore, a resource must represent a single specific item such as a tape drive, whereas Dijkstra's semaphore can represent a pool of tape drives (in the integer variable case). Also, the count associated with sera provides a means of counting the number of resources in the pool (if the counter is positive), or the number of processes waiting for the resource (if the counter is negative). It is a.'. , % 7antageous to handle pools of resources (such as tape drives) in a pooled fashion, rather than as individual items because they are all basically the same.

WAIT and POST are analogs to block and wakeup. WAIT operates on an event control block (ECB) and blocks (logically) a process, unless the ECB has previously been POSTED. POST awakens a process associated with an ECB if it has been blocked. (If no process is waiting, POST sets a flag in the ECB. ) WAIT can be generalized to allow a process to wait for n out of m possible events (n < m), but the major drawback is that it is impossible for more than one process to wait for a single event. Basically, WAIT and POST should be used only in cases in which Process A signals its completion to Process B.

Hansen's Primitives for Process Synchronization— Some primitives for syn- iori have been air -e T at message and data passing. The philosoph y is cc i s ron za an interprocess message-handling capability and will help solve synchronization problems. A similar concept is discussed concerning the data and control interfaces supported by RAMM of AADC. As an example of such primitives, consider those developed by P. Brinch HariFen in connection with the RC 4000 multiprogramming system of A/S Regnecentralen, Copenhagen, Denmark.

Ha:nseial,5 f ;ur primitives have the form: 1) SEnd message (receiver, message, buffer) 2) W.ai:t.message (sender, message, buffer) 3) Send answer (result, answer, buffer) cr) Wait answer (result, answer, buffer) Send message 1) obtains a fixed length message buffer from a buffer pool, 2) p laces message into the buffer, 3) and queues the buffer in the mes- sage queue of the specified receiver. The sending process is informed of the location of tt le buffer so it can wait for an answer. The message buffer also contains thle sender's identity. Should the intended receiver of the by message no longer be in the system, the sender is sent an answer the the system. If the receiver of a message is waiting, its state is changed from blocked (logically) to readti .

i H48 The wait message suspends the calling process until it receives a message in its queue. At that time, the name of the sender and message are copied into the receiving processes data area, the buffer is taken off the queue and its location returned to the calling process for answer trans- mission. The wait answer is analogous to the wait message, except that, on receipt of the answer, the buffer is released to the buffer pool.

The send answer copies the answer into the buffer where the message was received and places it into the sender's queue. The sender's execution state goes to ready if it was waiting for an answer.

These primitives impose very rigid conventions for process communi- cation. This may enable hardware support to be built. In Honeywell's sys- tem, the RAMM SFE can readily support such concepts. The rigid conven- tions also make things easier to analyze and understand. However, the primitives may not be economical, requiring the use of other primitives also.

Other Primitives -- MULTICS uses an exchange of messages in a common mailbox whose identity is known to the user processes by convention. The notify primitive returns the first message to be put in the mailbox, if any (otherwise it blocks the process).

GECOS (GE 600 series) uses a generalized WAIT and POST concept.

The shared objects are called events and a process can request notification when an event occurs by using a notify primitive. The event occurs when a process issues a CAUSE primitive to the event. The CAUSE then activates all processes waiting on the event.

The use of precedence fields to pass control and data boundaries between PMs in the MEC of AADC (Ref.. H6) is another example of a synchronization concept. In this case, RAAMM creates the I/OCommunication buffers for messages and I/O. Also, the process [ POST (process name) after (time)] manipulation facilities support process synchronization as detailed in Ref- erence H6.

AVVIONIC SOFTWARE LIBRARY The objectives of this subsection are two-fold. First, an investigation of the feasibility of applying the modular library concept to a multifunctional avionics problem will be made. Secondly, a study of the benefits to be gained by the application of such a library will lbe made. These investigations will be made such that the functional divisions inherent in the avionics subsys- tems considered are preserved.

H49 The approach used during these evaluations will he-gin with the selection of several avionics functions for consideration. Based on these selected functions, assessments of the applicability of the modular library concept will be made. These assessments will be extended from those considered to include a wide range of avionics; functions. In addition, the library con- cept will be considered at different levels within the selected functions.

Summary and Conclusions A library of avionics software appears to be both feasible and beneficial.

In the development of this library, it must be recognized that significant dif- ferences exist in the software for given subsystems as a function of imple- mentation and/or application. Consequently, the library must be developed at several different levels ranging from software for an entire function, key modules, and subroutines. The benefit of the avionics software library is that recurring software costs can be reduced.

A summary of avionics software that should be included in the library is shown in Figure H4. It is recommended that the software for functions such as LORAN, air data, OMEGA, and certain navigation subroutines can be standardized. Changes as a function of subsystem mechanization will be minimal. Development of library software for INS, display, and flight con- trol is recommended at a subfunction levei. A number of T.S mechaniza- tions are possible. However, there is a significant degree of software similarity between all of them. A library of key software modules should be developed with standardized interfaces. Many display functions are relatively independent of the aircraft or avionics systems. Consequently, software modules to drive integrated displays should be developed. Differ- ent equation subroutines are required to support digital flight control.

The algorithm for a Kalman filter is then independent of the application; however, the size of the matrices and the input data is unique to each appli- cation. Consequently, matrix operations will best facilitate the software development for a Kalman filter.

It is recommended that these software modules be developed at the source language level so long as the data processing hardware is not standardized. If the hardware is standardized, then an assembly language library is a reasonable alternative. In either case, it is recommended that the development of the library be preceded by the development of an easily understood Engligh language and mathematical description of each avionics function.

Benefits from this library will result from reuse of a given module across avkonic subsystem applications and reuse of the same subroutine across fun.Ctions within a given avionic system.

HSO w IN A fir( Rlrrll ft r laft Op

* wwww A"aw

NAVIGATION.

AVIONICS AIR FUNCTION LORAN OMEGA . RANGE/TIME TO GO . CHECK POINT UPDATE LEVEL K ^ p GREAT CIRCLE . RACE TRACT CROSS COURSE DEV , UjM TS! G TOLTT MNUG FLIGHT INERTIAL NAVIGATION DISPLAY WEAPON DELIVERY CONTROL FDI CLIP ( A/G) / (A/A) CCCLE,L RO OMETER OUTPUTS TO HSI NUMERICAL INTEGRATION EQUATIONSE NUMERICAL INTEGRATION ,A/C SYSTEMS EXTRAPOLATION *MEDIAN ., MATRIX OPERATION INDICATORS SELECT MATRD( ,A/C SYSTEMS ., GYRO TORQUING ,ARBS WARNING SU$FUNCTION J ST CONVENTIONAL LEVEL IIAV PANEL TRANSFORMATION i TRAIL CALCULATIONS ORD STATUS STEERING COMM STATUS TIME TO GO ,CONTROLS Lf%UNCH WINDOWS e^ COMM lAV STORES SELECT - A 'b KALMAN FILTER SUPPORT SUBROUTINES TRIG MATRIX OPERATIONS POWER SERIES ,ADD/SUBTRACT , MULTIPLY PROGRAM CONTROLLED I/C SUBROUTINE OCT/DEC ,TRANSPOSE ,INVERT BINARY/BCD BCD%6-INARY SQRT Figure H4, Software Summary M r i Selection of Avionic Subsystems for Consideration The selection of avionic components to be considered for use in a modular library must be based on properties of the components which affect that modularity.. The amount of software which applies from one mission to the next is restricted by the changes in the software that occur from one mission to the next.

The items which are considered most important in this respect include computational precision requirements, data constant values, routine param- eters, variations in algorithm implementations, and variation in module communication requirements. Each selected function must be evaluated in terms of each of these items to obtain a true assessment of the applicability of the module concept to that function.

In obtaining a true evaluation of the feasibility of the modular library concept, the avionics subsystems considered must be representative of the entire range of potential applications. In making subsystem selections, therefore, it is necessary to choose those which are likely to require recoding as a function of mission and/or subsystem mechanization as well Ens those which are not. The range of reusability is expected to extend from those modules which are completely reusable (except for data constants" those that may be highly application dependent and may not be reusable at all.

Characteristic of the first type of reuseability mentioned is a LORAN type navigation system. Its implementation is likely to change little from one mission to the next. Kalman filter data processing, on the other hand, is dependent on the application to the extent that gathering the input quanti- ties into the state variables matrices is new and unique each time a new system is defined. The computational sequence required to operate on these matrices may remain fairly standard over a numbe r of applications. Some- where in between these two problems is an inertial navigation system of one type or another. Although the computations required depend on the particular implementation of the navigation system (e, g. , platform or strap- down, etc. ), it is expected that certain functions which are common to all navigation systems can be modularized. Such common functions might include coordinate transformation, or range calculations.

Since these avionic subsystems seem to illustrate the range required, the major emphasis of the investigations will be placed on • LORAN systems • Inertial navigation systems • Kalman filter routines Secondary emphasis will be given to air data, flight control, and display.

H52 f

I

I

Feasibility Evaluations Software Library Typical computational sequences for the three avionics functions, to be For the inertial navigation considered are given in Figures H5, H6, and H7.

subsystem, the sequence is given for each of several different implementa- Using these as a base, the application of the modu- tions -of the subsystem.

The evaluations larity concept can now be evaluated for each subsystem.

A summary of will be made with respect to the criteria mentioned earlier.

these evaluations is prese-rated as Table H4, LORAN -- Of the three avionics subsystems considered, LORAN LORAN is a navigation provided the best opportunity for modularization.

hyperbolic navigation system that transmits pulses at precise intervals.

One station in the network serves as the master and the other two as slaves.

The master station transmits a pulse train which is retransmitted by each The time-of- slave at known time delays after receiving the master signal.

arrival of the three pulse trains is measured by a LORAN receiver and pro- ' vides the basis for the calculations. First, expected time differences, These are then compared based on present aircraft position, are computed, to measure time differences to obtain errors in the computed position.

Errors are then added algebraically to the computed present position to yield LORAN latitude and longitude (Ref. H7), Although different LORAN networks may transmit with different delay constants, all require the same computational precision. 24-28 bits is typical to maintain the inherent accuracy of the LORAN calculation. Since LORAN calculations are performed typically at rates of 10 to 25 times each second, the position change between each calculation is small so a large dynamic range is not required on input data values. Since most present avionics comp°ters have word lengths of 16 bits or less, double-precision calculations will also be a standard requirement for a LORAN subsystem.

Approximately 500 memory locations are required icy LORAN for con- These include --coordinate data on the LORAN transmitter net- stant values.

work, coding delay required by each LORAN slave station, and various _, correction data to compensate for geometric, magnetic, and environmental factors. If modularity is handled at the source level, this data can be pro- vided at compiles time via a "block data in FORTRAN, a "COhZ- program" FOOL" in JOVIAL, or a corresponding mechanism in anott,er higher order language.

Since all :LORAN mechanizations are based ur. the same concepts, there is justification that the computational implementation of the LORAN software = can be standardized.

Minor differences in algorithms exist in order to ex- Dloit the characteristics of one particular environment or t.'he other; however, benefits obtained are small.

H53 FIRST CHECK TO DETERMINE EM EM r K M PM IF CALCULATION IS TIME FOR THIS COMPUTE LORAN PHASE NET FIRST FOR PRESENT FACTOR CORRECTION LORAN NET E sl E sla I x sl Psl FOR MASTER AND I X SLAVES E st Es2o t2 P t2 YES FETCH AND STORE RETRILVL AND 51ORE A LONGI IUDE AND M • A N' o T CD sl ) - IP„ - P•, +E,. IBL, I E•,1 LATITUDE OF MASTER tl-M AND 5LAVE 1 AND T M EX PE C C —^ a-^-s R A sl' °sl EN ES SLAVE 2 TIME DIFRENES FOP TI ME DIF FER EN C ES FE C MASTER -SLAVE PA ) P,^ t• Es r IBL s2 . CDs2 1 -IPM . EMI 41s2-1101 1 t2' ss2 RETRIEVE AND STORE FETCH AND STORE vRESENT LONGITUDE 17 1 ANOLAT UDE INPUT a INPUT MEASURED TIME DIFFERENCES BETWEEN ST sl-M MASTER . SLAVE PAIRS T s2•M XM COMPUTE'.' DISTANCES OF LORAN MASIFIT AND s. -.a cot Ik" t I cos: 4 1 SLAVES RELATIVE TO sT %sl I sl-M - ^Tsl-M AIRCRAF I COMPUT ED X'TSl-M COMPUTE ERROR BEIWC.[N POSITION MEASURED AND COMPUTED TIME DIFFERENCE PAIR'.

i2 "n:i2 toss • sin: cas: t2 <ot '1 t2 • a1 `T 12-M • "Ts2-M c ` 7 s2•1 . c' ' 1 M Y M cos: M s.n T • ^lcot% M • cosXsll ER AND COMPUTE t .sl•M - OF M AS T ER R 10 ES a1 cos:tl s,n 4 M • SLAVES R E L A T IVE IVE 10 vsl AIRC RAF T CONIPUI ED T ^. Ico%XM - cos%i21 POST 110N ' s2•M COMPUTE % S OF To % . s,n'A • AI Ys2 Q COMPONENTS OF 1 COMPUTED TIME t. ISin% M - sinXS 1 DIFFERENCES T T t1 M X M , I rM T ti % M - Is^n —X121 CO%1PUTE REARING Y s2 •M M ANG LL HETWEEN LORAN 'a•+5'ER AN SLAVES RELAnVL 10 t-,I v x sl tl AIRCRAFI(01'PL1EU P0517 ION 1Y S2•M" T S1•M TT Sl•M X'Ts2•M LOfdPUTE x ANDY 1 • T T T Ian CO MPONENTS OF rs1 N2 ,tt2•Nt • sl-M T s2-M • Y sl-M DIFFERENCES BETWEEN xsl MEASURED AND (OAP- PUTED LORAN TIME T i _ DIFFERENCES ^' T sl ° ' T s2 's2-M -M 'sl-M-M °Y T T T s,n%M-rM-cAsXM xM 'sl-M V ,2-M ssl-M 's2•M M sn: M 1— cos: c°s: M cas s•n % • V <os% - K eA ^ COMPUTE CENTRAL ^sl N cos° ^.

tl t l sntlt 5n: . c t: cos: cot COMPUTELONGITUDE sl s] ANGLE BETWEEN l AND LATF, LITE TIf.'C 1 11R,t QAPI AND PA51EP eY EACP cttVE ^, DIFFERENCE CRRORS A ND sn xi2-Yi2- cos X 9 >2_ ^xs2 t2 M t.n.t2 smz .toss <ats s2 cot 'A S S — AT A L - 1.e1 1( m Cot: -M PM AII. -1 .

COMPUTELONGITUDE AND LAT tT UOE : L :. ec 2 1" -M 3 ^ttco 3 s 2 : s.. 2 % M • sn : - <o5 2 : M 1 2 X" P e2 s..

COMPUTE RANGE ON 00 `sl sl Z Z OUTPUT EARTH BETWEEN OUTPUT LONGITUDE AIRCRAFT AND LORAN AND LATITUDE MASTER AND SLAVES .,2 ;, jcos2: _2 xsl • s,n2: 1 tan 'sl Ps2 e 1 - I r 7 2 Xt2 cas : '12 _2 ,cot2: s,n2% - cot2= . s1 1 tan't2 s2 Figure H5. Computational Sequence for LORAN Navigation H54

Ift

^^ QU.44 TPY l f INPUT INPUT ACCELERATION V V V COMPONENTS FROM INERTIAL PLATFORM SYSTEM x l Y l z l f 1 • Vx = lV • Vx 1 • Vx v o x l t o a a COMPUTE LOCAL RADIUS 2 COMPUTE PRESENT VY = f IV • V ) • V N= all - f SIN 01I OF CURVATURE. NORMAL Yc Yo. VELOCITY COMPONENTS o "1 TO MERIDIAN V ` t N • V ) • V + o t z 1 x c ao COMPUTE RADIUS OF R - a (1 • 2f - 31 SIN2 CURVATURE IN MERIDIAN M V A • ^^ • C1 + C1 Ox=O V COMPUTE LONGITUDE, LATITU RATES DE AND ALTITUDE •' RM ` Cz • C.

COMPUTE COMPONENTS OF G y ' D E CGS. z i EARTH'S ANGULAR VELOCITY SIN ai Gz =cE h•Vt , C z • C: = y •t•3 V ^ V a= ' t a dt • x t,l x t • 't •1 ho 'o COMPUTE PRELIMINARY t' = V • f t•1 V .o ttdt C OM P UTE PRESENT a o VELOCITY COMPONENTS A Y •1 ( Y t t OSIP ON *1 OF AIRCRAFT ' t h- h dt • ho • ft•1 •o ,I zl Vzt•1=Vzt V OUTPUT h. v h OUTPUT PRESENT POSITION P . Y N1 AND VELOCITY COMPONENTS • V•' Vy , Vz COMPUTE ANGULAR VELOCITY OF THE AIRCRAFT SYSTEM Py = OF COORDINATES IN A FIXED EARTH SYSTEM SIN al WN = ( • e) COS a Vxt`1 '^'E CON __ Pz NCOS ti WE • - A + G DE COMPUTE GYRO TORQUING RATES Q x x + ( Pzt2nz ) VYt..1 -(P 2G y WD =- l6E `1) SIN A 'GDD l Vtul- C y < (P - (Px • 2 O x ) V COMPUTE COMPONENTS • 2 G) V z : x t • 1. zt•1 OF CORIO LIS A ACCELERATION -(P • OUTPUT C=(P `24 x)V 20)V z x Y •t^l Yt•1 Y OUT GYRO TORQUING RATES TO INERTIAL SYSTEM W N' W E WD 29o \h C 2 CO MPUTE LOCAL GRAVITY C 1 SIN oI 1 • - g o AT AIRCRAFT ALTITUDE A JJ gz _ =a.`a V `c x x c x x COMPUTE TOTAL ACCELERA- • • ay • ay cy V yc TION CORRECTIONS FOR EACH COMPONENT V zt = R Z • a s • A z • et R Figure HS. Computation Sequence for Platform Inertial Navigation z. -K1G`1LNT 1 PAG^B IS H55 OF POOR QUALITY Figure H7. Computational Sequence for Discrete Kalman Filter' "how Now wwwo TABLE H4. MODULARIZATION SUMMARY Computational Constant Parameters Algorithmic Program General Ease Precision Controlled I/O of Modularity Data and Arguments Variations • 24-28 bit precision Transmitter a Angular values LORAN mechaniza- a Input time differ- • typical for all LORAN coordinates tion all based on same ences from LORAN • Coordinate data mechanization concept so algorithm receiver o Coding delays Easy implementation can a Rouble precision • Output latitude/ LORAN • Environment be standardized required for most longitude values to Navigation propagation curren t avionics other systems correction computers t e Earth mag deel, correction a Accuracy required a Gyro drift rates a Number of steps Algorithm to be used • Senor inputs from is function of in numerical depands on imple- accelerometers a Accelerometer implementation. integration mentation biases Gyro torquing Moderate Inertial Differences may Platform signals • Navigation vary an order of a Initial position magnitude or more. condition a Strapdown longitude • Latitude / display outpute G ^, e Free azimuth • Polar CD and system alignment

Q

modes a Precision require- a Initial conditions a Order of matrices Algorithm is • Display output ments change as a to Kalman independent of trix starting • Kalman error • Ma Difficult Kalman function of param-, matrices characteristics of locations estimates Filter eter values, data being analyzed • Initial error • Process Precision • Wide dynamic range estimates requirement required to preserve contribution from all components.

• Scaling required Figure 20. Modularization Summary r Z _ I One common method in 3 olves a table hookup procedure in part of the calculations. This requires a large amount of core for storage of the table values. A closed-form version is available which performs the calculation required with sufficient accuracy and reduced core requirements; however, computational time requirements are high. A compromise of these two methods is an iterative method which appears satisfactory from both the storage and speed requirements as well as accurac y;. Even if these algo- rithm differences were critical to the successful performance of an avionics mission, multiple LORAN modules can exist in the library.

Inputs and outputs to the LORAN algorithm are limited and consist of time difference inputs at the algorithm iteration rate and outputs of latitude P.nd longitude. LORAN is considered to be a good candidate for module-ri- zation.

Inertial Navigation -- Inertial navigation has a few characteristics which make it less easily modularized than LORAN navigation. None the less, inertial navigation is still considered a likely candidate for incorpora- tion into a module library.

Inertial navigation computation determines current position, velocity, and gyro torquing rates using acceleration components supplied by the inertial system. These computations include the following steps: • Measure vehicle nongravitational acceleration components • Compute acceleration due to gravity and total vehicle acceleration • Integrate acceleration to obtain current latitude and longi- tude and velocity components Compute gyro torquing rates

I

There are various implementations of inertial navigation of which free azimuth, strapdown, electrostatic gyro (ESG), and stationary platform are only a few. Each of these systems requires its own unique computational sequence. Accuracy requirements also depend on the implementation. An inertial navigation system based on ESGs requires an order of magnitude greater accuracy than most other implementations. This represents a potential problem which must not be overlooked.

For inertial navigation, some of the constant quantities to be used include gyroscope drift rates, accelerometer bias, and initial latitude and longitude inputs. For inertial navigation, these constant values are a function of the individual aircraft involved and of the-position on earth where the mis- sion is to take place.

H58 The number of arguments required to implement the inertial navigation ;.package is small. Arguments include accuracy requirements and the number of numerical integration steps required along the way.

The most serious problems encountered when trying to implement inertial navigation software in a modular fashion will be due to difference in algorithms required by different hardware systems. As an example of this, consider the three systems shown in Figure H8 (Ref. H8). Figure H8 shows a system known as a "North-East-down':' system. Accelerometers are used to measure acceleration along two axes -which are held normal to each other and normal to a nominal vertical axis. These are corrected for bias errors, Coriolis acceleration, and integrated to obtain the angular velocities with respect to these coordinates. By appropriate trigonometric operations, these can be converted to a vector with three components which are used as gyro torquing inputs to re-align the platform. Figure 21b si'ows a system known as "free azimuth. " This is similar to the North-East-down system except that no torquing is applied along the vertical axis. Thus, the azimuth gimbal will have zero angular velocity about the vertical axis. In the North- East-down system the inertial coordinate system is kept close to the geo- graphic coordinate system. This is not true with a free azimuth system, and it is therefore necessary to apply coordinate transformations to the accelerometer inputs and to the torquing outputs. The free azimuth system requires more computation but has distinct advantages of accuracy when flying near the geographic poles. Near the poles the rotations around the vertical axis can become large. The required torquing signals force the gyros to be able to respond to a large dynamic range of inputs. Thus, the North-East-down system has accuracy problems near the poles. Since, in the free azimuth system, no attempt is made to torque the system about the vertical axis, it does not have the same problem, but it requires more com- putations.

Comparing Figure 118a with Figure H8b, the computational requirements for the "North-East-down" system and the "free azimuth" system are nearly the same. The exceptions are that the free azimuth system requires some coordinate transformations at both input and the output. These observations will be important to the conclusions made with respect to the modularity of inertial navigation sfotware.

A third example is a "non-rotating platform" inertial navigation system (Figure H80. In this system the platform does not rotate with respect to an x inertial system. This is accomplished via three gyros placed on a fourth.

gimbal in the system. Accelerometers, also mounted on the fourth gimbal, provide inputs of movement. Transformations are again required, and tor- quing is required with respect to three orthogonal axis. This system, however, requires a three-dimensional coordinate transformation, and the computations required break down in the polar regions.

H59 T - NAVIGATION j COMP INPUTS CALCULATIONS ACCELER- OMETERS Fi W x. .TORQUING nm SIGNALS Fix K ; S ) y ^` COMP a. NORTH-EXIST-DOWN NAV OUTPUTS COMP INPUTS i F COSY COSY I x NAVIGATION 1 ACCEL- CALCULATIONS ET EMS TORQUING SIGNALS

C F - SY

COSY COMP b. FREE AZIMUTH NAV. OUTPUTS COMP INPUT f

LF

E

TORQUING SIGNALS NAVIGATION ACCELER- WORE OOR01 CALCULATION 0 ETERS RAN NATE ffR^l'r TRANS- FORM

H:DT

COMP.

STATIONARY PLATFORM c.

Figure H8. System Functional Block Diagrams H60 From this discussion, algorithmic variations required by different im- plementations of inertial navigation will restrict the ease of modularity experienced with LORAN navigation, Notice, however, the computational similarity between the "non-rotating platform" system (Figure H8) and the two described earlier.

The bulk of the calculations are the same, but there must be coordinate transformation of the inputs similar to the free azimuth system (Figure H8b). In addition there must be integration at the outputs to ° system obtain the torquing signals required to maintain the heading.

The range of input and output values-used for inertial navigation should be easily handled. Program I/O includes the accelerometer readings and the torquing signals for the various gyros ; Latitude/ longitude coordinates will probably be required for pilot display.° The quantity of I/O and the dy- namic ranges required will be a function of the particular implementation used.

Kalman Filter -- Future aircraft navigation problems are ex- pected to involve the use of Kalman filter techniques for refining navigation data obtained via other sources (such as LORAN or inertial methods). Kalman filter techniques are based on the error models of the other naviga'ion sys- tems. These error models take into account discrepencies in computed position among the various techniques and predict a best estimate of the true position.

When this expected value of the measurement is compared to ,values actually measured, the differences can be used to correct the estimate of the aircraft's position and velocity in the next tine increment.

A sequence of such measurements, separated in time, together with an accurate mathe- matical model of the system and environment will eventually produce esti- ftates with sufficient precision to permit maneuvers to be made with confi- .

deuce, Figure H9 shows a block diagram of a Kalman filter implementation of a complex navigation system.

The Kalman filter outputs are fed back, to the navigation sensor at various points in the system and are used to form the differences between expected values and actual measured values.

Kalman filtering techniques are complex matrix operations involving state vafiFble vectors.

The way the sums and differences of various signals are produced is highly dependent on application (Ref. H9).

j This description of the Kalman filter characteristics indicates that Kalman filter computation,is not a good candidate for modularization of the functional level.

Since Kalman techniques are used to improve accuracy and refine values obtained by other methods, the , of other system signals into the state variable matrices is a new and different prob ;_, lem with each new flight system.

However, once the input values are gathered, the matrix operations required to reduce the . ,data may be, fairly standard.

The feedback of the Kalman outputs back in'to the system is again hi hl dependent on a application. . * ' . li..ation. .Kalman filterr.•?c^uYreme,^.*s do g Y P processing !

necessitate a number of matrix operations.

These ine-lude; Hb1 NAVIGATION COMPUTER ACTIVITIES + DIF F E REN CE ALI CE 1 EQUIPMENTS + + DISPLAY - BEST - (ALTITUDE AND _ CADC.

BEST ALTITUDE ALTITUDE + POSITION) \\ B L RATE + VERTICAL ACCELERATION ACCEL ACCEL. GRAVITY CA IBRATION IMU AZIMUTH HORIZ.

_ HORIZONTAL NAVIGATION BEST EARTH RATE - EQUATIONS,. LATITUDE COMPUTATION '^' . BEST + RATES + GYRO CAL.

MATRIX GROUNDSPEED, BEST 9 DRIFT ANGLE VELOCIT COMPUTATION GYRO SATES 6 + F.,I BEST D IF TORQ RATEUE + S p GROUND [ i R 3 O A DARER..

,' BEST 1 KALMAN FILTER POSITION i ^ _ OPTIMUM ERROR VELOCITY ESTIMATION 3 ALTITUDE TD - POSITION + RATE CDNVERSION 3 POSITIONS ALTITUDE 3. VELOCITIES !+ ^ _ LORAN KALMAN HEADING 2 PLATFORM TILTS 6 'iAFFERENCE Ud PLATFORM SLANT RANGE 1 PLATFORM HEAD AVERAGING RATES AND BEARING 3 GYRO DRIFTS ^ GYROS { 1. VERT. ACCEL.

EAN VERT.ACCEL.

1 DOPPLER DRIFT DOPPLER DRIFT + 1 CADC ALTITUDE 10 GROUND SPEED BAROMETRIC MULTI- SLANT RANGE ALTITUDE AND BEARING MODE -FIX PT LAT/LNG Figure H9, C-5A Kalman Navigation Mechanization

am

• Matrix addition and subtraction • Matrix multiplication Transpose multiplication • • Matrix inversion Scalar multiplication • Any attempt at modularizing the Kalman filter requirements should begin with implementation of these matrix operations. This would form a firm basis for coding the rest of the Kalman algorithm. If this is done, arguments of the matrix processing routines should include starting ad- dresses of matrices involved and their dimension. These matrix operations ` should then become part of the compile time library which form the lowest level of the subroutine hierarchy as shown in Figure H4.

By looking at Table H4, one can see that the properties of the Kalman filter are such that they become disadvantages to modularization as compared to the advantages for LORAN and inertial navigation.

Digital Flight Control-- The implementation ofdigital flight control is based on the solution of difference equations in place of analog filters. The number, sequence, order, and data coefficients for the difference equations will vary for each flight control system. Consequently, properly parameterised difference equation subroutines are required. A standard, reusable library module is not feasible. However, an English language and block diagram description of the typical computational sequence and digital filters that are '.

required for the stability augmentation and pilot relief loops is needed.

Air Data -- The calculations required for this function are relatively standard. This junction is a prime candidate for a standard library module.

Differences exist depending on (1) whether supersonic flight is possible, (2) output requirements to other subsystems, and (3) error correction terms. These differences are _slight and can be handled by allowing for data values unique to each application to be used. Power series expansion subroutines are useful for this function.

a a _j H63 REFERENCES -p H1. Parnas, D. L., "On the Criteria to Be Used in Decomposing Systems into Modules." CACM 15(12), December 1972, pp 1053-1058, H2. Haney, F. M., "Module connection analysis - A tool for scheduling software debugging activities," Proc AFIPS FJCC, 1972, H3. Liskov, B. H. , "A Design Methodology for Reliable Software Systems," AFIPS FJCC, 1972,

Proc

Dykstra, E. W., "The Humble Programmer,'' CACM 15(10), October H4.

859-866.

1972, pp.

H5, Organick, E. I., The Multics System: An Examination of Its Structure, The MIT Press, Cambridge, 1972, Thurber, K. J., et al., "Operating /AADC Preliminary H6. System Functional Specification," Final Report, Navy Contract N62269-72-C- 0051, October 1972.

H7. Study of Information Management Aspects of Integrated Avionics - Inc, , Technical Report Volume I, B. H. List, Texas Instruments No, AFAL-TR-69-166, Volume I, July 1969.

Broxmeyer, Charles, Inertial Navigation Systems, McGraw-Hill, H8.

New York, 1964._ H9, "Theory and Applications of Kalman Filtering," AGARDograph j No, 139, edited by C. T. Leandes, February 1970, AD 704306, q M H64 i

APPENDIX I LIGHT-EMITTING DIODES Introduction In the past decade there has been a rapid improvement in the efficiency and reliability of visible-light-emitting diodes (LED), the major problems limiting the performance of these devices have been mastered, and as a result large-scale manufacturing of diodes suitable for a variety of applications has become possible. GaAsl-xPx diodes that emit red light are the most widely used, but newer materials, such as GaP for green emission, Inl-xGaxP for yellow, and GaN for blue are being developed.

Luminescence is the emission of optical radiation ultraviolet visible or infrared P , light; i. e. , luminescence is a direct result of the energy released duringelectronic transi- tion within a material. Luminescence arises from a two-step process in which electrons and holes are generated in concentrations greater than those statistically permitted at thermal equilibrium, and then a significant fraction of these carriers recombine. Radia- tive recombination occurs when the energy of the recombining holes and electrons generate protons. The recombination process is nearly independent of the source of excess car- riers, but is very strongly characteristic of the p?lysical and electrical properties of the material.

Figures of Merit A measure of performance of a LED must include the relative rEtsponse of the eye at the wave length of interest. The two important figures of merit for IED's are quantum efficiency and luminence. Quantum efficiency is the ratio of the numb ' r of photons pro- duced by the number of electrons passing through the diode. The internal quantum effi- ciency is calculated in the p-n junction of the LED, while the external quantum efficiency, is calculated in the interior of the diode, The external quantum efficiency :s always less than the internal quantum efficiency due to the optical losses in the semiconductor.

Average external quantum efficiency values fall between 0. 1 and 7, 0 percent at room temperature, while internal quantum efficiencies can exceed 50 percent under optimum conditions, Table I1 (ref. Il) gives the quantum efficiency as well as the luminous power efficiency of some recent LED's.

a Because LED's t:mit radiation, they are more visible in dim ambient light and less { visible in bright ambient illumination.

Experiments at NADC show that LED's are not bright enough for military aircraft cockpit application. Also, the red LED color is not the best for aircraft use as it is a universal danger signal and is in the region of poor eye sensitivity especially for older people (ref Il). However, LED's are evidently being used to some degree in commercial aircraft and are probably only visible under bright ambient light with some shading.

LED's are high-current, low-voltage devices that are compatible with discrete MOS transistors. However, they are not readily driven by MOS IC's, particularly CMOS IC's a due to the electrical current requirement. Therefore, 'large LED displays will not be cost-competitive with other display materials (LCD, electrochromic, or electrophoretic) that can use less costly low-voltage, low-current TFT's or SOS IC's to build the elements j of an active matrix.

The fast time response of the LED makes it easy to matrix address or multiplex a display; however, display luminance will be limited unless memory of some sort is pro- The upper limit of the number of lines that can be multiplexed (or vided for each diode.

k I1 i Luminous Quantum efficiency Peak power efficiency LED Color emission wave length Commercial Research Commercial Research performance result performance GaAs P Red 6490 5.0x10-3 2.0x10-3 0.38 0.15 O. 6 0. 4 4.0xlO 3 0.76 GaAs Red- 6320 0.35P0.65 orange LPE GaP:Zn.0 Red 6925 1.5X10-2 0. 5-2. Ox10 -2 3. 0 0.1-0.4 VPE GaP:N Green 5700 1. Ox10 - 3 0. 3-0. 8x10- 3 0.6 0. 1809.48 (Zn diffusion) m LPE GaP:N Green 5700 3. 0x10- 3 0. 5-2. Ox10 -4 1.8 0.03-0.02 a (grown junction) H P :N 0.5-0.8x10-3 0.36 0.23-0.36 Yellow 5890 0.8xlO GaAs 0.15 0.85 VPE GaP:N Yellow 5900 1. 0x10 0.45 (N > /cm 2 A

Appendix I addressed) is 'the maximum permissible current through etzch diode divided by the average current required for the corresponding desired average b:tightness (ref, Il).

For line-at-a-time address, the required peak luminance BR with a desired time averaged brightness (I3) is: I3RNL -B (I1) where L is the number of di,spla, r lines, and N is the number of frames that the eye integrates in 0. 1 second.

Peak 'luminance of up to 6800 cd/m 2 (ref, 12) is possible with heat sinking and cool- ing, but 340-1400 cd/m2 is more common. 'Application of LED's is presently limited to small numerical instrument readouts of one line, but alpha-numeric vector-graphic dis- plays of up to 10 cm are technically feasible (ref, I2). Table I2 shows the time-averaged luminance levels for 16, 100, and 500 line displays, all at 30 frames/second TV rates.

TABLE I2. - MULTIPLEX OR MATRIX ADDRESS DISPLAY WITH LITMINANCH' AT 30 FRA ME/SECOND PATES Line-at-a-time address, Required contrast ratio Time-averaged numbr of lines e luminance, cd/ni2 1- 340-1400 10:1 .

i 16 63-261 53:1 100 10-42 333:1 500 (TV formate) 2.-8.4 1700:1 These displays must have a luminance of 680 to 1700 cd/m 2 when the vision is eye adapted to a cloud luminance of 3. 4 x 10 4 cd/m 2 . It can be seen that the luminance for displays with over 100 lines will have poor legibility under high ambient illuminance levels unless memory is provided between refresh periods to increase the average brightness. ` No references have been found in the literature of efforts to develop on-site memory.

Another basic problem with line -at-a-time display address is the steady-state I residual luminance of the LED in its off state, The time-averaged contrast is the time- averaged brightness of the display divided by the residual luminance of the LED, The required contrast ratio (CR)_between the peak luminance and the steady-state residual luminance is the desired time-averaged contrast (C) times the number of-lines' i (L) to be addressed, divided by the number of frames (N) integrated by the eye. Re- i quired contrast ratios are included in Table 72 for a time-averaged contrast of 10:1 at { 60 frames/second.

C = N 1, (I2) where CR is the 'required cell contrast, and C is the desired -time-averaged + contrast, 10:1.

F I3

e Appendix I It can be seen that contrast ratios requirements for a large-scale LED matrix would be severe even if the efficiency and luminance could be dramatically increased. Develop- ment of on-site memory appears to be the only way to develop matrix LED arrays for aircraft use.

Rise and decay times for LED's are in the 10 to 1000 nsec range with small teinpera- ture variation (ref. I1); therefore, temperature sensitivity can be neglected. Also, light output of the LED increaseci at a rate of approximately i%/ °C between 0" and 50°C, which is not important for most displays.

The cost of LED's are estimated at $0. 50 to $2. 50 per digit with a system cost of $1. 00 to $3. 50. Test results show that diodes can operate continuously for 50 000 hours although the light efficiency is low — 0. 1 to 0, 5 lm/VA T (ref. Il), compared to CRT's of 100 lm/W (ref. I3), Typical power dissipation for a segment in a calculator display is 0. 67 mW with an integral lens (increased brightness but reduced viewing angle) or 3 mW without a lens. A 10 by 10 alpha-numeric display with 256 (nine-segment) characters would require 7 watts for just the display.

Monolithic LED Arrays Progress is being made in the fabrication of monolithic matrix addressed arrays (ref. I4) of LED's in GaP using selective liquid-phase epitaxy (LPE) for 5 by 7 arrays.

These arrays are fabricated by GaP LPE processes on a single wafer with interconnected LED elements. Voltages of the dot matrix elements are compatible with silicon integrated circuits. This permits logic chips to be hybridized to the substrate of the GaP wafer, thus reducing the requirements for lead fan out and creating a natural inter- face with data-handling systems.

One of the problems; with monolithic displays is optical isolation between adjacent junction areas. Light spreading in GaP material would cause a large part of the semi- conductor wafer to light up the outside junction area without optical isolation. It is claimed, however, that efficient monolithic arrays in indirect GaP semiconductor can be produced by taking advantage of the air-isolated integrated circuit technology.

The monolithic display structure is preferable for small diodes with high-packing densities; the single chip approach should be used for large-area displays with low- packing densities limited for 50 elements/inch. However, changes in technology, material, cost, and applications are too rapid at the present time to permit a realisti?

appraisal of the transition point between the two structures.

Conclusions Advantages of LED's are long operation life and low-voltage requirements, Dis- advantages are low-element density (50 elements/inch) high-power consumption,- and low brightness without on-site memory. Present LED displays are probably limited to by 10 cm, 256 character alpha-numeric displays with line-at-a-time address. The 10 cm unknowns are cell isolation ratios, potential increase of efficiency, maximum packing density, and future development of on-site or intrinsic memory.

z Y F 14 '

T F r Appendix I REFERENCES IL Goodman, L. A. The Relative Merits of LEDs and LCDs, Proceedings of the SID, Vol. 16/1, First Quarter 1975, pp. 8-20.

I2. Reingold, I.: Display Devices; A Perspective on Status and Availability, Proceedings of the SID, Vol. 15/2, Second Quarter, 1924, pp. 63-74, I3. Van Raalte, J. A.: Matrix TV Displays, System and Circuit Problems, IEEE Transactions on Consumer Electronics, Vol. CE/21, No, 3, August 1975, pp.

APPENDIX J LIQUID CRYSTALS DISPLAY (LCD) Introduction crystal passive displays are many — low power, low cost, The advantages of liquid The reflective type of liquid crystal display (LCD) low voltage, and flexibility in size.

requires little power to operate compared to other types of displays such as LED's and low-discharge tubes. Because of the low cost of the liquid crystal material and the sim- of the display cell structure, the cost of liquid display is very attractive. With plicity operating voltages in the range of 1 to 6 volts, LCD's can be driven off a MOS chip or other low voltage electronics. This is an important cost advantage for a matrix display with many active elements.

Reflective dynamic scattering displays require a specular mirror-back electrode (ref. J1). This creates some viewing problems particularly under conditions of diffuse illumination (flying through clouds), and contrast wash may occur, However, this type of display material will probably not be used for aircraft application as twisted nematic material has much less power consumption with a faster response.

A diffuse reflector can be used with the +.wisted nematic display because twisted nematic does not induce light scattering. ,Consequently, an observer can see the voltage- induced change in light transmission without the chance of a reflective glare from the dynamic scattering LCD. The twisted nematic display is also visible under diffuse illu- will fall off with viewing angle unless mination. It should be noted that display contrast a drive voltage of greater than 20 volts is used. This higher voltage, however, may negate the advantage of driving the LCD with CMOS IC''s and of the ease of fabrication of large matrix displays.

Liquid crystal properties are temperature dependent and the prospects of finding new materials with low operating temperatures and wide temperature ranges is not encour- aging, The only practical solution is to incorporate a: heating element in the liquid crystal display. Manufacturers are currently quoting lifetimes of 50 000 hours as typical for LCD display with ac drive voltages (ref. J2), The disadvantage of do operation is that the electrochemical process degrades the crystals and shortens their life; the disadvantage that a capacitive coupling may partially turn on adjacent elements during of ac drive is the multiplexing or matrix address. Another disadvantage of some LCD materials is that they have a slow rise time of 10 μsec and long decay time of 100 to 300 μsec. However, on-site memory not only solves the problem of the slow rise time but increases display brightness.

LCD technology is relatively new and costs should continue to decrease as the manu- facturers gain more experience. Present costs for a 3-1/2 digit watch display 0. 2 inch high is $5. 00 in production quantities (ref. Jl), System costs for instrument applica- tions are estimated at $0. 85 to $2. 75 per digit.

Properties Liquid crystal states. — Liquid crystals differ from ordinary liquids by their reten- tion in the liquid state of certain types of crystalline order (ref, J3), The individual liquid crystal molecules have a somewhat cigar-shaped structure, An ordinary liquid" does not have an ordered arrangement of molecules and is therefore referred to as iso- tropic, ' i, e. , the crystalline properties are the same along all optical axes. Liquid I; Jl

i Appendix J crystals, however, have a nonrandom, ordered arrangement of the molecu: temperatures. These arrangements are called the liquid crystal phases and are referred to as anistropic states (crystalline properties vary along different axes), These aligned liquid crystal molecules can polarize, rotate the plane of polarization, scatter or dif- fract incident light, and produce the desired display effects, There are three liquid crystal phases: nematic, cholesteric, and smectic (Figure J1), The molecules of the nematic liquid crystals are arranged with their axis parallel, but not in layer form as in the case of the smectic liquid crystals. Nematic molecules are given region, Cho- free to slide past each other but remain essentially parallel within a lestric liquid crystals also consist of layers of crystals with parallel axes; however, the axes of the various layers are oriented in different directions within the plane of the y over a limited range of temperatures.

layers. These liquid crystal phases exist onl Below this temperature range, the liquid crystal material may become solid without cry- stalline properties and above it, the material may cease to be a crystalline liquid and may become an ordinary liquid with isotropic properties.

o119 V

00 0

o

<2-

o

^ft

Ordinary Liquid Nematic liquid crystal nn n Y1 Smectic liquid crystal Cholesteric liquid crystal Figure J1. Characteristic Crystal Structures for the Three Liquid Crystal Phases versus an Ordinary Liquid Liquid crystal materials. Commercially available liquid crystal materials must be purified to remove all Traces of water, oxygen, and unreacted components (ref. J4).

Most common nematic liquid crystal materials are either MBDA, EBBA, or a mixture of both., ,(see Table J1)._ a J2

Appendix J

TABLE Jl, — COMMON LIQUID CRYSTAL SYSTEMS

Type Temperature Comment

_F

Freeze point at 20°C, MBBA Disadvantages:

(Schiff base) Nematic at 20 0C to 41°C

Hydrolyze in presence of

moisture, acids, and bases.

EBBA Nematic at 38 0C to 60°C

Could decompose during cell

(Schiff base)

assembly. Decomposes in

ultraviolet light and sunlight.

Yellowish color, Mixture MBBA Freeze as low as -10°C, Advantages:

and EBBA Nematic at 10°C to 50°C

Both EBBA and MBBA have

fairly good scattering proper-

ties and easy to synthesize,

Trans-Stilbens Nematic at room More resistance to hydro-

temperature

C-N band of lyzation, Colorless.

Schiff replaced

by C:-C .band.

Liquid crystal effects. — Liquid crystal's most promising effects for display appli-

cation are summarized in Tables J2 and J3 (ref, J5 and J6), Figures J2 and J3 illustrate

the basic modes of operation and configurations. jj

At the present time the field effect (dielectric forces) liquid crystal displays are the

most popular (ref. J1) for matrix panels due to its low power requirements. - Of the types

of liquid crystals listed in Tables J2 and J3, only dynamic scattering, (dielectric and

conduction forces), twisted nematic (field effect), and the unknown Hughes Aircraft

proprietary field effect material will be discussed in this report

Surface alignment of liquid crystal molecules, - Only two distinct types of alignment

of the molecular nematic liquid crystal axis near the surface of an electrode face are

possible (ref. J7): homogeneous and homeotropic,

Homogenous alignment of the liquid

crystal molecules occurs when the molecules are parallel to the surface.

This type of

-

alignment is also referred to as parallel homeotropic orientation or optical normal homeo-

tropic orientation, Homeotropic alignment occurs when the liquid crystal molecules are

perpendicular to the surface, I-Iomeotropic alignment is also referred to as basal or

perpendicular homeotropic orientation or dipolar molecular

axis or director perpendicular

to the surface of the electrode,

The on or off states of a

liquid crystal phase must represent either uniform optical

clarity (one of the homeotropic states) or scattering (isotropic phase), Of all the physical interactions of liquid crystals, the interactions of the molecular with the surface are least

understood, However, permanence of molecule orientations near the surface are neces-

sary for long life time of the cell;

Perpendicular orientation of the molecule to the surface is obtained with high purity

materials and an exceptionally clean substrate.

The surface is considered to be'indiffer-

ent to the liquid, and minimum interai.cion occurs when the molecules are perpendicular

tothe surface. The presence of an interphasal material (on the surface) or surfactant

acts as an orientation layer to produce the parallel homeotropic orientation; the surface

active agent must interact specifically with the surface and the nematic liquid. These

J3

l

Field Effect and Trans- Mechanism mittance, Cell Structure Electronic Response E/O Effect Maximum Drive Time Off State On State Negative dielectric anistrophy Transparent, Cell is dark Scattering by turbulence 0. 10 pA/rm 2 -20V(17) 1 psec.at 250°C and Dynamic Scattering No 100?'1 between electrodes. if light source is not induced by charge flow. 5 10 Normal see ri 'Milky white appearance, visible, 10 psec rise time, 100-300 msec decay time ParallellIonivotropic )es Positive dielectric anisotrophic.I 13orneogenous orientation. Perpendicular homeotropie 25 0 Liquid. crystal between parallel Plane polarized light is con- orientation produces quasi- homeotropie electrodes and voted to elliptical by .iuik of isotropic scattering. De- ( crossed polarizers, parallel homeotropie liquid polarized light through + crystal, Analyzer passes analyzer produces dark plane polarized light to cell.

observer.

Field convert;; to matie and (luest-Host Yes Positive dielectric anistrophic, Dye moles ule axis aligns Id Interaction , 501, Liquid crystal with 1"; roncea- dye orientatio,,'., perpend- with nematic liquid crys+al CD tration dichroia dNe between axis in p.irallei homeotr. ,po is ular horneotropic, per- parallel homeotropie electrodes orientation l': light rector pendicular to I: light vector Color absorption is tuned ^ and parallel polarizers. parallel to d y e molecule.

X by voltage.

• 20 msec rise time Voltag Controlled ties Positive dielectric anistropic, Parallel homeotropie ncma- Liquid crystal becomes • 3V - 5V threshold I. isotropi.. and scatters light. • 7-31' maximum and 50 msec decay octical activity. or 5V. Liquid crystal between crossed it(- molecules turn 90' be y- ti.isrr ,l nemalie rubbed (parallel homeotropi ) tween electrodes, Pol irized Nemati molecules rotate • litanip/, m2 a urrent time with 5t' do 10 assume perpendicular • Good mat,li to com- drive.

electrodes and crossed nr light will follow molecules parallel polarizers. and twist 90-. ('ell is bright honieoiropio orientation plementar 1SOS • At 20'C and 3V, awa y froin electrodes. Cell • 10 l' Pulses 250 msec on and with crossed polarizers and dark with parallel polarizers. is bright with crossed 130 msec off.

- polarizers and dark with parallel polarizers.

or Nc) Saute as.Dvnamie Scattering. Transparent. Turbulent scattering in- Same as Dynamic Turn off Fast turn tiff 5 msec Chevron mode duced b y 600-11:: voltage. Scattering Milky white appearance.

Molecules are in parallel • 4 - 6V or t - 8V Deformation of Yes Negative dielectric anisotropic. Alolpcules are in perpendi- Liquid crystal between special cular homeotropie alignment. homeotropie orientation s 1 - 5 kilz Verde al1v Aligned • 5V threshold Phases ()AP Effect) perpendicular homeotropie- Polarized light is passed by and field-induced hire- cell unerfected and absorbed fringence alters polariza- • I pamplcm2 "r tuncri biro- textured surface electrodes 'ringvnco and crossed polarizers, by analyzer. tion to elliptical or 90` rotation, Some or all of the Iii ht is passed by analyzer, Grey Scale Viewing Anglf: Contrast Life Time Comment GJO Effect Cost Resolution 1 Low with do • Liquid crystal deteriorates Dynamic Scattering 10 shades above Liwest Highest 25 : with time due to de current to 100 V 1 flow 25 lineslin. 50: • Subject to cross talk with ac drive • Polarizers are not needed • Used in 90% of liquid crystal displays High Parallel ilomeotropic Color display. Density varies Guest-IIost upon field and type of dye Interaction determines color.

'CS cD ¢. 1 Highest 25 : 1 contrast decreases 40 : 1 high • Prime candidate for matrix Voltage-Controlled 20 lines/in.

displays with thin-film vacuum Optical Activity or to 4 s 1 at 40° for 'reflective 10 ; 1 at 25tj deposition transistor tech- Twisted 1Vematic and 85 1 for transmissive nology display.

Conti-act decreases from 5 : 1 at lOV • 120 x 120 matrix cells have been fabricated with TFT on- 40 : l to 30 : 1 at 30 1 off site memory from normal.

Not as good Qsrfllating domains do not Fast Turn—iffor as Dynamic scatter light as strongly as Chevron Mode intense turbulence Scattering f i Deformation of High • 1latrix addressed cells with Lowest 1000 : 1 higher Vertically Aligned 100 x 100 elements have been Phases (DAP Effect) built without cross talk.

or Tuned Bire- is fringence • possible b y bir f ingent effect.

• High purity material.

• Low cross talk.

r rn Light scattering Light absorbing Polarization modes Distortion Dynamic "New" Guest Twisted "New" w of aligned nodes host scattering nematic modes a phases i

T R T R T R T R T R T R

T (Transmissive) R (Reflective) Figure J2. The Two Basic Types of Liquid Crystal Displays and Their ------{ Basic Modes of Operation I

Ap pe ndix J

a. Light scattering

Observer

•^

♦ • •

Activated Quiescent Activated Quiescent Transmissive Reflective b. Light absorbing Observer Quiescent Activated Activated Quiescent Transmissive Reflective-

'splays

Figure J3. 'Light Paths for the Two Basic Liquid Crystal

J7

Appendix J interfaces have been generated by a variety of means including chemical cleaning or etching, rubbing, mechanical surface scribing or deformation, or the deposit of organic or inorganic; thin films (ref, J7), Positive and negative dielectric anisotropy. — The existence of electric dipoles in the crystalline molecular structure is necessary if eLectro-optic effects are going to occur.

The direction of the electric dipole moment determines whether a crystal molecule will have ,a positive or negative dielectric anisotropy, a property that controls the e le ctro- optic ;behavior of the crystalline dipolar molecule. For positive anisotropy, the com- ponent of the electric dipole moment parallel to the molecular axis is greater than that perpendicular to it. For negative anisotropy, the component of the dipole moment per- pendicular to the molecular axes is greater. Thus, an applied electric field will tend to align the positive anisotropy molecular (optical) axis to be parallel with the field. How- ever, the molecular axis of a negative anisotropy crystal will tend to rotate perpendicu- larly to the applied field. These alignments, produced by applied electric fields, are necessary to produce desired display effects.

Types of Liquid Crystals Dynamic Scattering, -- Dynamic scattering of liquid crystals occurs only with nematic liquid crystals that have a negative dielectric anisotropy. Dyna-rnic scattering cells con- sist of a few drops of nematic liquid crystals between two parallel glass plates with transparent electric conductors. Reflective displays use a highly reflecting rear elec- trode; however, if the display is to control transmitted light, t!len both the rear and front electrodes should be transparent, In the unactvvated state, the liquid crystal layer is transparent as the dipolar molecu- lar axes of the liquid crystal molecules align themselves in the same direction. If the light source is not visible in the display, all of the inactivated areas will appear black.

Whenever an electric field is applied, the molecules attempt to align themselves perpen- dicular to the field. However, due to impurities in the mixture, charged states exist, and the fluidbegins to flow. This flowing produces the hydrodynamic effect that disrupts the alignment of the molecules and in turn causes a scattering of the light because of spatial variation in the index of refraction, This scattering of light is mostly in the for- ward direction.

One disadvantage of the dynamic scattering reflective cell is that a mirror-like sur- face is required and if a bright source of light is seen as a reflection, the display can be washed out. Another disadvantage of any dynamic scattering display is the necessity of the current flow and power to create the turbulence and scattering. The threshold volt- ages for dynamic scattering is about 5 to 8 volts- with minimal contrast ratios of 5:1, However, the contrast ratio improves with voltage to 50:1 until the saturation point is reached (Table J3).

Twisted nematic, — The twisted nematic liquid crystal effect is most promising material for the matrix display application and is available commercially (ref. J8), The twisted nematic cell structure is achieved by rubbing the front and back electrodes (parallel homeotropic texture) at right angles to one another using a liquid crystal with positive anisotropy. If polarized white light, entering one face of the cell (Figure J4) is parallel to the rubbing direction, it will follow the twist around, emerging parallel to the rubbing direction to the second face,_ Thus, if the cell is placed between crossed polar- izers, the cell area is bright; if it is placed between parallel polarizers, the cell area is dark. When the field is applied above its threshold level (Figure J5), the liquid crystal bipolar molecules will rotate from the parallel to the perpendicular homeotropic orienta- tion. Therefore, the nematic liquid crystal molecules are rearranged' such that their orientation no longer has a continuous twist of 90 degrees. Hence, light now passes J8

Appendix J b. V>VTH a. V=0 Analyzer

•

- - Glass Transparent conductive ----^.

—> coating Glass Polarizer o^ (h V) 1 Orientation of (hv) ---• nematic molecules Figure X74. Side View of Twisted Nematic Effect for (a) V 0 and (b) V > VTH N 45 i r 2 4 6 8 Voltage J5. Curve (a)Shows Rotation Angle of Linearly Polarized Light Figure versus Voltage for a Nematic Liquid Crystal at Room Temperature and 1 kHz; Curve (b) Depicts the Transmission versus Voltage Response with Parallel Polarizers. The light source and detector are colinear and pointing normal to the ce 11.

Jy

f Appendix J through the nematic liquid crystals without rotating the vibration plane of polarization, The cell becomes dark (near zero transmission) between crossed polarizers and becomes j bright when the cell is placed betweenthe parallel polarizers, Hughes Aircraft liquid crystal matrix display development, Hughes Aircraft is presently developing at least two LCD's, One is a multimode alpha-numeric display being developed for NADC, and the other is a pictorial display with a TV-compatible matrix one- line- at- a-time address, Hughes Aircraft decided several years ago that LCD was the best approach for the high ambient light environment of an aircraft cockpit as neither LED' s or gas plasma displays were thought to have sufficient brightness.

j The multimode alpha-numeric display has 30 to 40 lines of information with 40 to 60 characters per line. Each character is one quarter inch high with 14 segments and one dot in a starburst pattern. The display provides a readout of weapons, fuel, and engine status and is intended to replace the warning lights. This type of display has been a checked out under high ambient flood lighting, and both NADC and Hughes Aircraft agree that the display visibility is satisfactory. The segments of all characters are wired in parallel, and individual characters are lit up by encoded digital words, Each character has a logic circuit to decode the input binary data and memory latch such that the display character stays on between refresh periods.

i The TV-compatible pictorial matrix display uses a field effect proprietary liquid crystal material. It uses silicon on sapphire LSOS chip as a substrate with MOSFET (transistors) ] with ion implementation to form the source and drain region (ref, J9).

The matrix array has a transistor and capacitor at each X-Y bus bar intersection to latch up the memory after the display element is addressed. The time constant of the on-site capacitor and the liquid crystal resistance is longer than the 1 /30 second frame rate (refresh rate) of the display, Consequently, no power is required to keep the display element turned on, i,e,, field effect LCD consumption is less than 20 watts at 5 to 10 volts, The yield of the present one-by-one inch display wafers is 2 or 3 defects out of 10, 000 elements (capacitors or transistors). The liquid crystal thickness is one-quarter to one-half mils to obtain the required time constant. Present cell resolution is 100 ele- ments per inch, and plans are for resolution of 256 elements per inch next year. Hughes is presently assembling four, one-inch elements into a quad assembly to get a 200 by 200 line resolution. Later this year plans are to go to a three-inch wafer for a larger display.

A potential problem is the cross talk betweenthe contiguous edges of the wafers formingthe quad display. The two outside edges of each quad contain the matrix address electronics. Also, the usable display temperature range is limited to 40 °C. The display is heated to permit operation at low temperature; however, very little power is required to heat the thin display, Predictions at Hughes Aircraft are that the X-Y address matrix LCD's will be used in aircraft for radar presentations and proximity warning devices. They expect that the prices will be compatible with TV displays in '5 to 7 years, The LCD is front (wedge) lighted as common with aircraft instrumentation. The present display contrast is 15 to 1 and it decreases when off from normal viewing inci- dence. -Contrast improvement of from 30 to 1 is expected with new techniques to increase the reflectivity of the surface of the liquid crystal material in its off state.

a J10

Appendix J REFERENCES J1. Goodman, L. A, : The Relative Merits of LEDs and LCDs, Proceedings of the SID, Vol. CE-21, No, 3, August 1975, pp. 213-219.

J2, Anon: Readouts are Plugable. Electronics,_ September 4, 1975, pp. 145, Gurtler, R. W.: Liquid Crystal Displays, IEEE Spectrum, November 1972, J3.

pp. 24-31, Anon: Liquid Crystal Displays Bring Flat TV Closer. Electronics, March 29, J4.

1971, pp. 106-107.

J5, Castelano, J. A. : How Heat is Off Liquid Crystals Can Show Their Colors Everywhere, Electronics, July 5, 1970, pp. 64-70, J6. Tults, J. : A Facsimile Printer Utilizing an Array of Liquid Crystal Cells, Proceedings of the SID, Vol, 12, 1971, pp. 199-203.

J7, Kahn, F. J. : Surface-Produced Alignment of 'Liquid Crystal. Proceedings of IrEE, Vol. 16, No, 7, July 1973,

APPENDIX K i ELECTROCHROMIC DISPLAYS (ECD) ) Electrochromic displays make use of color changes on the surface of a chemical They have the potential for the most contrast and the least contrast angle electrode, However, this sensitivity of any passive display (except possibly electrophoretics), material is in an early stage of development and much more research is needed before r it can be used for displays, One report (ref. KI) claims that the ECD's advantage of high contrast is offset by The report also states that although the drive voltage is short life and slow response.

low, each write and erase operation requires the passage of a charge through the display Thus the power requirement is high at video rates as it varies with the writing material.

However, a more technical report (ref. K2) states that the threshold voltage is rate.

This report differentiates between electrochromic (EC) and low, on the order of 1 volt.

The details of the various electrical and electro- electrochemichromic (ECC) systems.

optical properties, and chemical reactions are beyond the scope of this report and the reader is referred to the literature.

i It is important, however, that a reference is made to an ECC system that has 10:1 contrast and an electro-optical response time of 1 to 10 milliseconds. This is suitable Further reference is made to for matrix line-at-a-time address with on-site memory, However, a potential intrinsic memory or persistence which would then require low power.

there are crosstalk leakage problems, and this limits matrix size to about 7 lines in the This application of TFT has reflection mode unless integrated TFT circuits are used, not yet been explored, and further research is needed to determine its suitability for multiples or matrix address displays, i REFERENCES t ) K1, Sobel, A. Summary: New Techniques in Video Displays, IEEE Transactions on Consumer Electronics, Vol, CE-2.1, No,- 3, August 1975, i K2, Change, I. F.: Performance Characteristics of Electro-Chromic Displays, SID, Vol. 16/3, 1975, 168 Proceedings of the Third Quarter pp. -177, , Isl

f^ APPENDIX L ELECTROPHORETIC Introduction An EPID panel uses the electrophoretic migration of charged pigment articles in a suspension. The suspension composed of pigment particles is sandwiched between a pair of transparent electrodes with a layer of thickness of 25 to 100 micrometers.

An applied do field moves the particles toward one or the other of the electrodes, depending on the polarity of the charged particles. The reflective color of the suspen- sion layer viewed through the transparent electrode changes as a result of the migration of the particles. Take as an example white pigment particles that are positively charged in a black suspending liquid. As the white pigment particles move toward the charged transparent electrode, that portion of the panel becomes white in reflective color. On the other hand, when the other transparent electrodes are charged with an opposite polarity, the white pigment particles move to the opposite electrode and are hidden behind the black suspending liquid.

Many color combinations are possible, and the EPID panel has a memory function.

This is the result of pigment particles remaining on the surface after removal of the applied voltage due to the Van de Walls theory of attractive forces between pigment particles and electrode. This memory function serves to simplify the driving circuits and reduce the power consumption.

Applications and Development One panel (ref. L1) constructed by Matsushita Electrical Industrial has a maximum contrast ratio of 20 to 1 with rise and fall times of 20 to 10 milliseconds. Voltages required to achieve these contrast ratios depend on the type and thickness of suspension level; but for contrast levels of 20 to 1, 'voltages of approximately 50 volts are required at a frequency of one thousand cycles. This company has developed an experimental digital clock using a black and white panel with a contrast ratio 40 to 1 at 75-volt pulse j operation.- The electrical power dissipation is about 200 Mw /cm 2 at a field density of 100 V/100 μm, This referenced article does not indicate potential dot density for a matrix display; however, due to the slow rise time and decay time, on-site memory is required for a matrix display.

Another suspension display material (ref. L2) was produced by Marks Polarized a Corporation and is referred to as Herapathite dipole suspension. These cells are similar to the type already described. An ac voltage at a minimum frequency of 50 ;Hz i required, but 3 kHz is preferred. The operating voltage is typically 35 volts, peak to peak per mil of fluid path length. The cell is used in the reflective mode, and o percent less than 1 of the ambient light is reflected through the suspension fluid in the offstate; about 40 percent of the light is reflected back to the viewer from the energize"?

j areas. This yields a contrast ratio of 40 to 1.

Response time of this material was tested (ref) L3) and found to be about 50 μsec .50 volts peak to peak. Significant settling was also observed in the material (VARAD200 and 300) over a 2. 5 day period, and some discoloration was observed. Further development is needed to perfect the material.

r I A recent electrophoretic display (ref. L4) developed by Philips Laboratory consists of colloidal size particles pigment (Figure Li). The particles are T i ,'0 2 and have better light-scattering properties than any other display material tested and have L1 s

e

Appendix L excellent contrast over very wide ranges of viewing angles (see Figures L2 and L3). It is the only display that approaches the scattering properties of paper and ink. However, a d c pulse of 30 volts is required, and switching time is 100 msec. Power consumption is less than 20 μV /cm2 of area, the particles with nonuniform Principal degradation of this display is agglomeration of covering of electrode surface. The maximum lifetime is now only 10 6 cyles, but progress is being made. If a nonlinear device is added to the cell to improve the threshold, then small line-at-a-time address matrix displays are possible. -site memory can improve On the contrast such that large-area matrix displays are possible.

Conclusions The passive electrophoretic display materials require very little power (4W/cm2) and have the very real advantage of excellent contrast over wide viewing angle. However, these displays have problems with the suspended particles sticking to the electrode sur- face, deterioration of the charging characteristics of the particles, irreversible electro- chemical reation of the suspension with the electrode s,electrolytic decomposition, precipitation, slow response time, and drive requirements of 25 to 30 volts.

TRANSPARENT.

ELECTRODES { PIGMENT PARTICLES OPAQUE s LIQUID ..

:...

SPACER — t I Figure L1. 'Schematic of EPID Ce 11 L2 i J

Appendix L

F o^ eo PAPER

b ^ ^

r

EPID (Ti02I-- '^\ 0\^ m

\0

so

a

N 50 I Z F w - Z I _ 40 ^- -PLZT, L.C. AND _j 30 GROUND GLASS W i W ;`:•:.

F a 20

U

IO 6 12 18 2430 36 SCATTERING ANGLE (DEGREES) ry

Figure L2.. Scattering Profiles Comparing

the EPID Device with Several

Other Passive Display Media

Ioo Lt PAPER a INK PLZT \.

m o EPID LIOUID CRYSTALS V i0 20 ' 30 -40 50' F.. VIEWING ANGLE (DEGREES) ^.

Figure L3, The Contrast Merit Factor for

`

the EPID Device and Several

Other Passive Display Media

L3

) Z Appendix L E i REFERENCES c L1. Ota, J., et al; Electrophoretic Image Display (EPID) Panel, Osaka, Japan, Proceedings of the IEEE, July 1973.

L2 t TT= q A. M. ; Electroptical Characteristics of Dipole Suspensions, Applied r'-.s, Optics, Voame 8, No. _ 7, July 1969.

L3. Bonne, V. ; F'lectro-optical Properties of Herapathete Suspension II, Memo to J. C. Myors, Tune 1974, L4. Dalisa, A. L. Recent Progress in Electrophoretic Displays, 1974 SID International Symposium, May 1974, pp. 88-89.

a I L4

I APPENDIX M PLZT 'SYSTEMS Introduction Generally, the PLZT electro-optic material may be classified into one of three passive operational groups: memory, linear, or quadratic. Memory materials exhibit the conventional ferro-electric P versus E hysteresis loop in whici'x a continuous range of remanent polarization (polarization state with no external electric field) can be j achieved, The grains or crystallites of these polycrystalline ceramic materials are randomly orientated, but the application of polarizing electric fields causes ferro_ electric domain growth and orientation in specifically allowed directions, Consequently, polarization occurs, and a birefringence condition results, the magnitude of which is a function of the remanent polarization. When thermally depoled, PLZT ceramic materials exhibit zero effective birefringence. However,, in the electrically depoled state, a net birefringence may exist.

Memory materials with high coercive fields (typically those with tetragonal crystal structure) exhibit a linear electro-optic effect (see Figure M1). However at zero-fi-eld conditions, the linear materials possess a net birefringence that must be accounted for in operation.

The quadratic PLZT compositions exhibit a very narrow hysteresis loop (Figure Ml), 'slim- Below saturation, the electric birefringencc of the e loop" materials is a quad- ratic (Kerr effect) function of the electric field. At zero field, cubic crystal symmetry exists, and the materials are optically isotropic, exhibiting zero birefringence, ' d Extensive theoretical and experimental work has been done on optically active piezo- electric material (PLZT) at Honeywell and elsewhere. At Honeywell, basic parameters such as birefringence, switching speed, and transmission characteristics have been studied for several materials manufactured in-house. Cockpit displays have been built at Honeywell, ranging from two-color landing aid displays (PAFA;J!) to bar-type displays, and reticle-type displays.

Application of PLZT for a display suggests that it be used in a memory mode to have as high an optical -transmission duty cycle as possible. The memory mode can be ob- tained from memory-type PLZT materials or from on-site electrical memory. On-site electrical memory requires a fairly complex, though feasible, deposition of microcircuit thin-film transistors on the PLZT substrate. A system with a resolution of a few hun- dred lines per inch and a transmission factor of 1/16 appears possible, but intrinsic on- site memory is required for adequate contrast. At present, the optical transmission qualities of nonmemory PLZT are better than the memory types, principally in trans- parency and reduced scattering characteristics, j Required drive voltages for PLZT on the order of 30 to 50 volt tend to restrict the application of microelectronics, Alternately, a dc bias of 30 volts plus a reduce drive of f3 volts can be applied to reduce the drive voltage amplitude (ref, M1), j Improved PLZT materials are available, but more effort is needed to further reduce scattering and to increase transparency.

i

Appendix M c^ P P R ^a Rhombohedral Memory 8/65/35 —4 TE y 1.0 0.5 0.0 0.5 1.0 E C Normalized polarization Pi/PR o Tetragonal P -4 Linear X j 12/40/60 '. '= - E ` ^ / -15 0 15 e P t 1 m X Cubic ^a Ql^adradic E \ LOOOOO^ 10/'65/35 i E (kv/cm) s Hysteresis Loops and Electro-optic, Birefringence Char- Figure M1, acteristics for Memory, Tlinear, and Quadratic Materials in the-PLZT System; P scale _,10 μc/cm?/div., E Scale 5 I7.V / cm / div.

.. a M2

S Appendix M Modes of Operation The transparent ceramic PLZT (from the constituents elements (Pb, La, Zr, Ti) ex- hibits light transmission properties that are voltage dependent, Without lanthinum, the materials is not transparent, but exhibits conventional piezoelectric characteristics of dimensional change with applied voltage (PZT).

To use the material in a solid-state display, it is necessary to use the optical properties of induced birefringence and scatter- ing.

The active optical effects of the scattering mode are achieved by applying an electric field transverse to the direction of the transmitted light, The birefringent mode is imple- mented by operating the material such that an applied voltage will vary the polarization of the transmitted light.

The effect can be observed through an analyzer sheet as a change in intensity.

In the scattering mode, transmitted light is diverted from its normal propa- direction and is scattered into a larger solid gation by the voltage angle application of to the material, Within these two modes of operation, the material can be classified accord- ing to its memory properties.

The PLZT wafer rr,ay have memory or no memory proper- ties in either the birefringent or scattering modes.

The birefringent and scattering modes of operation caii be applied to either transmissive or reflective passive displays.

Drive Requirements Electrical for driving PLZT determined by the requirements e'lemen^s are mainly required voltage gradient and the desired switching speed. The niat -vial impedance is largely capacitive, The capacitance of a bar 7 mils wide by 1 inch long and 5 mils thick Dissipation factors (tan 5) vary from 1 percent is '12 pF for a, dielectric constant of 4000.

for memory materials (EO 70, -80, -120) to 7 percent for new memory materials_(EO-90).

Typically 10 V/mil are required to switch the materials at very low frequencies. At switching times of a few microseconds, the required voltage gradient increases by a Based on data for EO-90 from reference 1172, the required drive factor of four (ref. M2)-, voltage for a given switching time is shown in Figure M2. The pacing parameter is the thickness of the PLZT element as this determines the voltage gradient for a given applied It can be seen from the figure that for a switching time of 40 μsec, a 2 by 2 i:nil voltage.

element requires about 40-volts drive; on Lhe other hand, a 5 by 5 mil element could riot be switched much faster than 600 u.sec for tue same voltage.

Erasure or switch-off can be accomplished in one of two ways: a reverse voltage can be applied to restore the birefringence to its initial value or the material can be heated to its curie point temperature to restore it to the original :state. Heating or ther- mal erase has been used on. bar-type aircraft cockpit displays made at Honeywell. The response time for thermal erase for such configurations is approximately; l/2 second, and it could conceivably be reduced to 0. 1 second for smaller elements. Application of the thermal erase technique is limited as the material must be cooled back to its opera- ting temperature after being heated to the curie point. In a high-density, multi-element matrix, the heat generated in localized elements may be more difficult to remove and One method of thermal erasing is to may cause some _ smearing" in viewing quality.

apply an ac field of approximately 100 Hz and to traverse the hysteresis loop a few hundred times.

A voltage-pulse erase may be the only high-speed method of switching "off" in memory materials having amore "square"hysteresis loop, However.', there is the limita- tion that temperature effects will alter the geometry of the hysteresis loop such that there could be a drift or migration of the switching values of birefringence. Such changes could introduce a reduction of contrast. A compensation for temperature effects is to the matrix by operating it at a controlled temperature pvovide thermal stabilization in above the ambient.

M3 90 S ^, S Mid P GFM FNT MFNT k Z M/C F ^FMFNT 100 600 2 10 40 Figure M2, Required PLZT Driving Voltage as a Function of Switching Time for Element Sizes of ixl, 2x2 and 5x5 x 10- 3 Inches 3 Electrode Configurations A number of approaches towards electrode configuration have been made to provide the transverse field required for birefringent action in PLZT. Surface electrodes have been used, but their inefficiency in establishing a uniform transverse field has led to a slotting and applying electrodes to the sides of the slots. Further, to provide for x, y addressable elements in the matrix that are compatible with memory or nonmemory materials, methods have been worked out using slots on both the front and back surface of the PLZT wafer.

The double-slotted wafers could have a 1 mil wide by 8 mil deep slots, in which the front set of parallel slots, are at right angles to the rear set. In addition, the depths of the front and back slots overlap to allow for bringing through deposited "finger" elec- trodes,, as well as bar electrodes. A model of this grid is shown in Figure M3, This approach to a slotted wafer results in a rather fragile and costly structure, but it is j possible by proper mounting to use it in airborne 2 plications, PLZT Scattering Characteristics A study (ref.. M3) has been recently made of the scattering characteristics of several display materials including PLZT. Scattering predictions were based on a convolution-scattering model. The predictions were in agreement with experimental data of PLZT material.

M4 mom low wow MOW

Appendix M The results of the study show that two active media, PLZT and LC, have similar scattering profiles (on states) that are below that for ground glass and far below that for white paper (Figure M4), The relatively narrow forward scattering of these media, how- ever, limits their effectiveness in wide-angle direct-view display applications (Fig-are M5). The comparison of their contrast ratios show that PLZT and LC undergo a contrast reversal (Figure MO at a viewing angle near the optical axis.

In addition, electrically poled PLZT has a poor contrast ratio due to the poor trans- parency of the off state. A large reduction in the transparency of PLZT samples were shown when the material was switched from the thermally depoled state to the electri- cally poled state. It is evident that a strong requirement for an acceptable contrast ratio, in an electro-optic scattering media is a highly transparent off state, Conse- quently, the electrically driven PLZT material may have poor contrast for an aircraft display.

Conclusions The disadvantages of the PLZT material are high drive voltages, cracking under stress, poor contrast with electrical depoling, small'viewing angles, thermal sensitivity, a complex technology, and need for transverse electrical drive fields. Drive voltages of some materials can be as low as 40 volts (40 volt bias; t3 volt drive) to as high as 300 volts. The PLZT material (ref. M4) shows an extreme sensitivity of the structure to electrical and mechanical stresses. Careful and thorough annealing is required to put the material in an isotropic condition at room temperature and ordering stresses have been found to generate mechanical as well as optical anisotropy, The need for a trans- verse drive field requires either the depositing of interdigitated electrodes or cross slotting of the PLZT material itself (Figure M5).

Interdigitated electrodes are required on both sides of the PLZT material to allow matrix element address. However, this may introduce half-select and grey-scale prob- lems. Cross slotting of PLZT slabs and electrode deposition may not have these prob- lems, but cutting will be difficult on 2 to 3-mil centers. The material is already sus- ceptible to failure under stress, and cutting will probably result in a very fragile unac- { ceptable structure, In conclusion, although PLZT has the capability for intrinsic memory, there are j ptoblems with both material and electroding techniques. Moreover, as no articles in 1 recent literature have been found which suggest use of PLZT for display application, it appears that no one has found a solution to the problems, i ) ( a i Mg

rr 1 ; t } Appendix M 100— Lamberti'an

90—

Paper Ground glass _ 50 40 PLZT (Electrically depoled) U Liquid crystals (40 volts) f 0 10 20 30 5 15 25 35 Scattering angle

The Scattering Profiles of Various Display Media

Figure vT4.

y ad., ^ x

M7

' .

-` > !

' Appendix ^^ ` { ' =^ —%t77Larnbertian screen Paper and ink I - LiqLfld crystals Off ^^) 10 1 ' PLZT PLZT 7EP Cn I0 5 10 15 20 25 30 35 40 45 50 55 Viewing angle Figure M5. The Contrast Ratio of Several Display Media. (The on and off states are assumed to vary similarly so that the contrast ratio remains an arbitrarily chosen 100.^, .

^ M8 ` i ^!

Appendix M Lambertian I, Paper and ink L PLZT(TD) y i v GrOOnd glass U 14Q V Liquid crys als off 10 20 30 40 50 60 Viewing angle The Contrast Merit Factor is the Product of Contrast Figure M6.

Ratio and the Scattering Light Intensity (normalized to unity on axis for each medium) f M9

Appendix M REFERENCES M1. Bonne, U.: IC Compatible EO-Ceramic Display, Honeywell Patent Disclosure 857: 4-35, January 13, 1972, M2, Bonne, U. ; and Hicks, J, : Properties and Limitations of EO-Ceramics as Display Media II, Honeywell Memorandum HR-R- 1-243-1-32, t M3. Dolisa, A. L, : Convolution Scattering Model for Ferroelectric Ceramics and Other Display Media, Proceedings of the IEEE, Vol, 61, No. 7, July 1973, pp. 981-991, 1\14, hTeitzler, A, iI, et, al.: Polymorphism and Penferroelectricity in PLZT Ceramics, Proceedings of the IEEE, Vol, 61, No. 7, July* 1973, pp, 959-966.

F A i '7\I10 J

I APPENDIX N GAS PLASMA DISPLAYS Introduction i The gas -discharge panel has gained acceptance as a computer terminal display device. Its advantages are (ref. N1): high brightness, high contrast, inherent memory, direct digital addressing, and selective write-erase with see-through capabilities. Also, the gas panel is capable of displaying up to 300 characters.

Its disadvanage is that it is too expensive to compete with the CRT. (ref, N2).

A gas-discharge display panel consists of a pair of glass plates that are separated by a space containing the working gas mixture. Row and column electrodes are deposited on the inner surfaces of the glass and then all overcoated with thin transparent dielectric, which acts to retain the wall charges. A sustaining ac voltage of peak value is maintained across the panel, although the voltage by itself is insufficient to ignite the discharge of the panel, Discharge occurs if a selected cell, which is defined by intersection of the electrode pair, is momentarily addressed by a higher. voltage.

The cell then breaks into a self-quenching discharge that repeats itself (sustairs) at a lower drive voltage, The discharge is visible as a continuous glow in the neighborhood of the intersecting pair because of the high repetition rate (50 kHz).

Erasure of the written spot occurs by temporarily applying an erase pulse of sufficient magnitude and polarity; thus, the sus- taining voltage is reduced to below the threshold, Current Display Technology One display fabricated by IBM (ref, N1) uses a doughnut-shaped electrode thatprovides a port for viewing the gas discharge. This display has a packing density of 50 elements per inch, requires 340 to 480 volts to operate, and experiences no unwanted ignitions of neighboring cells.

National Cash Register Company has reported development (ref. N3) of 'a capacity coupled plasma, line display that has a capacity for 16 segmented numerical digits. Thick- film techniques are evidently used for the electrodes, and neon gas is used to fill the # panel. Projected life is over 20 000 hours, brightness uniformity of f7 percent over the panel, contrast ratios are greater than 50;1,and power dissipation is 100 mw/0, 7 inch digit ( ref N2).

7 Burroughs has developed a technique (ref. N4) using low-voltage MOS elements to drive the high-voltage display, The approach is to regulate the voltage on the elec- 3, trodes of the plasma display to about 50 volts short of a potential necessary to fire the tube. The MOS device can swing the anodes up 25 volts and a cathode down 25 volts to provide the firing ionization voltage; however, a cathode bias potential of -135 volts is still required,. This technique requires one MOS element diode and two resistors per segment of a digit. Therefore, a minimum number of segments would be equal to the sum of the horizontal and vertical electrodes for an HMD.

One of the advantages of the display developed by Burroughs (ref. N5) is the 'self- scanning feature, which alleviates the interconnection problem for addressing each of the matrix elements. Normally, a 512 by 512 element GPD_panel would require 1024 con- nections to the panel for addressing and driving circuits, However, this has been reduced by the self-scanning feature of the Burroughs panel to about seven driver; by using two cavities within one panel (ref. N6).

One cavity is for the display and one is for Nl

Appendix N scanning. The scanning cavities in the panel have a glow discf^arge that shifts down each column, creating a glow scan. This creates, in effect, a shift register that is an integral part of the panel. The glow discharge is established on the back side of the reset cathode and is transferred sequentially down the entire length of the panel at the rear of each cathode. The glow scan is hardly visible from the front of the display, However, a refresh memory is needed for each frame as is the case for the CRT display, The Owens-Illinois panel, on the other hand, uses a more complex multiplexed addres- sing such that only 18 lines are used instead of 1024 connections for a 512 by 512 panel while retaining the inherent memory feature, Luminance Display Peak luminance (BR) of current matrix displays is 25 700 cd/m 2 (ref. N7). Table N1 gives the scale for the time-averaged luminance (B) of matrix displays without memory from BR = BXL/N, where N 3.

TABLE N1. MULTIPLEX OR MATRIX ADDRESS DISPLAY LUMINANCE Line-at-a-time address, Times averaged luminance, No, of lines (L) cd/m2 1 25 700 ('peak brightness) 16 4800 100 771 500 153 Eye adaption vision 3.4 x 104 ( clouds) - Efforts are now underway to reduce high-voltage drive requirements (170-200 vdc) as high-voltage IC's are more vulnerable to breakdown. Experiments are also being conducted to find different phosphor na.terials for colors other than orange.

TV Flat Panel Displays i Most of the work done to develop flat panel TV is with gas-discharge devices, Efficiencies currently are at 0. 5 lm/W (ref. N2), and the limit to illuminance is power dissipation andlife. Gas-discharge devices have a sharp threshold for good contrast, while modulation voltages are low enough to be compatible with IC's, - Response time fast enough for line-at-a-time addressing, a+ Gas discharge panels are of two types; do and ac. Alternating current (ac) panels have memory (bistable - on or off) and stay on over the entire frame or refresh rate while do panels do not stay on, 'Direct current (de) panels are preferred for TV appli- cation due to simpler circuitry for gray-scale control and vertical scan, Table N2 3 (ref, N8) presents a summary of fifteen experimental TV flat panel displays announced to date with their performance. It should be noted that no panel has yet exceeded 342 cd/m2 (100 ft-L) luminance, except for a single-cell, green, mercury vapor with positive column geometry, which must be operated at 80°C, Two major problems have been reported (ref. NJ) that have prevented the development of gas-discharge matrix cells with memory for higher luminance. First, the low impedance and negative resistance characteristics of gas discharge require high-value limiting resistors a z N2

^l Appendix N and cause oscillations. Secondly, the write, erase, and sustain operating margins require close control of cell electrical characteristic uniformity, A report (ref. N10) has been published describing a gas discharge panel with graphite cathodes that provides memory and high luminance without the complication of individual rnegohm resistors for each cell.

The object is to limit the current flow and to maintain do voltage to sustain display luminance. Luminance of 3000 cd/m 2 is claimed, Further progress (ref. Nll) is being made on color displays, reduction of drive electronics cost, reductions of the number of panel connections, and reduction of con- trol voltages to within the capability of MOS IC's, Progress is also being made in gas- discharge display technology and should be monitored for application to aircraft displays, Conclusions It is predicted (ref. N5) that the resolution limit for GPD's is about 40 lines per cm. Current resolution is about 20 lines/cm (TableN2). GPD's require greater drive complexity than LCD's, and the electronics is more expensive, However, if LSI's can be modified to higher voltages or if GPD operating voltages can be reduced, then the cost of the driving circuits could be reduced.

Although power consumption is low, high drive voltages of 170 volts are a distinct disadvantage. MOS elements might be used with the Burroughs low-voltage technique (ref. N4), but mounting these elemen c. presents a mechanical problem. On-site or inherent memory must be used for displays over 100 lines as the luminance is not high enough for aircraft application with line-at-a-time address, Most GPD's lack grey scale, but it is being developed, and grey scale is of no concern for an alpha-numeric display.

Costs of present GPD's are too high for a 500-line matrix; the cost per digit is $0.'75 to $1. 90, and system cost is $1.-50 to $3. 00 per digit, Assuming the cost per matrix element is equal to one segment, 1/9 of $0. 75 or $0. 08/element yields 'a display cost of $21 000, This technology should be followed as progress is being made to reduce cost, drive complexity, and to improve luminance.

r a ) a i s N3

i t

Appendix N

i

TABLE N2, -- CHARACTERISTICS OF CURRENT GPD

^i Report - ?d.

Calculated luminance Luminoun Video storage, Panel t e, rc ion luminance at Contrast Panel size i Company h Color intensity (foot-lambert efficiency of discharge used ruwsx columns 0, 600 or 0, 2 ratio duty factor flmnenslwattiinodulatton duty factor (perrentl Philips dc, negative glow Orange 60 ft-1. 11 ft-f . 0, 2 Em/W 10:1 Analog, continuous duty 2 in. x 5 in.

'isitile emission 1, 1% 40 x 100 factor Zenith de, negative glov . Orange 8 ft-L 8 R-1_. 0.1 4m 40:1 Analog, continuous 6,.'I in, x 2,4 . in, / W F visible emission 0.2 a current 212 x 80 Bell tabs Orange 2r, ft-L, 15 ft-L Analog, continuous . 8,1 in.. x 3,4 in.

de, negative glow 0.1 4m/W 30:1 visible emission 0, 33:0 current 222 x 77 .fapan dc, negative glow Orange Iii ft-L, NR NR 25 : 1 Nil NR Nutt Broadcasting visible emission Ali Co, Bell Labs dc, negative glow White 11 R-L, 2.2 ft-J. 0, 09 4 m/W NR :analog, continuous G, G in, x 0,42 in, 110 x 7 - visible emission and 1^b current phosphor excited by low-energy electrons Red, N$: Nil Nil 0, 040 in, dfam, Philips de, positive column 0.8 4mAV NR VV excites. Blue, 2. "T, 16 x 16 phosphors Green Toshiba dc, constricted Orange 60 fi-L, 0.G ft-L at 0 20:1 Digital, 16 discrete 2.0in, x 3.6 in.

.4 4ni/W glow visible 0.35a 4.. currentlevels 46 x 65 4x 1 10 emission blitsubishi. ac, negative glow Orange NR NA NR--- 12 discrete NR ::NR Digital,.

visible emission duty factor levels 128 x 128 Sony dc, negative glow Orange . 2.5 ft-.L 21 ft-1: n. 6.4r1 / W 40;1. Digital, 32 .discrete 4,'-' in. c 6, 51n, visible emission 0.24^,': - luvcl. wing duty 212 s '41?

- factor and current modulation Red, 7 ft-L 0, 05 4 m llitachi dc, r,gative glow 2. S 11-1 / w 8:1 Digital, 64. discrete 4. 7 in, x 6, in,.

tTV pirsphor Blue, white, mhiti, levels using duty 120 x 160 Green 0. 38e, excitation factor and current modulation l NHK de., negative glow Red,. 5It-L . 1.25 ft-L. 0, 074r^ I tV ' . 30;1 .Analog, continuous Sin, xG.41n, UV phosphor Blue, white duly factor and 127 x 160 white 3 excitation Green 0. 0?6 current modulation J G'1'&1r Orange 25 ft-L, NA Digital, 64 discrete - 6.5 in, x 8-5 in, ac, negative glow lilt, NR visible emission nearly duty factor levels 512 x 512 1005, GT&1; dc, positive column Red, 16 It-L : 25 ft-L 1.2 Rm/W Data is for single cells, no panels reported VT excites phosphors Blue, green, green.

_l ' Green 0.15 Zenith dc, positive column .tied, 960 ft-L ^ 400 ft-L 3.4 tm/W Data is for single cells, no panels reported UV excites phosphors ' Blue, green spot green. spot Green luminance, luminance- i . 0. 18% Bell labs ac, negative glow. Orange NR, 100% NA NRt- NR Digital; ordered 512 x 512 dither visible emission

Appendix N REFERENCES N1, Welber, B. et, al, : A Gas Display Panel with Quasi-Axial liiectrode Configurations, 1972, SID Digest of Technical Papers, p. 32, Panel Journal Scientific N2, Weston, G. F . : Plasnia Displays. of Physics, E. : Instruments, 1975, Vol„ 8, pp, 981-991, Coleman, W. E.., et, al.: An-All-Thick-Film A. C. Plasma Line Display.

.N3, Proceedings IEEE, Nov, 1972.

N4, Lee, J. Y. et, al, : MOS Chip 'Plus Level-Shifting Circuit Drives Gas-Discharge Display. Electronics, March 1973.

N5, Stepke, E. T.: Display Terminals: The Callenge of the GPDs Electro-Optical System Design, October 1972, Sobel, Alan: Summary, New Techniques in Video Displays.

N6. IEEE Transactions on Consumer Electronics, Vol, CE-21, No. 3, August 1975, pp. 290-297, N7, Van Roalte, J. A. : Matrix T. V. Displays; ,System and Circuit Problems.

IEEE ! Transactions on Consumer Electronics, Vol. CE-21, No. 3, August 1975, pp. 213- 219.

N8. Chodil, Gerald: Gas Discharge Plasma for Flat-Panel. IEEE Transactions on Consumer Electronics, Vol, CE-21, No. 3, August 1975, pp, 221-235, N9, Holtz, G. E. : Post Gas Discharge Display with Memory, 1972, SID Digest of Technical Papers, p. 36.

N10,Smith, James: Experimental Storage Display Panels Using DC Gas Discharges without Resistors, IEEE Transactions on Electron Devices, Vol, ED-22, No, 9 September 1975, pp. 642-649, N1.1.Sobell, Allan: Introduction to Special Joint Issue on Display Devices and Systems.

IEEE Transactions on Electron Devices, September 1975, pp. 629-633.

i Ap i a a N5 f I ^ h ^ ^ ^ s x APPENDIX O a ELECTROLUMINE SCENT DISPLAYS (ELD) Electrol.uminescent (EL) matrix displays are under development, and resolutions of up to 12 line pairs/cm- 2 for areas of 15 by 15 cm have been reported (refs. 01 and 02).

Vacuum-deposited thin-film transistors provide the required nonlinearity for good thresh- old and a contrast of 50:1 (ref. 03), Matrix address is line at a time with an ac drive of 8'0 volts <(rms) at 8 kHz. Consequently, the capacitance of the ac driven phosphor between two electrodes cannot be used as a storage capacitor; an extra capacitor and associated a switen (transistor) is required for,on-site memory to provide frame-period storage at each display element.

Maximum cell luminance, with a virtual 100 percent duty cycle, is 1.40 cd /m2 watt under typical alphanumeric display conditions. Progress Power consumption is one is 'being made toward developing a gray-scale capability, and the display is expected to operate at TV video rates..

i i Direct current EL phosphors do not require on-site memory and can be driven at lower voltages but have a short lifetime. Alternating,EL driven phosphors have a life of over 20 000 hours with luminance levels of 340 cd /m^ (ref. 04), but the driving voltage becomes high (250 V rms).

REFERENCES Large Scale Integration for Display Screens. IEEE Transactions on 01. Brody, T. P.

August 1975, pp. 260-288.

Consumer Electronics, Vol. CE-21, No. 3, 02. Kramer, G: Thin-Film-Transistor Switching Matrix for Flat-Panel Displays.

Proceedings of the SID, Vol. 16/3, Third Quarter, 1975.

03. Brody, T. P.: A Six by Six Inch 20-Line per Inch Ele ctro- Luminescent Display Proceedings of the SID, Vol, 16/3, Third Quarter' 1975, pp, 158-167, Panel, IEEE Transactions on 04. Sobel, A.: Summary: New Techniques in Video Displays, Consumer Electronics, :Vol. CE-21, No. 3, August 1975.

Ana

^ d i APPENDIX THIN FILM VERSUS SILICON TECHNOLOGY One promising approach to the development of an integrated matrix flat panel display Thin-film technology has recently emerged from a maturing thin-film device technology, (TFT) has now advanced to the state where thin-film integrated circuits (TFICs) are deposited on the same insulating substrate in one vacuum pump-down. Thus, integration of the drive electronics around the edge of the flat-paneled display with the X-Y electrodes TFICs offer the advances of low cost, unique packaging, and on-site memory is possible.

and systems applications for the development of an aircraft display.

The present integrated circuit (IC) -technology uses monolithic silicon crystal into- The asso- grated circuits (SIC) formed within the surface of a single block of silicon.

ciated passive elements are either formed within the silicon surface or are deposited over The TFT approach in to replace the the semiconductor substrate by thin-film techniques, All components, including crystalline semiconductor by an inert insulating substrate.

active and passive elements, are deposited upon a substrate by thin-film techniques.

These thin films are prepared entirel3} by sequential thermal evaporation through shadow masks of the respective metal, semiconductor, and dielectric materials on the insulating substrate, TFTs (matrix on-site memory) deposited on insulating substrates have many It makes interfacing with other electronic and system components easier.

advantages, Also, this technique does not suffer f rorn any of the limitations of high voltages or high power and can be used for gas panel matrix displays requiring high or low voltage LCDs.

Costly chip and wire bonding is eliminated and reliability is improved over silicon tech- Also, nology, and TFTs have a higher yield over larger areas than silicon chips.

localized defects in silicon substrates will result in defective transistors; this is not the TFICs have a much lower, cost than SIGs due to the <nexpensive sub- case with TFTs.

Silicon technology strate and starting materials and the single-step batch processing.

As this technology is a maturing technology, approaching the end of its rapid growth.

begins to saturate, the next big breakthrough in cost reduction will come from thin-film Also, develop- technology, which has the potential for a factor of 10 2 to 10 3 lower cost.

ment of TFTs was abandoned in the late 1960 1 s due to persistent stability problems.

These stability problems have been solved, however, and the solution has been confirmed by research with experimental data (refs, .F1 and P2).

Fabrication of liquid crustal (LC) cells with thin-film deposition of TFT, storage For example, a capacitance, and X-Y electrodes has already been accomplished.

laboratory thin-film twisted nema.tic LC transmissive cell developed by Westinghouse has _a 20 line/inch resolution (ref. P3), The basic addressing scheme of the LC thin-film matrix display is shown in Fig- Each matrix element of the LC panel is composed of a TFT, which is integrated ure P1.

The combination allows rapid address with a suitable storage capacitor (C 11 , etc.).

and temporary capacitive storage of charge sufficient to activate the slower responding The TFT is used only as a simple on-off switch and the required performance is LC.

mode st.

The row generators (Figure P1, 'R1, Matrix address is at a line-at-a-time rate.

A serial-in-parallel-out shift register-con- etc. ) turn on the TFTs along a given row.

taining one horizontal line of video information is connected to the column generators The charge, which represents a video pulse level, is then stored in capacitor (C1, etc).

When the next row, R.2, is addressed, C 11 through the conducting TFT from column C 1 .

There it the formally addressed TFTs turn off and trap the charge on the capacitor.

Pi

Appendix P C 21 C12 CI.

C2 Figure P1, Line-at-a-time Addressing Scheme stays until the next addressing occurs at one frame time later. The charges of video l information on columns C through C come from the storage of the serial-in-parallel-out shift register, The polarity of the video signals are reversed for each frame period.

The TFT, X-Y/electrodes, and capacitors are deposited on a LC glass face plate in one vacuum pump-down. This is achieved in twelve deposition steps through the use of a variable raulti-aperture mask and four materials (ref, P3). It is expected that thin-film depositions on a liquid crystal will reduce the number of wires and connections needed for matrix address. The drive electronics must be mounted along the edges of the panel to allow operation of a transmissive display and must be integrated with a termination of the X-Y electrodes.

i S I b s P2

Appendix P REFERENCES P1, Cramer, G.: Thin Film Field Effect Transistors. International Microelectric Symposium, Oct, 22, 1973, Sadasiv, G.; et al, Thin Film Circuits for Scanning Image-Sensor Arrays, P2, IEEE Transaction, ED15, 1968, p. 215, P3. Fisher, A, Design of a Liquid Crystal Color TV Panel, IEEE Conference on Display Service, C, 11, Oct, 12, 1972, i F..

P3

APPENDIX Q LUMINANCE AND CONTRAST REQUIREMENTS Luminance of emissive displays is reduced if the active elements are not on during the 0. 1 second integration time of the eye. Most display materials are quoted for their peak luminance unless it is the time-averaged luminance of the display that is measured.

It is necessary to know the refresh rate of a display when it is multiplexed or matrix addressed to establish the relationship between the required peak luminance (BR,) and desired time-averaged luminance (B).

=BNL

BR (Q1) where N = number of refresh periods during 0. 1 second integration time of the eye, L = number of characters to be sequentially multiplexed or the number of lines of a matrix display being driven one line at a time.

The required peak luminance must be 170 times the time-average of brightness for a 500-line matrix address display with a 30 TV frame rate, It is apparent that a display with intrinsic or on-site memory would greatly improve display luminance as the driven element would be on during the entire refresh period.

The luminance of a display (instantaneous threshold) must be at least 1/100 of the luminance level of the surroundings (to which the eye is adapted) to be visible. however, this data was from test of a black square with an angular subtend against a white back- ground, and a smaller ratio of 2/100 or 5/100 should probably be used for a/c displays Therefore, an aircraft display should have a luminance of from 680 to 1700 cd/m 2 to be visible with the eye adapted to the luminance levels of white clouds (i, e. , 34 000 cd/m2), The intrinsic contrast between on and off elements of a display are degraded when that 1 display is multiplexed. The relationship of the required display intrinsic contrast ratio (CR) to the desired time-averaged contrast ratio (C) is i C N X L C R = (Q2) The intrinsic contrast between cells is measured when the display element is on over the entire integration time of the eye. The time-averaged contrast is measured while the display is being multiplexed or matrix addressed and the display cell is not on con- If a time-averaged contrast of 10;1 is required, then an intrinsic contrast of tinuously.

1700:1 is required for a 500-line matrix display with a 30 .frame refresh rate (N = 3. 0).

Because few display materials have this high of an intrinsic contrast, on-site _memory is needed for matrix addressed passive displays.

This contrast expression (Equation Q2) is valid for a passive reflective display under any conditions of ambient illumination as the luminance ratio is the same as the contrast ratio, However, the contrast of an active display is degraded by any ambient 'illumination on the display due to direct sun illuminance or ambient illuminance from the sky. The time-averaged contrast (C) of an active display is also C=C (Q3)

L

QI

1 ( Appendix Q or BI-Ii N C = (Q3a) B Lo L where BI-Ii is the peak cell brightness during the on time, and B Lo is the average ce11 brightness during the off time.

The time-averaged contrast ratio changes when the luminance due to the effective display reflectance (R) with an incident illumination (E) is added to the intrinsic cell Luminance levels BH i and BLo; (B + R E/rr) N Ei C _ (Q4) / T + R E r) L (B Lo or R E / Tr) ( B Hi + N C = (B (Q4a.)

/CR + R E L TT — T) H, It can be seen that the time-averaged contrast is reduced by any illuminance on the display.

The required (peak) display luminance (B Hi) during the cell on time is found from the above equation to be RE(N/L - C) (Q5) rjIn Tr (C/CR - N/L) An example of increased display luminance requirements is given here for explanation, Direct sun illuminance is about 100 000 lm / m 2 , Ambient illuminance (EC) on the display from white cloud luminance (BC) over a solid angle (0) of 1, 6 ste p radians (esti mate of solid angle of white 'bright clouds through cockpit windows) is approximated as C S2 BC (Q6) EC _ 1 6 x 34 000 cd/m a EC = 28 000 lm / m 2 A non'multiplex display (N/L = 1. 0) in direct sunlight with an intrinsic contrast ratio -(CR) of 100:1, a desired display contrast (C) of 10 with a cell reflectance of 0, 05 would require an intrinsic_ peak luminance (B Ii) of a _ RE (1 - C) (Q7) BHi n {C CR - 1) In substituting for the case of direct sun illumination, a 0.05x105 (1- 10) i BI3i (10/100 -'1) ) BHi = 16, 000cd/m 2 and in cloud ambient 1111 1mination, BHi = 4456 cd/m2.

i Q2

a

Appendix Q It should be noted that as the intrinsic contrast (C R ) approaches the required contrast (C) or when C/C becomes unity, the display luminance requirement becomes infinite, It can be concluded that the intrinsic contrast of a nonmultiplexed display should be roughly ten times the desired display contrast to avoid unreasonable display brightness require- ments in an aircraft.

The display luminance and intrinsic contrast ratio requirements for a matrix line- at-a-time display becomes severe in the ambient illumination of an aircraft cockpit. The required peak display intrinsic luminance is RE (NIL - C) B (Q$) = Hi 1 7 (C C R NIL)

i

The numerator is negative as N/L is less than C for matrix displays, Therefore, C/CR must be less than N /L to have a positive (real) solution for the display peak luminance.

If C/C R is to be 10 times less than NIL to minimize the peak luminance requirements, R then the intrinsic contrast (C ) must be 17 000:1. This is for the matrix display case for C = 10, L = 500 lines, and N 3.

CR > 10 N (Q9) 10x10 x500 C > R

t

CR > 16 660:1 This high contrast is expected because matrix address cell elements are on for a short time, ,making residual luminance of the "off" cells significant, Therefore, it is critical that there be very little drive leakage to the off cells, i.e. , the off cells residual luminance must be 17 000 times less than the peak luminance of the on cell. The peak display luminance requirement for this case in direct sunlight is 0, 05 x 10 (3/500 - 10) B (Q10) Hi r (10/ 17 000 __ - _ 3 500) 106 cd/m 2 for direct sun luminance BIi - 3. 0 x for ambient sky luminance BHi 8. 2 x 10 6 cd/m

i

These luminance levels are very high compared to what is available for flat panel materials. The best solution for matrix displays in an aircraft is to develop on-site intrinsic or inherent memory capability; it can be concluded that development of on-site 5 memory is a firm requirement for active matrix addressed displays in an aircraft.

This analysis does not account for the improvement of display contrast and reduction of display brightness through the use of ambient light suppression face plates, louvers, or filters because these devices, will probably not reduce the brightness or contrast requirements of a nonmemory active display to a reasonable level. These devices, however, will permit some active nonmultiplex displays or a matrix display with on-site memory to function in ambient illumination. Operation in ,direct sun may be possible only for a passive display in the -nonmultiplex mode, i

i

a Q3

Appendix Q REFERENCES y

r APPENDIX R OPTICAL .MEMORY PROJECTION Optical memories are being researched using both real image and holographic storage.

The major problems in this area are concerned with the storage media; the major need is a permanent, yet selectively erasable, storage medium. Techniques that may be viable in the 1580 time frame are given Table R1. (reference R1). Two of these approaches will be discussed in more detail. Optical memories will be aimed at the secondary and mass memory areas of the memory hierarchy and .,along with bubbles, constitute a threat to existing magnetic technologies.

I Table R1, Characteristics of Optical Storage Media Storage Write/ Memory Material Density 2 Read Problems Erase Bits/CM Photochromic 106 Optical Optical Gradual data loss (Alkali Halides) Absorp- Absorption tion Ferroelectric 4 Ferro- Current Sense- 10 Resolution-lifetime (BaTiO ) electric Destruction Ferromagnetic Thermal Magneto- Low readout efficiency 16 MnBi Optic Therrnoplasti.c 106 Thermal Optical Resolution-efficiency hologram Semiconductor Electron Cathode life beam Optical 10 Capacitors Beam deflection Electron Beam Addressed Memory (EBAM) I An EBAM memory is shown in Figure Rl. A beam of electrons is generated by an electron lens onto a storage target, where the beam causes local physical changes. The bit size corresponds to the size of the beam at the target. Addressing is achieved by deflecting the beam to different areas of the target plane. Either random access or block access can be achieved, depending on 1-iow the target is scanned. Electrostatic .means can be used to focus and deflect the beam, Storage Readout Deflector hlane syskem Lens Electron gun Figure Rl. Major Components of EBAM Tube R1 al

Appendix R One method stores data by depositing charge generated by the beam in the oxide of the MOS capacitors located on the target place. The charge state of the oxide is subsequently probed by the same beam during readout. No structure is necessary in the plane of the MOS target, thus fabrication and beam-target registration are simplified. Fatigue effects caused by prolonged write-erase operation have been noted. These effects are thought to be related to radiation-damage effects in the bulk silicon (reference 132). EBAM'S are useful for storage systems in the 10 7 to 10 10 bit range and can provide access in 0, 5 to 3 μsec, Write speeds of 1 megabit/sec and read speeds of 10M bits/sec can be achieved.

Because MOS capacitors are used, the data must be refreshed. Volatility can be ensured with a flood beam to restore lost charge. Costs of 0. 02¢ to 0, 05¢/bit are forecast with densities of 2-4x10 6 bits/inch 2 (reference R3, 114).

General Electric's BEAMOS (Beam Addressed Metal Oxide Semiconductor) Memory uses unstructured MOS chips and an electron lens to read, write, or erase. The memory can operate without power for over a month, has an access time of 30 μ sec, and a transfer rate of 10 Mbits /sec (reference R5).

Problems that must be overcome in this technology include; • Beam forming and deflection • Improving cathode life a Improving storage medium • Reducing fatigue effects High-density modules will be fabricated with the main limitations on size being the size of the storage cell and the amount of deflection possible.

The dynamic nature of this technology, and the flood beam necessary to achieve non- volatility, limits the use of this high-capacity technology to on-line applications rather than archival storage. The speed of operation qualifies it for secondary storage use.

Laser Memories Two basic types of read/write laser memories are under development today one stores a hologram of t1ie,data, and the second type stores the actual data in -a bit serial fashion.

Holographic Memories. — The storage media most commonly used are photographic film and thermoplastic materials. A block diagram of a laser holographic memory with- out moving parts is shown in Figure R2 (reference R6), Such a memory with a capacity of 108 bits and access times of 1 to 5 μsec should be feasible in 1980 if a suitable storage medium can be developed. While the theoretical bit density limit is on the order of 6x 108 bits /in 2, the practical limit may be more like 6 x 10 7 bits /in 2 Experiments have already produced systems with data rates of 50 Mbit/channel, thus high speed can be expected from this technology (reference R7), The elements shown in the figure perform the follow- ing functions; 0 Laser provides an intense monochromatic light source, i • Modulator - a crystal whose temperature and bias voltage is very precisely controlled to effect transparent-to-opaque state change and thus modulate the laser beam, a X-Y Deflector - a'crystal whose index of refraction is varied by appropriate voltage and temperature bias to deflect light.

) • Deflector Optics used to direct and condense light, R2

Appendix R !

Modulator Deflector optics_ Deflector Laser I Input Electronic control unit Output Modulator

0°

b

° b^0

° o o

4p ° o ° o

Flys eye lens °° h Page composer Detector array Holographic storage medium Figure R2. Holographic Memory without Moving Parts R3

Appendix R • Page Composer - an array of light valves upon which information is composed before entry into the storage medium, Storage Medium - the medium upon which the digital information is stored.

• Detector Array - a photosensitive readout transducer.

• Control Unit - provides overall system control, j The storage process requires that data bits first be entered and stored in a page com- poser, which is an array of x -y addressed light valves or shutters electrically or optically operated according to the required bit positions and states, as specified by the control unit. This transforms the data bits into a two -dimensional digital pattern or page having light and dark spots.

g p The page composer is placed near a lens; when the page composer and lens are illuminated with the laser beam, a pattern, which is the Fourier transform of the bit pattern array produced by the page composer, is formed at the plane of the holographic, storage medium. A reference beam, obtained by splitting the original laser beam, is made to be coincident with the Fourier transform pattern. The resulting interference pattern is recorded in the storage medium in the form of a hologram. Because individual bits are not uniquely recorded in a hologram, the system is quite tolerant of such things as dust or surface impurities on the recording medium.

by moving the incident Holograms are stored in other locations on the storage medium optical system beam with the beam deflector. The beam deflector system <s followed by an that positions the beam on any element in an x-y array of small fly s-eye lenses. Move- ment of the beam from one lens to another changes the position of the recorded hologram in the x-y plane. Likewise, the reference beam tracks the signal beam such that both address the same spot in the storage, medium.

Data are read out by addressing a hologram with only the reference beam or else another beam incident at the same angle as the reference beam. The reference beam is - diffracted by the hologram, and an image of the page composer data is projected through a field lens onto a photodetector array having the same relative dimensions as the page originally stored, in the page composer is incident on a photodetector composer. Each bit in the array, and the data are converted back to an electric signal. Each photodetector is connected to a transistor flip-flop, which is set by the photodetector signal and read out by the controller (reference R8), x a Figure R3 a holographic memory that employs a moving tape. The operation shows of this system is much the same as the preceding approach except that a one-dimensional hologram is stored on -a movable medium (in this case a thermoplastic tape). While this approach suffers an access time penalty over the fixed medium approach, it allows storage of 2 x 108 bits per linear foot of 1/4 inch wide tape. , The maximum storage capacity and access time is, thus, a function of the tape length. A 50-foot tape could contain 10 10 bits.

Serial Memories. — The two-dimensional holographic memory stores or records up to to be stored and 10 5 bits at a time; the single-dimension hologram allows about 300 bits read at once The serial laser memory stores a single bit at a time. Thus, the read/ write speed of the holographicapproaches are much higher than the serial laser memory.

i Serial laser memory development has been aimed at both ROM and RAM applications.

The main difference between this approach and the holographic approach is the use of low cost - lasers and the elimination of complex optical parts.

power - thus low a As with the holographic approach, serial memories can be constructed using a fixed moving media and have about the same storage density and capacity. The main draw- or backs of the approach are the speed reduction due to serial operation, and the dependence uniformity due to the ;single location of each data bit.; The main advantages are Oil media cost, size, and reliability.

R4

I

I

i

Appendix R I j Problem Areas. — Technical difficulties are currently encountered in all subelements of laser memory systems and some are discussed briefly below.

Laser power of up to 10 watts may be required for the holographic approaches, and current prices would place these devices at around 20 thousand dollars, thus affecting cost advantages of the system. Lasersalso require elaborate cooling apparatus if they are the high-power variety (reference R8).

The most serious roadblock to development of a read/write laser memory is that of the storage medium. If a suitable medium is not found, R/ W laser memories may not be i feasible.. The use of thermoplastics, for example, requires thermal deformation of the film, and fatigue problems have been shown after only a few thousand erase/write cycles. j a The storage capacity of a fixed medium holographic memory is also limited by the size of the optics required. Capacities beyond 10 8 bits will most likely require precision lenses over 1/2 meter in diameter. This will adversely affect the cost, size, and weight parameters of the memory system.

l The limited lifetime of the laser and the elaborate optics required also present R9), potential reliability problems (reference C onclusions. — • Laser memories are limited to 10 8 to 109 bits, if fast access (1-5 μsec) j is to achieved.

• Read/write laser memories depend upon development of a suitable storage medium.

• Reliability and cost of high-powered lasers may limit the use of holographic laser memories even if a suitable medium is found.

• EBAMS appear to be a better choice.

Josephson Memory Devices Experimental superconducting Josephson devices have been shown to operate at very high speeds and have ultimate density limits that exceed present day photolithographic capabilities.

memory cell for a Figure P e r sist ent incl ckwiseOor counterclockwise circulating urren^ts (1 /2) directiions represent odata stored as a logic one or zero respectively. When an external current,Iw is applied, W B A j i Figure R4. NDRO Random Access Memory Cell R6

j Appendix R it splits equally into both branches and is superimposed on the existing circulating current.

Thus, Iw will flaw through one branch and no current will flow through the other. As long as the loop remains superconducting, the original current is restored when the external Iv, be detected by applying ex- is switched off. The direction of circulating current can thus ternal currents Iw and Is. I s causes devices to switch only when the control current ex- i ceeds Iw/2. Data is written by coincident word current Iv, and bit current Ib, which to the alternate branch.

rerouted the work current With line-width limits of two microns, these cells have been fabricated in 1. 4 mil t and have switched in less than 100 psec. It has been shown that 5 x 10 8 read operations do not disturb the data contents.

DRO memories can be fabricated using a single device per cell and even higher bit densities than the NDRO cells.

Like semiconductor. memories, Josephson devices allow the fabrication of decoders, drivers, and sense circuitry of the same technology and on the same substrate as the j memory cells. Thus, with these devices, large-scale integration is feasible.

The main obstacle to the Josephson device development is the low reproducability of extremely thin and defect-free oxide tunnel barriers. Encouraging improvements 3 the are being made however.

limits, a 4K bit NDF RAM with a 2. 5 p sec cycle With present day photolithographic time could be fabricated with a bit density of 2 x 10 5 bits/in - a 16K bit DRO cell could be fabricated with 20 to 30 nsec cycle time and 6. 5x 10 5 bits/in 2 . These estimates assumed that the technology was developed and ready for manufacture. If line-width resolution could be improved as a result of uv, e-beam, or x-ray ex_osure techniques, density and speed would improve (reference R10).

i { i R7

Appendix R Hodges, D.; Alternative Component Technologies for Advanced Memory Systems, R1.

Computer, September 1973, pp. 35-37.

Cohen, M. and Moore, J.; Physics of the MOS Electron-beam Memory, Journal of R2.

Applied Physics, December 1974, pp. 5335-5348 Kelly, J.; The Development of an Experimental Electron Beam Addressed Memory R3.

Module, Computer, February 1975, pp. 32-42, R4. Martin, R. and Franekl, H.; Electronic Disks in the 1980s, Computer, Iebruary 1975, pp. 24-30.

Hughes, W., et al.; BEAMOS - A New Electronic Digital Memory, Proceedings, R5.

National Computer Conference, May 1975, pp. 541-548, R6. Butter, C. D. and Lee, T. C. Thermoplastic Holographic Recording of Binary Patterns in PLZT Line Composer, IEEE Transactions on Computers, April 1975, 402-406.

pp .

R7. Roberts, H., , of al. ; IIigh Speed Holographic Digital Recorder, IEEE Transactions on Applied Optics, April 1974, pp. 841-856.

y Williams, J., Stevens, J. ; Research Guidelines for Laser Memories, System R8.

Development Corporation document TM-IiU-201/000/00, 5 June 1975.

Little, A, D., Inc.; Technology and Cost Forecasts for Electronic Data Processing R9.

Hardware, Software, and Data Communications Networks, Contract No, , F 19628- 74-C-0093, 15 February 1974.

R10. Anacker, W.; Superconducting Memories Employing Josephson Devices, Proceedings, National Computer Conference, May 1975, pp. 529-534.

i r