Data Sheet AD5940/AD5941

ADC Circuit Features....................................... 55 ADC Circuit Operation......................................55 ADC Transfer Function.....................................55 ADC Low Power Current Input Channel...........56 Selecting Inputs to ADC Mux........................... 56 ADC Postprocessing........................................ 57 Internal Temperature Sensor Channel............. 57 50 Hz/60 Hz Mains Rejection Filter.................. 57 ADC Calibration................................................57 ADC Circuit Registers...................................... 58 ADC Calibration Registers............................... 64 ADC Digital Postprocessing Registers (Optional)........................................................71 ADC Statistics Registers.................................. 72 Programmable Switch Matrix...............................74 Switch Descriptions.......................................... 74 Recommended Configuration in Hibernate Mode.............................................................. 74 Options for Controlling All Switches................. 74 Programmable Switches Registers.................. 76 Precision Voltage References............................. 87 High Power and Low Power Buffer Control Register—BUFSENCON................................87 Sequencer........................................................... 89 Sequencer Features.........................................89 Sequencer Overview........................................ 89 Sequencer Commands.....................................89 Sequencer Operation....................................... 91 Sequencer and FIFO Registers........................93 Waveform Generator........................................... 99 Waveform Generator Features.........................99 Waveform Generator Operation....................... 99 Using the Waveform Generator with the Low Power DAC............................................. 99 Waveform Generator Registers........................99 SPI Interface......................................................104 Overview........................................................ 104 SPI Pins..........................................................104 SPI Operation.................................................104 Command Byte...............................................104 Writing to and Reading from Registers.......... 104 Reading Data from the Data FIFO................. 104 ECC for DATA FIFO...........................................106 ECC Algorithm................................................106 Sleep and Wake-Up Timer................................ 107 Sleep and Wake-Up Timer Features.............. 107 Data Sheet AD5940/AD5941 TABLE OF CONTENTS analog.com Rev. G | 3 of 142 Sleep and Wake-Up Timer Overview............. 107 Configuring a Defined Sequence Order......... 107 Recommended Sleep and Wake-Up Timer Operation......................................................107 Sleep and Wake-Up Timer Registers............. 108 Interrupts............................................................112 Interrupt Controller Interupts...........................112 Configuring the Interrupts............................... 112 Custom Interrupts........................................... 112 External Interrupt Configuration......................112 Interrupt Registers.......................................... 113 External Interrupt Configuration Registers..... 118 Digital Inputs/Outputs........................................ 122 Digital Inputs/Outputs Features......................122 Digital Inputs/Outputs Operation.................... 122 GPIO Registers.............................................. 123 System Resets.................................................. 127 Analog Die Reset Registers........................... 127 Power Modes.....................................................129 Active High Power Mode (>80 KHz)...............129 Active Low Power Mode (<80 KHz)............... 129 Hibernate Mode..............................................129 Shutdown Mode............................................. 129 Low Power Mode............................................129 Power Modes Registers................................. 129 Clocking Architecture.........................................132 Clock Features............................................... 132 Clock Architecture Registers.......................... 132 Applications Information.................................... 137 EDA Bioimpedance Measurement Using a Low Bandwidth Loop.................................... 137 Body Impedance Analysis (BIA) Measurement Using a High Bandwidth Loop............................................................. 138 High Precision Potentiosat Configuration.......139 Using the AD5940/AD5941, AD8232, and AD8233 for Bioimpedance and Electrocardiogram (ECG) Measurements.... 140 Smart Water/Liquid Quality AFE.................... 141 Outline Dimensions........................................... 142 Ordering Guide...............................................142 Evaluation Boards.......................................... 142 Automotive Products...................................... 142 REVISION HISTORY 2/2026—Rev. F to Rev. G Changes Table 4............................................................................................................................................ 17 Changes to SCLK Section........................................................................................................................... 104 5/2025—Rev. E to Rev. F Changes to Internal Temperature Sensor Channel Section...........................................................................57 12/2024—Rev. D to Rev. E Changes to Table 9........................................................................................................................................ 25 1/2024—Rev. C to Rev. D Changed Master to Initiator and Slave to Target (Throughout)........................................................................1 Changes to Features Section.......................................................................................................................... 1 Change to Applications Section....................................................................................................................... 1 Changes to Figure 2........................................................................................................................................ 5 Deleted Figure 3; Renumbered Sequentially................................................................................................... 5 Changes to ADC RMS Noise Specifications Section.....................................................................................16 Change to Table 9..........................................................................................................................................25 Change to Low Power DAC Section.............................................................................................................. 30 Changes to Equation 6 and Equation 7......................................................................................................... 31 Changes to High Speed DAC Output Attenuation Options Section...............................................................45 Changes to Figure 29.................................................................................................................................... 50 Change to Table 38........................................................................................................................................52 Changes to ADC Circuit Features Section.....................................................................................................55 Changes to ADC Postprocessing Section..................................................................................................... 57 Data Sheet AD5940/AD5941 TABLE OF CONTENTS analog.com Rev. G | 4 of 142 Changed Sinc2 Filter (50 Hz/60 Hz Mains Filter) Section to 50 Hz/60 Hz Mains Rejection Filter Section.... 57 Added 50 Hz/60 Hz Notch Filter Section....................................................................................................... 57 Change to Table 43........................................................................................................................................58 Changes to Table 45...................................................................................................................................... 60 Changes to Table 46...................................................................................................................................... 60 Changes to Table 51...................................................................................................................................... 62 Changes to AFEx Switches Section.............................................................................................................. 74 Changes to Figure 35.................................................................................................................................... 75 Change to Sinusoid Generator Section......................................................................................................... 99 Change to Table 122....................................................................................................................................102 Change to SCLK Section............................................................................................................................. 104 Added ECC for DATA FIFO Section and Table 127; Renumbered Sequentially......................................... 106 Added ECC Algorithm Section, Table 128, and Table 129...........................................................................106 Changes to Active High Power Mode (>80 KHz) Section............................................................................129 Changes to Clock Features Section and Figure 52..................................................................................... 132 Changes to Table 171.................................................................................................................................. 132 Deleted Key Protection Register for the CLKCON0 Register—CLKCON0KEY Section............................. 132 Changes to Table 172.................................................................................................................................. 133 Data Sheet AD5940/AD5941 FUNCTIONAL BLOCK DIAGRAM analog.com Rev. G | 5 of 142 Figure 2. AD5940/AD5941 Functional Block Diagram Data Sheet AD5940/AD5941 GENERAL DESCRIPTION analog.com Rev. G | 6 of 142 The AD5940 and AD5941 are high precision, low power analog front ends (AFEs) designed for portable applications that require high precision, electrochemical-based measurement techniques, such as amperometric, voltammetric, or impedance measurements. The AD5940/AD5941 is designed for skin impedance and body impedance measurements, and works with the AD8233 AFE in a complete bioelectric or biopotential measurement system. The AD5940/AD5941 is designed for electrochemical toxic gas sensing. The AD5940/AD5941 consist of two high precision excitation loops and one common measurement channel, which enables a wide capability of measurements of the sensor under test. The first excitation loop consists of an ultra low power, dual-output string, digital-to-analog converter (DAC), and a low power, low noise po- tentiostat. One output of the DAC controls the noninverting input of the potentiostat, and the other output controls the noninverting input of the transimpedance amplifier (TIA). This low power excitation loop is capable of generating signals from dc to 200 Hz. The second excitation loop consists of a 12-bit DAC, referred to as the high speed DAC. This DAC is capable of generating high frequency excitation signals up to 200 kHz. The AD5940/AD5941 measurement channel features a 16-bit, 800 kSPS, multichannel successive approximation register (SAR) ana- log-to-digital converter (ADC) with input buffers, a built in antialias filter, and a programmable gain amplifier (PGA). An input multiplex- er (mux) in front of the ADC allows the user to select an input channel for measurement. These input channels include multiple external current inputs, external voltage inputs, and internal chan- nels. The internal channels allow diagnostic measurements of the internal supply voltages, die temperature, and reference voltages. The current inputs include two TIAs with programmable gain and load resistors for measuring different sensor types. The first TIA, referred to as the low power TIA, measures low bandwidth signals. The second TIA, referred to as the high speed TIA, measures high bandwidth signals up to 200 kHz. An ultra low leakage, programmable switch matrix connects the sensor to the internal analog excitation and measurement blocks. This matrix provides an interface for connecting external transimpe- dance amplifier resistors (RTIAs) and calibration resistors. The ma- trix can also be used to multiplex multiple electronic measurement devices to the same wearable electrodes. A precision 1.82 V and 2.5 V on-chip reference source is available. The internal ADC and DAC circuits use this on-chip reference source to ensure low drift performance for the 1.82 V and 2.5 V peripherals. The AD5940/AD5941 measurement blocks can be controlled via direct register writes through the serial peripheral interface (SPI) interface, or, alternatively, by using a preprogrammable sequencer, which provides autonomous control of the AFE chip. 6 kB of static random access memory (SRAM) is partitioned for a deep data first in, first out (FIFO) and command FIFO. Measurement commands are stored in the command FIFO and measurement results are stored in the data FIFO. A number of FIFO related interrupts are available to indicate when the FIFO is full. A number of general-purpose inputs/outputs (GPIOs) are available and controlled using the AFE sequencer. The AFE sequencer allows cycle accurate control of multiple external sensor devices. The AD5940/AD5941 operate from a 2.8 V to 3.6 V supply and are specified over a temperature range of −40°C to +85°C. The AD5940 is packaged in a 56-lead, 3.6 mm × 4.2 mm WLCSP. The AD5941 is packaged in a 48-lead LFCSP. Data Sheet AD5940/AD5941 SPECIFICATIONS analog.com Rev. G | 7 of 142 AVDD = DVDD = 2.8 V to 3.6 V; the maximum difference between supplies = 0.3 V; IOVDD = 1.8 V ± 10% and 2.8 V to 3.6 V; the ADC reference, excitation, DAC, and amplifier = 1.82 V, internal reference; low power DAC reference = 2.5 V, internal reference; TA = −40°C to +85°C for the AD5940 and AD5941, unless otherwise noted. TA = −40°C to 105°C for the AD5941W, unless otherwise noted. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments BASIC ADC SPECIFICATIONS Pseudo differential mode measured relative to ADC bias voltage (voltage on VBIAS_CAP1 pin, 1.11 V), unless otherwise noted; specifications based on high speed mode, unless otherwise noted; ADC voltage channel calibrated in production with PGA gain = 1.5; AFE die clock for the analog domain (ACLK) = 32 MHz or 16 MHz, unless otherwise noted Data Rate2 fSAMPLE 400 kSPS High speed mode; decimation factor = 4 200 kSPS Normal mode; decimation factor = 4 Resolution2 16 Bits Number of data bits Integral Nonlinearity2 INL Normal Mode −4 ±2.0 +4 LSB PGA gain = 1.5, 1.82 V internal reference,1 LSB = 1.82 V ÷ 215 ÷ PGA gain −5.6 ±2.0 +4.7 LSB PGA gain = 9, 1.82 V internal reference Differential Nonlinearity2 DNL Normal Mode −0.99 ±0.9 +2.5 LSB PGA gain = 1.5, 1.82 V internal reference; 1 LSB = 1.82 V ÷ 215 ÷ PGA gain, no missing codes DC Code Distribution3 ±6 LSB PGA gain = 1.5, low power mode, ADC input = 0.9 V; ADC output data rate = 200 kSPS; 1 LSB = 1.82 V ÷ 215 ±6 LSB Input channel is low power TIA = 1 μA, RTIA = 512 kΩ, RLOAD = 10 Ω, ADC output data rate = 200 kSPS ±6 LSB Input channel is high speed TIA = 1 μA, RTIA = 10 kΩ, RLOAD = 100 Ω, ADC output data rate = 200 kSPS ADC ENDPOINT ERRORS Offset Error Low Power Mode −600 ±200 +600 μV PGA gain = 1.5, low power mode, all channels except AIN3 −620 ±200 +880 μV PGA gain = 1.5, AIN3 only High Power Mode2, 4 −1.1 ±0.5 +1.4 mV PGA gain = 1.5 Drift over Temperature2 ±3 μV/°C Using 1.82 V internal reference Offset Matching ±2 LSB Matching compared to AIN3 Full-Scale Error −1000 ±400 +800 μV PGA gain = 1.5, excluding internal channels and AIN3; both negative and positive full scale; error at both endpoints −1000 +1000 μV PGA gain = 1.5, AIN3 only High Power Mode2, 4 −2.2 ±0.9 +1.82 mV PGA gain = 1.5 Internal Channels2 0.2 0.75 % FS AVDD/2, DVDD/2, VBIAS_CAP, VREF_2V5, VREF_1V82, AVDD_REG Gain Drift over Temperature2 −3 ±1 +3 μV/°C Full-scale error drift minus offset error drift Gain Error Matching ±3 LSB Mismatch from channel to channel PGA Mismatch Error2 ADC offset and gain calibration5, 6, 7, 8 with a gain value of 1.5 PGA Gain = 1 to 1.5 −0.2 +0.1 +0.3 % PGA Gain = 1.5 to 2 −0.2 +0.1 +0.3 % PGA Gain = 2 to 4 −0.65 +0.2 +0.65 % PGA Gain = 4 to 9 −0.65 +0.2 +0.65 % ADC DYNAMIC PERFORMANCE fIN = 20 kHz sine wave, fSAMPLE = 200 kSPS; using AINx voltage input channels; PGA gain = 1.5 Signal-to-Noise Ratio SNR Includes distortion and noise components Data Sheet AD5940/AD5941 SPECIFICATIONS analog.com Rev. G | 8 of 142 Table 1. (Continued) Parameter Symbol Min Typ Max Unit Test Conditions/Comments 80 dB PGA gain = 1, 1.5, and 2 762 dB PGA gain = 4 702 dB PGA gain = 9 Total Harmonic Distortion2 THD −84 dB Peak Harmonic or Spurious Noise2 −86 dB Channel to Channel Crosstalk2 −86 dB Measured on adjacent channels Noise (RMS)9 800 nV/√Hz Chop on 400 nV/√Hz Chop off ADC INPUT Input to ADC mux Input Voltage Ranges2 0.2 2.1 V Voltage applied to any input pin V Pseudo differential voltage between VBIAS_ CAP pin and analog input from ADC mux −0.9 +0.9 V Gain = 1 −0.9 +0.9 V Gain = 1.5 −0.6 +0.6 V Gain = 2 −0.3 +0.3 V Gain = 4 −0.133 +0.133 V Gain = 9 Input Current Range2 0.00005 3000 μA Low power TIA and high speed TIA current input channel ranges Common Mode Range2 0.2 1.1 2.1 V Leakage Current −1.5 ±0.5 +1.5 nA AIN0, AIN1, AIN2, AIN3/BUF_VREF1V82, AIN4/LPF0, AIN6 (TA = −40°C to +85°C) −6 +6 nA CE0, RE0, SE0 and DE0 (TA = −40°C to 85°C) −3.5 ±0.5 +3.5 nA AIN0, AIN1, AIN2, AIN3/BUF_VREF1V82, AIN4/LPF0, AIN6 (TA = −40°C to +105°C) −8 +8 nA CE0, RE0, SE0 and DE0 (TA = −40°C to +105°C) Input Current2 −8 ±2 +8 nA AIN0, AIN1, AIN2, AIN3, AIN4, AIN6, CE0, RE0, SE0, and DE0 Input Capacitance2 40 pF During ADC acquisition Antialias Filter 3 dB Frequency Range2 Three programmable settings Mode 0 50 kHz Mode 1 100 kHz Mode 2 250 kHz ADC Channel Switch Settling Time Time delay required after switching ADC input channel; excludes sinc3 settling time Antialias Filter −3 dB Cutoff Frequency2 250 kHz 20 μs 100 kHz 40 μs 50 kHz 60 μs DISCRETE FOURIER TRANSFORM (DFT)- BASED IMPEDANCE MEASUREMENTS2 With High Bandwidth Loop For impedance (Z) of 1000 Ω (0.1% tolerant resistor), excitation frequency = 0.1 Hz to 200 kHz, sine amplitude = 10 mV rms, RTIA = 5 kΩ; RCAL = 200 Ω;1% accurate temperature coefficient 5 ppm/°C; single DFT measure- ment; DFT using 8192 ADC samples; Hanning on; HSDACCON Bits[8:1] = 0x1B for low power mode and impedance measurements ≤80 kHz; HSDACCON Bits[8:1] = 0x7 for high power mode and impedance measurements ≥80 kHz Data Sheet AD5940/AD5941 SPECIFICATIONS analog.com Rev. G | 9 of 142 Table 1. (Continued) Parameter Symbol Min Typ Max Unit Test Conditions/Comments Accuracy Magnitude −1.25 ±0.2 +1.25 % 20 kHz to 200 kHz ±0.2 % 10 Hz to 20 kHz ±1 % 1 Hz to <10 Hz Phase −0.3 ±0.1 +0.3 Degrees Three-Resistor Star Cell Accuracy R1 = R2 = R3 = 2.2 Ω (see Figure 17); 0.1 Hz to 200 kHz Magnitude ±0.5 % Phase ±0.5 Degrees Accuracy R1 = R2 = R3 = 100 Ω connected (see Figure 17); 0.1 kHz to 200 kHz Magnitude ±0.2 % Phase ±0.2 Degrees With High Bandwidth Loop, 50 kHz, 4‑Wire Isolated For Z = 1 kΩ (0.1% tolerant resistor); excitation frequency = 50 kHz; sine amplitude = 0.6 V p-p; RTIA = 1 kΩ; CTIA = 32 pF; Isolation Capacitor 1 (CISO1) = 15 nF; Isolation Capacitor 2 (CISO2) = Isolation Capacitor 3 (CISO3) = Isolation Capacitor 4 (CISO4) = 470 nF; current-limiting resistor (RLIMIT) = 1 kΩ Accuracy Device to device repeatability for three devices at 50 kHz Magnitude 0.26 % Percentage error Phase 1 Degrees With Low Bandwidth Loop For Z = 100 kΩ; excitation frequency = 100 Hz; sine amplitude = 1.1 V p-p; RTIA = 100 kΩ; CTIA = 100 nF; CISO1 = 15 nF; CISO2 = 470 nF; RLIMIT = 1000 Ω Frequency Range 1 300 Hz Accuracy2 Device to device repeatability for three devices at 100 Hz Magnitude ±0.3 % Percentage error Precision2 Magnitude 450 Ω Standard deviation High Speed Loop See Figure 17; valid for impedance spectroscopy, voltammetry, and pulse tests Allowed External Load Capacitance2 100 pF R2 + R3 ≤ 100 Ω; R1 ≤ 100 Ω 50 pF R2 + R3 ≤ 500 Ω; R1 ≤ 100 Ω 40 pF R2 + R3 ≤ 1600 Ω; R1 ≤ 800 Ω; frequency ≥ 1 kHz Excitation Amplifier Bandwidth2 3 MHz Impedance Frequency Range2 0.015 200,000 Hz LOW POWER TIA AND POTENTIOSTAT Input Bias Current2 TIA Amplifier, SE0 Pin 80 200 pA Potentiostat Amplifier 20 150 pA Offset Voltage2 50 150 μV Offset Voltage Drift vs. Temperature 1 μV/°C Noise2 Unity-gain mode; V p-p in 0.1 Hz to 10 Hz range 1.6 μV Normal mode (LPTIACON0 Bit 2 = 0) 2 μV Half power mode (LPTIACON0 Bit 2 = 1) Potentiostat Source/Sink Current2 −750 +750 μA Normal mode (LPTIACON0 Bits[4:3] = 00); from CE0 −3 +3 mA High current mode (LPTIACON0 Bits[4:3] = 01 or 11 from CE0 DC PSRR2 70 dB At RE0 pin; RTIA = 256 kΩ; RLOAD = 10 Ω Data Sheet AD5940/AD5941 SPECIFICATIONS analog.com Rev. G | 10 of 142 Table 1. (Continued) Parameter Symbol Min Typ Max Unit Test Conditions/Comments Input Common-Mode Range2 300 AVDD – 600 mV Output Voltage Range2 300 AVDD – 400 mV Normal mode (LPTIACON0 Bits[4:3] = 00; sink/source = 750 μA 300 AVDD − 400 mV High current mode (LPTIACON0 Bits[4:3] = 01 or 11); sink/ source = 3 mA Overcurrent Limit Protection2 20 mA Amplifiers try to limit source/sink current to this value via internal clamp Allowed Duration of Overcurrent Limit2 5 sec User must limit duration of overcurrent condition to less than 5 sec or risk damaging amplifier Allowed Frequency of Overcurrent Conditions2 1 Per hour Short-Circuit Protection2 12 mA When amplifier output is shorted to ground PROGRAMMABLE RESISTORS Low Power TIA RLOAD on SE0 Inputs2 0 Ω RLOAD Accuracy 0.01 0.08 0.15 Ω 10 Ω RLOAD Accuracy 9.8 11.7 13.5 Ω 30 Ω RLOAD Accuracy 28 33.8 39 Ω 50 Ω RLOAD Accuracy 48 55 63 Ω 100 Ω RLOAD Accuracy 88 110 130 Ω ±200 ppm/°C 10 Ω, 30 Ω, 100 Ω, 1500 Ω, 3000 Ω, and 3500 Ω ±400 ppm/°C 50 Ω Low Power TIA RTIA10 on SE0 Input2 Accuracy −5 +20 % User programmable; includes 1 kΩ, 2 kΩ, 3 kΩ, 4 kΩ, 6 kΩ, 8 kΩ, 10 kΩ, 16 kΩ, 20 kΩ, 22 kΩ, 30 kΩ, 40 kΩ, 64 kΩ, 100 kΩ, 128 kΩ, 160 kΩ, 192 kΩ, 256 kΩ, and 512 kΩ 100 120 140 Ω 200 Ω setting with RLOAD = 100 Ω Drift over Temperature ±100 ppm/°C Mismatch Error2 Error when moving up or down one RTIA value −0.6 +0.2 +0.6 % 512 kΩ to 2 kΩ range excluding 40 kΩ −3.5 +0.5 +3.5 % 40 kΩ (up to 48 kΩ, down to 32 kΩ) ±20 % 200 Ω High Speed TIA RTIA on SE0 Input Accuracy 20 % User programmable; includes 100 Ω, 200 Ω, 1 kΩ, 5 kΩ, 10 kΩ, 20 kΩ, 40 kΩ, 80 kΩ, and 160 kΩ Drift over Temperature ±200 ppm/°C High Speed TIA RLOAD on SE0 Input2 User programmable; includes 10 Ω, 30 Ω, 50 Ω, and 100 Ω Accuracy 102 110 116 Ω Fixed 100 Ω target setting Drift over Temperature ±160 ppm/°C High Speed TIA RTIA on DE0 Input2 User programmable; includes 0.1 kΩ, 0.2 kΩ, 1.5 kΩ, 10 kΩ, 20 kΩ, 40 kΩ, 80 kΩ, and 160 kΩ Accuracy 100 135 170 Ω 100 Ω setting 190 250 320 Ω 200 Ω setting ±20 % 1 kΩ, 5 kΩ, 10 kΩ, 20 kΩ, 40 kΩ, 80 kΩ, and 160 kΩ Drift over Temperature ±350 ppm/°C 100 Ω and 200 Ω settings ±200 ppm/°C 1 kΩ, 5 kΩ, 10 kΩ, 20 kΩ, 40 kΩ, 80 kΩ, and 160 kΩ High Speed TIA RTIA Mismatch Error on DE02 Error introduced when moving up or down one RTIA value −3.5 +1 +3.5 % 160 kΩ to 5 kΩ range −25 ±2 +5 % 1 kΩ, 200 Ω, and 100 Ω Data Sheet AD5940/AD5941 SPECIFICATIONS analog.com Rev. G | 11 of 142 Table 1. (Continued) Parameter Symbol Min Typ Max Unit Test Conditions/Comments High Speed TIA RLOAD on DE0 Input2 Load resistor on the DE0 pin (RLOAD_DE0) Accuracy 0.001 0.15 Ω 0 Ω setting 5 11 Ω 10 Ω setting 26.5 32.6 37.6 Ω 30 Ω setting ±15 40 % 50 Ω and 100 Ω settings Drift over Temperature ±0.2 %/°C 10 Ω setting ±200 ppm/°C Excludes RLOAD = 0 Ω and 10 Ω HIGH SPEED TIA Bias Current2 1 nA Maximum Current Sink/Source2 −3 +3 mA Ensure RTIA selection generates an output voltage of <±900 mV with PGA gain = 1 Input Common-Mode Range2 300 AVDD − 700 mV Output Voltage Range2 200 AVDD − 400 mV Overcurrent Limit Protection2 17 mA Amplifier attempts to limit the source/sink current to this value via the internal clamp; tested with RLOAD = 0 Ω and RTIA = 100 Ω Allowed Duration of Overcurrent Limit2 5 sec Allowed Frequency of Overcurrent Conditions2 1 Per hour Short-Circuit Protection2 12 mA When amplifier output is shorted to ground LOW POWER, ON-CHIP VOLTAGE REFERENCE 2.5 V 0.47 μF from VREF_2V5 to AGND; reference is measured with low power voltage DAC and output amplifier enabled Accuracy ±5 mV TA = 25°C Noise2 60 μV p-p Reference Temperature Coefficient2, 15 −25 ±10 +25 ppm/°C PSRR DC 70 dB AC11 48 dB AC 1 kHz; 50 mV p-p ripple applied to AVDD supply HIGH POWER, ON-CHIP VOLTAGE REFERENCE 1.82 V 0.47 μF from VREF_1V82 to AGND; reference is measured with ADC enabled Accuracy ±5 mV TA = 25°C Reference Temperature Coefficient2 −20 ±5 +20 ppm/°C PSRR DC12 85 dB DC; variation due to AVDD supply changes AC 60 dB AC; 1 kHz, 50 mV p-p ripple applied to AVDD supply ADC Common-Mode Reference Source2 1.11 V 470 nF from bias capacitor on ADC (VBIAS_CAP) to AGND; reference is measured with ADC enabled Accuracy2 ±5 mV TA = 25°C Reference Temperature Coefficient2 −20 +20 ppm/°C DC Power Supply Rejection Ratio PSRR 80 dB DC variation due to AVDD supply changes AC Power Supply Rejection Ratio PSRR 60 dB AC 1 kHz, 50 mV p-p ripple applied to AVDD supply LOW POWER, DUAL OUTPUT DAC (VBIAS013 AND VZERO0) VBIAS0 specifications derived from measurements taken with potentiostat in unity-gain mode and measured at CE0; VZERO0 specifications derived from measurements at VZERO0; dual output low power DAC Resolution2 Number of data bits 12-Bit Mode 12 Bits 6-Bit Mode 6 Bits Data Sheet AD5940/AD5941 SPECIFICATIONS analog.com Rev. G | 12 of 142 Table 1. (Continued) Parameter Symbol Min Typ Max Unit Test Conditions/Comments Relative Accuracy2 INL 12-Bit Mode −3.5 ±1 +3 LSB 1 LSB = 2.2 V/(212 − 1) 6-Bit Mode −3.5 ±0.5 +2 LSB 1 LSB = 2.2 V/26 Differential Nonlinearity2 DNL 12-Bit Mode −0.99 +2.5 LSB Guaranteed monotonic, 1 LSB = 2.2 V/(212 − 1) 6-Bit Mode −0.5 +0.5 LSB Guaranteed monotonic, 1 LSB = 2.2 V/26 Offset Error2 −7 ±3.9 +7 mV VBIAS0/VZERO0 in 12-bit mode; 2.5 V internal reference, DAC output code = 0x000; Target 0x000 code = 200 mV −2 ±0.2 +2.6 mV Differential offset voltage of VBIAS0 referred to VZERO0 Drift over Temperature ±5 μV/°C VBIAS0 or VZERO0 referred to AGND Differential Offset VBIAS0 to VZERO0 ≈ 0 V2 4 μV/°C Differential offset voltage of VBIAS0 referred to VZERO0; −40°C to +60°C range; LPDACDAT0 = 0x1A680 Differential Offset VBIAS0 to VZERO0 ≈ ±600 mV2 10 μV/°C Differential offset voltage of VBIAS0 referred to VZERO0, −40°C to +60°C range; LPDACDAT0 = 0x1AAE0 Gain Error2 ±0.2 ±0.5 % 12-bit mode, DAC code = 0xFFF with target voltage of 2.4 V Drift over Temperature 10 ppm/°C Using internal low power reference Analog Outputs Output Voltage Range2 LSB size = 2.2/(212 − 1); the input common-mode voltage of the low power potentiostat amplifier and low power TIA = AVDD − 600 mV 12-Bit Outputs 0.2 2.4 V AVDD ≥ 2.8 V 6-Bit Outputs LSB size is 2.2/26; the input common-mode voltage of the low power potentiostat amplifier and low power TIA = AVDD − 600 mV 0.2 2.366 V AVDD ≥ 2.8 V 0.2 2.3 V AVDD < 2.8V AVDD to VBIAS0/VZERO0 Headroom Voltage2 400 mV A minimum headroom between AVDD and VBIAS0/VZERO0 output voltage, increases to 600 mV if connected to low power TIA or low power low power potentiostat amplifiers Output Impedance2 1.65 MΩ DAC AC Characteristics Output Settling Time 1.5 sec Settled to ±2 LSB12 with 0.1 μF load for ¼ of full scale to ¾ of full scale Output Settling Time 500 μs Settled to ±2 LSB12; no load Glitch Energy ±5 nV/sec 1 LSB change when the maximum number of bits changes simultaneously in the LPDACDAT0 register; switch to external capacitors on VBIAS0/VZERO0 opened; no capacitors on CE0 and RC0_x pins EXCITATION DAC/PGA/ RECONSTRUCTION FILTER Use HSDACDAT register range of 0x200 to 0xE00; specified for gain = 2 (HSDACCON Bit 12 and Bit 0 = 0); for gain = 0.05 (HSDACCON Bit 12 and Bit 0 = 1) DAC Common-Mode Voltage Range2 0.2 AVDD − 0.6 V Set by the negative node of the excitation amplifier Resolution2 12 Bits 1 LSB = 293 μV × programmable gain Differential Nonlinearity2 DNL −0.99 +1.25 LSB Gain = 2 ±7 ±20 LSB Gain = 0.05 Integral Nonlinearity2 INL ±2 ±3 LSB Gain = 2 ±8 ±20 LSB Gain = 0.05 ±0.6 ±3 LSB Gain = 2 Data Sheet AD5940/AD5941 SPECIFICATIONS analog.com Rev. G | 13 of 142 Table 1. (Continued) Parameter Symbol Min Typ Max Unit Test Conditions/Comments Full-Scale Error2, 14 Positive 600 630 650 mV Gain = 2, DAC code = 0xE00 15.1 mV Gain = 0.05, DAC code = 0xE00 Negative −660 −640 −620 mV Gain = 2, DAC code = 0x200 −15.1 mV Gain = 0.05, DAC code = 0x200 Gain Error Drift over Temperature2 Gain = 2 11.5 μV/°C Gain = 0.05 0.33 μV/°C Offset Error (Midscale) Measured at an output of the excitation loop across RCAL; DAC code = 0x800 ±25 mV Gain = 2 ±0.5 mV Gain = 0.05 Offset Error Drift over Temperature Gain = 2 40 μV/°C Gain = 0.05 5 μV/°C DC PSRR2 70 dB DC variation due to AVDD supply changes PGA, Programmable Gain2 0.05 2 Gain Reconstruction Filter 3 dB Corner Frequency Accuracy ±5 % Programmable to 50 kHz, 100 kHz, and 250 kHz Allowed External Load Capacitance2 SE0, DE0, AINx, and RCAL0/RCAL1 pins <80 kHz (Low Power Mode) 100 pF >80 kHz (High Power Mode) 80 pF Overcurrent Limit Protection2 15 mA Amplifier attempts to limit the source/sink current to this value via the internal clamp Allowed Duration of Overcurrent Limit2 5 sec Allowed Frequency of Overcurrent Conditions2 1 Per hour Short-Circuit Protection2 10 mA When amplifier output is shorted to ground SWITCH MATRIX Switches on analog front end before ADC mux On Resistance2 RON Characterized with a voltage sweep from 0 V to AVDD; production tested at 2.8 V Current Carrying Switches 40 80 Ω Tx/TR1 switches, except T5 and T7 30 52 Ω T5 and T7 switches only 35 70 Ω Dx/DR0 switches Noncurrent Carrying Switches 1 5 kΩ Nx/Nxx and Px/Pxx switches DC Off Leakage 370 pA Analog input pin used for test driven to 0.3 V DC On Leakage2 530 2000 pA Analog input pin used for test driven to 0.3 V TEMPERATURE SENSOR Resolution 0.3 °C Accuracy ±2 °C Measurement taken immediately after exiting hibernate mode; user single-point calibration required POWER-ON RESET POR Refers to voltage on DVDD pin POR Trip Level Power-On 1.59 1.62 1.72 V Power-Down2 1.799 1.8 1.801 V POR Hysteresis1 10 mV Delay Between POR Power-On and Power-Down Trip Levels2 110 ms After DVDD passes POR power-on trip level, DVDD must remain at or above power-down level for this period Data Sheet AD5940/AD5941 SPECIFICATIONS analog.com Rev. G | 14 of 142 Table 1. (Continued) Parameter Symbol Min Typ Max Unit Test Conditions/Comments External Reset Minimum Pulse Width2 1 μs Minimum pulse width required on external reset pin to trigger a reset WAKE-UP TIMER2 Shortest Duration 31.25 μs Longest Duration 32 sec DIGITAL INPUTS Input Leakage Current2 Logic 1 GPIO 1 ±5 nA Voltage input high (VIH ) = IOVDD, pull-up resistor disabled Logic 0 GPIO 1 ±10 nA Voltage input low (VIL ) = 0 V, pull-up resistor disabled Input Capacitance2 10 pF Pin Capacitance2 XTALI 10 pF XTALO 10 pF GPIO Input Voltage Low VINL 0.25 × IOVDD V High VINH 0.57 ×IOVDD V XTALI Input Voltage2 Low VINL 1.1 V High VINH 1.7 V LOGIC INPUTS GPIO Input Voltage2 Low VINL 0.25 × IOVDD V High VINH 0.57 × IOVDD V Pull-Up Current2 30 130 μA Input voltage (VIN) = 0 V; DVDD = 3.6 V LOGIC OUTPUTS All digital outputs, excluding XTALO GPIO Output Voltage2,15 High VOH IOVDD − 0.4 V Source current (ISOURCE) = 2 mA Low VOL 0.35 V Sink current (ISINK) = 2 mA Pull-Down Current2 30 100 μA VIN = 3.3 V GPIO Short-Circuit Current 11.5 mA PIN SUPPLY RANGE FOR 1.8 V INPUT/ OUTPUT2 1.62 1.8 1.98 V Input Voltage Low VINL 0.3 × pin supply V High VINH 0.7 × pin supply V Output Voltage Low VOL 0.45 V ISINK = 1.0 mA High VOH Pin supply − 0.5 V ISOURCE = 1.0 mA OSCILLATORS Internal System Oscillator 16 or 32 MHz Data Sheet AD5940/AD5941 SPECIFICATIONS analog.com Rev. G | 15 of 142 Table 1. (Continued) Parameter Symbol Min Typ Max Unit Test Conditions/Comments Accuracy 16 MHz Mode ±0.5 ±3 % 32 MHz Mode ±0.5 ±3 % External Crystal Oscillator 16 32 MHz Can be selected in place of the internal oscillator Logic Inputs, XTALI Only Input Low Voltage VINL 1.1 V Input High Voltage VINH 1.7 V XTALI Input Capacitance 8 pF XTALO Output Capacitance 8 pF 32 kHz Internal Oscillators 32.768 kHz Used for watchdog16 timers and wake-up timers Accuracy ±5 ±15 % EXTERNAL INTERRUPTS Pulse Width2 Level Triggered 7 ns Edge Triggered 1 ns POWER REQUIREMENTS Power Supply Voltage Range (AVDD to AGND, DVDD to DGND, and IOVDD to DGND) 2.8 3.3 3.6 V IOVDD17 1.62 1.8 1.98 V AVDD Current 0.56 0.74 mA Analog peripheral in idle mode Hibernate Mode 8.5 μA Only low power DAC, potentiostat amplifiers, low power reference, low power TIA, and 32 kHz oscillator active 6.52 μA Only low power DACs, potentiostat amplifier, low power reference, and 32 kHz oscillator active; potentiostat amplifier and low power TIA in half power mode 1.82 μA Lowest power mode; only wake-up timer active; all analog peripherals powered down Impedance Measurement Modes2 Impedance Spectroscopy Mode 9.1 mA When ac impedance engine, ADC and sequencer are active 50 kHz Impedance Measurement 106 μA 50 kHz excitation signal; DFT enabled with DFT sample number = 2048; 1 Hz output data rate (ODR) 100 Hz Impedance Measurement 65 μA When low power loop creates sine wave at 100 Hz and the receive channel and DFT engine is duty cycled, with DFT sample number = 16, gives 4 Hz ODR Additional Power Supply Currents2 ADC 1.5 mA ADC frequency (fADC) = 200 kSPS, ADC clock is 16 MHz 3.45 mA fADC = 400 kSPS, ADC clock is 32 MHz High Speed TIA 0.3 mA Low power mode 0.9 High power mode High Speed DAC Includes excitation amplifier and instrumentation amplifier 2.2 mA Low power mode 4.5 mA High power mode DFT Hardware Accelerator 550 μA Low Power Reference 1.65 μA Low Power DACs for VZERO0 and VBIAS0 2.3 μA Low power DAC powered up, excluding load current Low Power TIA and Potentiostat Amplifier 2 μA Per amplifier, normal mode 1 μA Per amplifier, half power mode Data Sheet AD5940/AD5941 SPECIFICATIONS analog.com Rev. G | 16 of 142 Table 1. (Continued) Parameter Symbol Min Typ Max Unit Test Conditions/Comments START-UP TIME Processor clock = 16 MHz AFE Wake-Up2 30 ms Wake-up time to allow communication on SPI bus ADC Wake-Up2 80 180 μs Time delay required on exiting hibernate mode before starting ADC conversions 1 VBIAS_CAP is only meant for internal biasing within the IC. 2 Guaranteed by design, not production tested. 3 Code distribution can be reduced if ADC output rate is reduced by using sinc2 filter option. 4 ADC offset and gain not calibrated for high power mode in production. User calibration can eliminate this error. 5 There is a correction factor of 1.835 V introduced to the ADC code to voltage conversion as a result of the calibration to the ADC. 6 A 1.835 V/1.82 V factor must be added while performing the calibration. 7 The 1.82 V reference is used to calibrate the ADC offset and gain. 8 If the ADC is calibrated and there is a hardware reset, the calibration registers are cleared to the default value. One way around this clear is to store the calibrated values in the MCU flash during factory calibration and load those values on power-up. 9 Noise can be reduced if ADC sample rate is reduced using the sinc2 filter. See Table 2 for ADC rms noise: digital filter settings. 10 The low power TIA gain resistor must be calibrated regularly because the resistor has a high temperature drift. 11 See Figure 7 for details. 12 See Figure 9 for details. 13 VBIAS0 can be used for sourcing the offset voltage to external amplifiers. 14 High speed DAC offset calibration can remove this error. See the High Speed DAC Calibration Options section for details. 15 Measured using the box method. 16 The watchdog can be turned off during system initialization. 17 IOVDD can optionally be powered from a 1.8 V supply rail. ADC RMS NOISE SPECIFICATIONS The internal 1.82 V reference is used for all measurements. Note that there is a correction factor of 1.835 V introduced to the ADC code to voltage conversion as a result of the ADC calibration. Although a 1.82 V reference is used to calibrate the ADC offset and gain, 1.835/1.82 factor is needed to be multiplied during the calibration. If the ADC is calibrated and there is a hardware reset, the calibration registers clear to the default value. The low power TIA gain resistor must be calibrated regularly because this resistor has a high temperature drift. ADC RMS Noise: Digital Filter Settings Table 2 provides the rms noise specifications for the ADC with different ADC digital filter settings. Table 2. ADC RMS Noise1 Update Rate (Hz) Sinc3 Oversampling Rate (OSR) Sinc2 OSR Gain = 1 rms Noise (μV) Gain = 1.5 rms Noise (μV) Gain = 2 rms Noise (μV) Gain = 4 rms Noise (μV) Gain = 9 rms Noise (μV) 200,000 4 Not applicable 72.43 49.732 37.83 18.93 8.62 9090 4 22 29.29 19.59 10.4 6.687 4.42 900 5 178 24.0 17.11 12.832 6.416 1.018 1 Noise can be reduced if ADC sample rate is reduced using the sinc2 filter. ADC RMS Noise: Peak-to-Peak Effective Bits Table 3 provides the rms and peak-to-peak effective bits based on the noise results in Table 2 for various PGA gain settings (peak-to-peak effective bits results are shown in parentheses). To calculate the rms bits, use the following equation: Data Sheet AD5940/AD5941 SPECIFICATIONS analog.com Rev. G | 17 of 142 log2 ((2 × Input Range)/RMS Noise) (1) where: Input Range is the input voltage range to the ADC. RMS Noise is the rms of the noise. To calculate the peak-to-peak effective bits, use the following equation: log2 ((2 × Input Range)/(6.6 × RMS Noise)) (2) Table 3. ADC Effective Bits Based on RMS Noise Update Rate (Hz) Sinc3 OSR Sinc2 OSR Gain = 1 Gain = 1.5 Gain = 2 Gain = 4 Gain = 9 Settling Time1 Settling Time2 200,000 4 Not applicable 14.6 (11.9 p‑p) 15 (12.4 p-p) 14.95 (12.23 p‑p) 14.95 (12.23 p‑p) 14.9 (12.15 p‑p) 16.25 μs 16.25 μs 9090 4 22 15 (13.18 p‑p) 15 (13.8 p-p) 15 (14.09 p‑p) 15 (13.73 p‑p) 15 (13.15 p‑p) 236.25 μs 236.25 μs 900 5 178 15 (13.47 p‑p) 15 (13.96 p‑p) 15 (13.8 p‑p) 15 (13.79 p‑p) 15 (15 p-p) 2.245 ms 37 ms 1 Settling time except for 50 Hz and 60 Hz notch filter enables. 2 Settling time including 50 Hz and 60 Hz notch filter enables. SPI TIMING SPECIFICATIONS MOSI and MISO are launched on the falling edge of SCLK and sampled on the rising edge of SCLK by the host and the AD5940/AD5941, respectively. IOVDD = 2.8 V − 3.6 V and 1.8 V ±10%, unless otherwise noted. Table 4. Parameter Time Unit Description t1 190 ns maximum CS falling edge to MISO setup time t2 5 ns minimum CS low to SCLK setup time t3 40 ns minimum SCLK high time t4 40 ns minimum SCLK low time t5 80 ns minimum SCLK period t6 27 ns maximum SCLK falling edge to MISO delay t7 5 ns minimum MOSI to SCLK rising edge setup time t8 5 ns minimum MOSI to SCLK rising edge hold time t9 19 ns minimum SCLK falling edge to hold time CS t10 80 ns minimum CS high time tWK 22 μs typical AD5940/AD5941 wake-up time (not shown in Figure 3) SPI Timing Diagram Figure 3. SPI Interface Timing Diagram Data Sheet AD5940/AD5941 ABSOLUTE MAXIMUM RATINGS analog.com Rev. G | 18 of 142 Table 5. Parameter Rating AVDD to AGND −0.3 V to +3.9 V DVDD to DGND −0.3 V to +3.9 V IOVDD to DGND −0.3 V to +3.9 V Analog Input Voltage to AGND −0.3 V to AVDD +0.3 V Digital Input Voltage to DGND −0.3 V to DVDD +0.3 V Digital Output Voltage to DGND −0.3 V to DVDD +0.3 V AGND to DGND −0.3 V to +0.3 V Total GPIOx Pins Current Positive 0 mA to 30 mA Negative −30 mA to 0 mA Storage Temperature Range −65°C to +150°C Operating Temperature Range AD5940/AD5941 −40°C to +85°C AD5941W −40°C to +105°C Reflow Profile Moisture Sensitivity Level 3 (MSL3) J-STD 020E (JEDEC) Junction Temperature 150°C Electrostatic Discharge (ESD) Human Body Model (HBM) 4 kV Field Induced Charged Device Model (FICDM) 750 V Machine Model (MM) 100 V Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operat- ing conditions for extended periods may affect product reliability. THERMAL RESISTANCE Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Close attention to PCB thermal design is required. θJA is the natural convection junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. θJC is the junction to case thermal resistance. Table 6. Thermal Resistance Package Type1 θJA θJC Unit CB-56-3 33.0702 0.0642 °C/W CP-48-4 32.03 2.85 °C/W 1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal test board. See JEDEC JESD51. ESD CAUTION ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protec- tion circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. Data Sheet AD5940/AD5941 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS analog.com Rev. G | 19 of 142 Figure 4. AD5940 Pin Configuration Figure 5. AD5941 Pin Configuration Table 7. Pin Function Descriptions Pin No. Mnemonic Input/Output Supply Description AD5940 AD5941 A1 28 AFE4 Analog Uncommitted Analog Front End Pin 4. A2 27 AFE3 Analog Uncommitted Analog Front End Pin 3. A3 37 AIN2 Analog Uncommitted Analog Input Pin 2. This pin connects to the switch matrix. A4 41 AVDD Supply Analog Circuit Power. Short this pin to Pin F2 (AVDD). A5 43 VREF_1V82 Analog 1.82 V Reference Decoupling Capacitor Pin. The recommended capacitor value is 4.7 μF. A6 45 SE0 Analog Sense Electrode Input Pin for High Bandwidth and Low Bandwidth Loop Circuits. This pin connects to the switch matrix. Data Sheet AD5940/AD5941 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS analog.com Rev. G | 20 of 142 Table 7. Pin Function Descriptions (Continued) Pin No. Mnemonic Input/Output Supply Description AD5940 AD5941 A7 47 CE0 Analog Counter Electrode Input Pin for High Bandwidth and Low Bandwidth Loop Circuits. This pin connects to the switch matrix. A8 48 RE0 Analog Reference Electrode Input Pin for High Bandwidth and Low Bandwidth Loop Circuits. This pin connects to positive node of the switch matrix. B1 33 RCAL1 Analog Terminal B of Calibration Resistor (RCAL). Connect this pin to the switch matrix. B2 34 AFE1 Analog Uncommitted Analog Front End Pin 1. B3 38 AIN1 Analog Uncommitted Analog Input Pin 1. This pin connects to the switch matrix. B4 40 AIN4/LPF0 Analog Uncommitted Analog Input Pin 4 (AIN4). Low Power TIA Output Low-Pass Filter Capacitor Pin (LPF0). B5 36 AIN3/BUF_VREF1V8 Analog Uncommitted Analog Input Pin 3 (AIN3). 1.82 V Reference Buffered Output (BUF_VREF1V8). This pin connects to the switch matrix. B6 46 DE0 Analog Analog Input Pin. This pin connects to the input and output of the high speed TIA. B7 9 VZERO0 Analog Low Power, Dual-Output DAC, Zero Voltage Output Pin. Connect a 100 nF capacitor to this pin. B8 2 RC0_1 Analog Low Power TIA Reconstruction Filter 0 Feedback Pin 1. This pin is connected to the output of the low power TIA. C1 32 RCAL0 Analog Terminal A of Calibration Resistor. Connect this pin to the switch matrix. C2 35 AFE2 Analog Uncommitted Analog Front End Pin 2. C3, D3 N/A DNC Analog Do Not Connect. Do not connect to this pin. C4 42 AGND Ground Analog Ground. Short this pin to Pin E3 (AGND). C5 N/A AIN6 Analog Uncommitted Analog Input Pin 6. C6 1 RC0_2 Analog Low Power TIA Reconstruction Filter 0 Pin 2. This pin can be left open (optional). C7 8 VBIAS0 Analog Low Power, Dual-Output DAC Bias Voltage Output Pin. Connect a 100 nF capacitor to this pin. C8 3 RC0_0 Analog Low Power TIA Feedback Pin. This pin is connected to the feedback of the low power TIA. D1 31 VBIAS_CAP Analog ADC 1.11 V Input Bias Decoupling Capacitor Pin. The recommended capacitor value is 470 nF. D2 39 AIN0 Analog Uncommitted Analog Input Pin 0. This pin connects to the switch matrix. D4, G1, G8 7, 10, 24 DNC Not applicable Do Not Connect. Do not connect to this pin. D5 44 AGND_REF Ground Analog Reference Ground. D6 20 GPIO1 Digital input/output General-Purpose Input/Output Pin 1. D7 4 VREF_2V5 Analog 2.5 V Analog Reference Decoupling Capacitor Pin. Connect a 470 nF capacitor to this pin. D8 5 AVDD_REG Supply Analog Regulator Decoupling Capacitor Pin. E1 21 GPIO2 Digital input/output General-Purpose Input/Output Pin 2. E2 N/A GPIO3 Digital input/output General-Purpose Input/Output Pin 3. E3 29 AGND Ground Analog Ground. Short this pin to Pin C4. E4 to E6 13, 23, 25 DGND Ground Digital Ground. E7 17 MOSI Digital input SPI Initiator Output, Target Input. E8 18 MISO Digital output SPI Initiator Input Target Output. F1 22 RESET Digital input Reset Pin, Active Low. F2 30 AVDD Supply Analog 3.3 V Circuit Power. F3 6 DVDD Supply Digital Circuit Power. F4 N/A GPIO6 Digital input/output General-Purpose Input/Output Pin 6. F5 19 GPIO0 Digital input/output General-Purpose Input/Output Pin 0. F6 N/A GPIO5 Digital input/output General-Purpose Input/Output Pin 5. F7 15 CS Digital input/output SPI Chip Select. Data Sheet AD5940/AD5941 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS analog.com Rev. G | 21 of 142 Table 7. Pin Function Descriptions (Continued) Pin No. Mnemonic Input/Output Supply Description AD5940 AD5941 F8 16 SCLK Digital input SPI Clock. G2 26 IOVDD Supply Digital Input/Output Supply Pin. DVDD (Pin F3) must be driven before IOVDD is enabled. G3 14 DVDD_REG_1V8 Analog 1.8 V Digital Regulator Decoupling Capacitor Pin. Connect a 470 nF capacitor to this pin. G4 N/A GPIO7 Digital input/output General-Purpose Input/Output Pin 7. G5 11 XTALI Digital Input 16 MHz External Crystal Input Pin. G6 12 XTALO Digital output 16 MHz External Crystal Output Pin. G7 N/A GPIO4 Digital input/output General-Purpose Input/Output Pin 4. Data Sheet AD5940/AD5941 TYPICAL PERFORMANCE CHARACTERISTICS analog.com Rev. G | 22 of 142 Figure 6. Magnitude vs. Frequency, ADC 1.82 V Voltage Reference AC PSRR Figure 7. Magnitude vs. Frequency, Low Power 2.5 V Voltage Reference AC PSRR Figure 8. Low Power Reference (2.5 V) vs. Supply Voltage, DC PSRR Figure 9. High Power Reference vs. Supply Voltage, 1.11 V Voltage Reference DC PSRR Figure 10. High Power Reference vs. Supply Voltage, ADC 1.82 V Voltage Reference DC PSRR Figure 11. Low Power Potentiostat Input Bias Current (IBIAS) vs. RE0 Pin Voltage Data Sheet AD5940/AD5941 TYPICAL PERFORMANCE CHARACTERISTICS analog.com Rev. G | 23 of 142 Figure 12. Low Power TIA Input Bias Current (IBIAS) vs. Temperature Figure 13. Low Power Potentiostat Input Bias Current vs. Temperature Figure 14. Electrodermal Activity (EDA) Measurement Relative Error vs. Impedance Figure 15. VREF 1.8 V Lifetime Drift Figure 16. VREF 2.5 V Lifetime Drift Data Sheet AD5940/AD5941 TYPICAL PERFORMANCE CHARACTERISTICS analog.com Rev. G | 24 of 142 REFERENCE TEST CIRCUIT Figure 17. High Speed Loop Connected to Sensor (R1, R2, and R3), C1 and C2 Represent Capacitance to Ground Data Sheet AD5940/AD5941 THEORY OF OPERATION analog.com Rev. G | 25 of 142 The main blocks of the AD5940/AD5941 are as follows: ► Low power, dual-output, string DAC used to set the sensor bias voltage and low frequency excitation. Supports chronoampero- metric and voltammetry electrochemical techniques. ► Low power potentiostat that applies the bias voltage to the sensor. ► Low power TIA that performs low bandwidth current measure- ments. ► High speed DAC and amplifier designed to generate excitation signals for impedance measurements up to 200 kHz. ► High speed TIA that supports wider signal bandwidth measure- ments. ► High performance ADC circuit (see the High Performance ADC Circuit section). ► Programmable switch matrix. The input switching of the AD5940/ AD5941 allows full configurability in the connections of the exter- nal sensors (see the Programmable Switch Matrix section). ► Programmable sequencer (see the Sequencer section). ► SPI interface. ► Waveform generator designed to create sinusoid and trapezoid waveforms up to 200 kHz (see the Waveform Generator section). ► Interrupt sources that output to a GPIOx pin to alert the host controller that an interrupt event occurred (see the Interrupts section). ► Digital inputs/outputs (see the Digital Inputs/Outputs section). CONFIGURATION REGISTERS Table 8. Configuration Registers Summary Address Name Description Reset Access 0x00002000 AFECON AFE configuration register 0x00080000 R/W 0x000022F0 PMBW Power modes configuration register 0x00088800 R/W Configuration Register—AFECON Address 0x00002000, Reset: 0x00080000, Name: AFECON Table 9. Bit Descriptions for AFECON Register Bits Bit Name Settings Description Reset Access [31:22] Reserved Reserved. 0x0 R 21 DACBUFEN Enables the dc DAC buffer. This bit enables the buffer for the high impedance output of the dc DAC. 0x0 R/W 0 Disables the dc DAC buffer. 1 Enables the dc DAC buffer. 20 DACREFEN High speed DAC reference enable. 0x0 R/W 0 Reference disable. Clear to 0 to disable the high speed DAC reference. 1 Reference enable. Set to 1 to enable the high speed DAC reference. 19 Reserved Reserved. Always set this to 1. 0x1 R/W [18:17] Reserved Reserved. 0x0 R 16 SINC2EN ADC output 50 Hz/60 Hz notch filter enable. This bit enables the 50 Hz/60 Hz supply rejection filter. 0x0 R/W 0 Supply rejection filter disabled. Disables sinc2 (50 Hz/60 Hz digital filter). Disable this bit for impedance measurements. 1 Supply rejection filter enabled. Enables sinc2 (50 Hz/60 Hz digital filter). 15 DFTEN DFT hardware accelerator enable. This bit enables the DFT hardware acceleration block. 0x0 R/W 0 DFT hardware accelerator disabled. 1 DFT hardware accelerator enabled. 14 WAVEGENEN Waveform generator enable. This bit enables the waveform generator. 0x0 R/W 0 Waveform generator disabled. The waveform generator includes a sinusoid wave and a trapezoid wave. 1 Waveform generator enabled. Data Sheet AD5940/AD5941 THEORY OF OPERATION analog.com Rev. G | 26 of 142 Table 9. Bit Descriptions for AFECON Register (Continued) Bits Bit Name Settings Description Reset Access 13 TEMPCONVEN ADC temperature sensor convert enable. This bit enables the temperature reading. If this bit is set to 1, a temperature reading is initiated. When the temperature conversion is complete, the result available in the TEMPSENSDAT register. 0x0 R/W 0 Temperature reading disabled. 1 Temperature reading enabled. 12 TEMPSENSEN ADC temperature sensor channel enable. This bit enables the temperature sensor. 0x0 R/W 0 Temperature sensor disabled. The temperature sensor is powered down. 1 Temperature sensor enabled. The temperature sensor is powered up. Temperature readings are not performed unless TEMPCONVEN = 1. 11 TIAEN High speed TIA enable. This bit enables the high speed TIA. 0x0 R/W 0 High speed TIA disabled. 1 High speed TIA enabled. 10 INAMPEN Excitation instrumentation amplifier enable. This bit enables the instrumentation amplifier. 0x0 R/W 0 Programmable instrumentation amplifier disabled. 1 Programmable instrumentation amplifier enabled. 9 EXBUFEN Excitation buffer enable. This bit enables the excitation buffer to drive the resistance being measured. 0x0 R/W 0 Excitation buffer disabled. 1 Excitation buffer enabled. 8 ADCCONVEN ADC conversion start enable. 0x0 R/W 0 ADC idle. The ADC is powered on, but is not converting. 1 ADC conversions enabled. 7 ADCEN ADC power enable. This bit enables the ADC. 0x0 R/W 0 ADC disabled. The ADC is powered off. 1 ADC enabled. The ADC is powered on. The ADCCONVEN bit must be set to 1 to start conversions. 6 DACEN High speed DAC enable. This bit enables the high speed DAC, the corresponding reconstruction filter, and the attenuator. This bit only enables the analog block and does not include the DAC waveform generator. 0x0 R/W 0 High speed DAC disabled. 1 High speed DAC enabled. 5 HSREFDIS High speed reference disable. This bit is the power-down signal of the high power reference. Set this bit to 1 to power down the reference. 0x0 R/W 0 High power reference enabled. 1 High power reference disabled. [4:0] Reserved Reserved. 0x0 R Power Mode Configuration Register—PMBW Address 0x000022F0, Reset: 0x00088800, Name: PMBW The power mode configuration register, PMBW, configures the high and low power system modes for the high speed DAC and ADC circuits. Table 10. Bit Descriptions for PMBW Register Bits Bit Name Settings Description Reset Access [31:4] Reserved Reserved. 0x8880 R Data Sheet AD5940/AD5941 THEORY OF OPERATION analog.com Rev. G | 27 of 142 Table 10. Bit Descriptions for PMBW Register (Continued) Bits Bit Name Settings Description Reset Access [3:2] SYSBW System bandwidth configure. The reconstruction filter of the high speed DAC and the antialias filter bandwidth configuration of the ADC are configured by a single register. 0x0 R/W 00 No action for system configuration. The reconstruction filter and antialias filter are automatically configured according to the waveform generator frequency. Waveform generator frequency = 50 kHz, reconstruction filter and antialias filter cutoff = 5 kHz. Waveform generator frequency = 50 kHz to 100 kHz, reconstruction filter and antialias filter cutoff = 100 kHz. Waveform generator frequency = 100 kHz to 200 kHz, reconstruction filter and antialias filter cutoff = 250 kHz. 01 Sets cutoff frequency to 50 kHz, −3 dB bandwidth. 10 Sets cutoff frequency to 100 kHz, −3 dB bandwidth. 11 Sets cutoff frequency to 250 kHz, −3 dB bandwidth. 1 Reserved Reserved. 0x0 R 0 SYSHS Sets the high speed DAC and ADC in high power mode. 0x0 R/W 0 Low power mode. Clear this bit for impedance measurements of <80 kHz. 1 High speed mode. Set this bit for impedance measurements of >80 kHz. Data Sheet AD5940/AD5941 SILICON IDENTIFICATION analog.com Rev. G | 28 of 142 The AD5940/AD5941 contains a chip ID register and a hardware revision register. These registers can be read by software to allow users to deter- mine the revision of the silicon currently in use. ADIID is always equal to 0x4144. The CHIPID register contains the device identifier (Bits[15:4] and silicon revision number (Bits[3:0]). The device identi- fier changes with silicon revision. IDENTIFICATION REGISTERS Table 11. Identification Registers Summary Address Name Description Reset Access 0x00000400 ADIID Analog Devices Inc., identification register 0x4144 R 0x00000404 CHIPID Chip identification register 0x5502 R Analog Devices, Inc., Identification Register—ADIID Address 0x00000400, Reset: 0x4144, Name: ADIID Table 12. Bit Descriptions for ADIID Register Bits Bit Name Settings Description Reset Access [15:0] ADIID Analog Devices identifier. Always equal to 0x4144. 0x4144 R Chip Identification Register—CHIPID Address 0x00000404, Reset: 0x5502, Name: CHIPID Table 13. Bit Descriptions for CHIPID Register Bits Bit Name Settings Description Reset Access [15:4] Part ID Device identifier 0x550 R [3:0] Revision Silicon revision number 0x3 R Data Sheet AD5940/AD5941 SYSTEM INITIALIZATION analog.com Rev. G | 29 of 142 To ensure proper operation of the AD5940/AD5941 device, an initialization sequence must be implemented after each device reset. Table 14 shows the required registers that must be written to, as well as the data that must be written to the register. If this initialization sequence is not followed correctly, the device does not function properly. Table 14. AD5940/AD5941 Initialization Register Address Data 0x0908 0x02C9 0x0C08 0x206C Table 14. AD5940/AD5941 Initialization (Continued) Register Address Data 0x21F0 0x0010 0x0410 0x02C9 0x0A28 0x0009 0x238C 0x0104 0x0A04 0x4859 0x0A04 0xF27B 0x0A00 0x8009 0x22F0 0x0000 Data Sheet AD5940/AD5941 LOW POWER DAC analog.com Rev. G | 30 of 142 The ultra low power DAC is a dual output string DAC that sets the bias voltage of the sensor. There are two output resolution formats: 12-bit resolution (VBIAS0) and 6‑bit resolution (VZERO0). In normal operation, the 12-bit output sets the voltage on the reference electrode and counter electrode pins, RE0 and CE0, via the potentiostat circuit. This voltage can also be sent to the VBIAS0 pin by configuring the SW12 switch (see Figure 22). An external filtering capacitor can be connected to the VBIAS0 pin. The 6-bit output sets the voltage to the positive low power TIA inter- nal node that connects to the ADC mux, LPTIA_P. The voltage on the sense electrode is equal to this pin. This voltage is referred to as VZERO0 and can be connected to the VZERO0 pin by configuring the SW13 switch (see Figure 22). In diagnostic mode, the VZERO0 output can also be connected to the high speed TIA by setting Bit 5 in the LPDACCON0 register to 1. The low power DAC reference source is a low power, 2.5 V reference. The low power DACs are made up of two 6-bit string DACs. The main 6-bit string DAC provides the VZERO0 DAC output, and is made up of 63 resistors. Each resistor is the same value. The main 6-bit string with the 6-bit subDAC provides the VBIAS0 DAC output. In 12-bit mode, the MSBs select a resistor from the main string DAC. The top end of this resistor is selected as the top of the 6-bit subDAC, and the bottom end of the selected resistor is connected to the bottom of the 6-bit subDAC string, as shown in Figure 18. The resistor matching between the 12-bit and 6-bit DACs means 64 LSB12 (VBIAS0) is equal to one LSB6 (VZERO0). The output voltage range is not rail to rail. Rather, it ranges from 0.2 V to 2.4 V for the 12-bit output of the low power DAC. Therefore, the LSB value of the 12-bit output (12-BIT_ DAC_LSB) is 12 ‐ BIT_DAC_LSB = 2 . 2 V 212 − 1 = 537 . 2 μ V (3) The 6-bit output range is from 0.2 V to 2.366 V. This range is not 0.2 V to 2.4 V because there is a voltage drop across R1 in the resistor string (see Figure 18). The LSB value of the 6-bit output (6-BIT_DAC_LSB) is 6-BIT_DAC_LSB = 12-BIT_DAC_LSB × 64 = 34.38 mV (4) To set the output voltage of the 12-bit DAC, write to LPDACDAT0, Bits[11:0]. To set the 6-bit DAC output voltage, write to LPDAC- DAT0, Bits[17:12]. If the system clock is 16 MHz, LPDACDAT0 takes 10 clock cycles to update. If system clock is 32 kHz, LPDACDAT0 takes one clock cycle to update. Take these values into consideration when using the sequencer. The following code demonstrates how to correctly set the LPDAC- DAT0 value: SEQ_WR(REG_AFE_LPDACDAT0, 0x1234); SEQ_WAIT(10); // Wait 10 clocks for LPDACDAT0 to update SEQ_SLP(); Optionally, the waveform generator described in the Waveform Generator section can be used as the DAC codes source for the low power DAC. When using the waveform generator with the low power DAC, ensure that the settling time specification of the low power DAC is not violated. The system clock source must be the 32 kHz oscillator. This feature is provided for ultra low power, always on, low frequency measurements, such as skin impedance measurements where the excitation signal is approximately 100 Hz and system power consumption needs to be <100 μA. LOW POWER DAC SWITCH OPTIONS There are a number of switch options available that allow the user to configure the low power DAC for various modes of opera- tion. These switches facilitate different use cases, such as electro- chemical impedance spectroscopy. Figure 22 shows the available switches, labeled SW0 to SW4. These switches are controlled either automatically via Bit 5 in the LPDACCON0 register, or individ- ually via the LPDACSW0 register When LPDACCON0, Bit 5, is cleared, the switches are configured for normal mode. The SW2 switch and the SW3 switch are closed and the SW0, SW1, and SW4 switches are open. When LPDAC- CON0, Bit 5, is set, the switches are configured for diagnostic mode. The SW0 switch and the SW4 switch are closed and the remaining switches are open. This feature is designed for electro- chemical use cases, such as continuous glucose measurement where, in normal mode, the low power TIA measures the sense electrode. Then, in diagnostic mode, the high speed TIA measures the sense electrode. By switching the VZERO0 voltage output from the low power TIA to the high speed TIA, the effective bias on the sensor, VBIAS0 − VZERO0, is unaffected. Using the high speed TIA facilitates high bandwidth measurements, such as impedance, ramp, and cyclic voltammetry. Use the LPDACSW0 register to control the switches individually. LPDACSW0, Bit 5, must be set to 1. Then, each switch can be individually controlled via LPDACSW0, Bits[4:0]. Data Sheet AD5940/AD5941 LOW POWER DAC analog.com Rev. G | 31 of 142 Figure 18. Low Power DAC Resistor String RELATIONSHIP BETWEEN THE 12-BIT AND 6- BIT OUTPUTS The 12-bit and 6-bit outputs are mostly independent. However, the selected 12-bit value does have a loading effect on the 6-bit output that must be compensated for in user code, particularly when the 12-bit output level is greater than the 6-bit output. When the 12-bit output is less than the 6-bit output, 12-Bit DAC Output Voltage = 0.2 V + (LPDACDAT0, Bits[11:0] × 12-BIT_LSB_DAC) (5) 6-Bit DAC Output Voltage = 0.2 V + (LPDACDAT0, Bits[17:12] × 6-BIT_LSB_DAC) (6) When the 12-bit output is ≥ the 6-bit output, 12-Bit DAC Output Voltage = 0.2 V + (LPDACDAT0, Bits[11:0] × 12-BIT_LSB_DAC) – 12-BIT_LSB_DAC (7) 6-Bit DAC Output Voltage = 0.2 V + (LPDACDAT0, Bits[17:12] × 6-BIT_LSB_DAC) (8) Therefore, in user code, it is recommended to add the following: 12BITCODE = LPDACDAT0 [11:0]; 6BITCODE = LPDACDAT0 [17:12]; if (12BITCODE > (6BITCODE *64)) LPDACDAT [11:0] = (12BITCODE – 1); This code ensures that the 12-bit output voltage is equal to the 6-bit output voltage when LPDACDAT0, Bits[11:0] = 64 × LPDACDAT0, Bits[17:12]. LOW POWER DAC USE CASES Electrochemical Amperometric Measurement In an electrochemical measurement, the 12-bit output sets the voltage on the reference electrode pin via the potentiostat circuit shown in Figure 19. The voltage on the CE0 pin and RE0 pin is referred to as VBIAS0. The 6-bit output sets the bias voltage on the LPTIA_P node; this output sets the voltage on the sense electrode pin, SE0. This voltage is referred to as VZERO0. The bias voltage on the sensor effectively becomes the difference between the 12-bit output and the 6-bit output. Figure 19. Electrochemical Standard Configuration Data Sheet AD5940/AD5941 LOW POWER DAC analog.com Rev. G | 32 of 142 Electrochemical Impedance Spectroscopy In many electrochemical applications, there is significant value in carrying out a diagnostic measurement. A typical diagnostic technique is to carry out an impedance measurement on the sensor. For some sensor types, the dc bias on the sensor must be maintained during the impedance measurement. The AD5940/ AD5941 facilitates this dc bias. To perform this measurement, set LPDACCON0, Bit 5 = 1. VZERO0 voltage is set to the input of the high speed TIA and the high speed DAC generates an ac signal. The level of the ac signal is set via the VBIAS0 voltage output of the low power DAC, and the voltage on SE0 is maintained by VZERO0 voltage. The high speed DAC dc buffers must also be enabled by setting AFECON, Bit 21. Low Power DAC in 4-Wire Isolated Impedance Measurements For 4-wire isolated impedance measurements, such as body impe- dance measurements, a high frequency sinusoidal waveform is applied to the sensor via the high speed DAC. A common-mode voltage is set across the sensor using the low power DAC 6-bit output voltage, VZERO, and the low power TIA. This configuration sets the common-mode voltage between AIN2 and AIN3 (see Figure 20). To enable this common-mode voltage setup, SWMUX, Bit 3, must be set to 1. The VBIAS0 voltage output of the low power DAC also sets the common-mode voltage for the high speed DAC excitation buffer. Figure 20. Low Power DACs Used in a 4-Wire Impedance Measurement (HSTIA_P = Positive Output of High Speed TIA) LOW POWER DAC CIRCUIT REGISTERS Table 15. Low Power TIA and Low Power DAC Registers Summary Address Name Description Reset Access 0x00002128 LPDACCON0 Low power DAC configuration register 0x00000002 R/W 0x00002124 LPDACSW0 Low power DAC switch control register 0x00000000 R/W 0x00002050 LPREFBUFCON Low power reference configuration register 0x00000000 R/W 0x0000235C SWMUX Common-mode switch mux select register 0x00000000 R/W 0x00002120 LPDACDAT0 Low power DAC data output register 0x00000000 R/W LPDACCON0 Register—LPDACCON0 Address 0x00002128, Reset: 0x00000002, Name: LPDACCON0 Table 16. Bit Descriptions for LPDACCON0 Register Bits Bit Name Settings Description Reset Access [31:7] Reserved Reserved. 0x0 R 6 WAVETYPE Low power DAC data source. This bit determines the DAC waveform type. 0x0 R/W 0 Direct from LPDACDAT0. 1 Waveform generator. Data Sheet AD5940/AD5941 LOW POWER DAC analog.com Rev. G | 33 of 142 Table 16. Bit Descriptions for LPDACCON0 Register (Continued) Bits Bit Name Settings Description Reset Access 5 DACMDE Low power DAC switch settings. This bit is the control bit for the low power DAC output switches. 0x0 R/W 0 Low power DAC switches set for normal mode (default). Clear this bit to 0 for normal output switch operation. See the Low Power DAC section for more information. 1 Low power DAC switches set for diagnostic mode. Set this bit to 1 for diagnostic mode switch settings. See the Low Power DAC section for more information. 4 VZEROMUX VZERO0 voltage mux select. This bit selects the DAC output that connects to the VZERO0 node. Ensure that the same value is written to the VBIASMUX bit. 0x0 R/W 0 VZERO0, 6-bit (default). Clear this bit to 0 for the VZERO0 voltage output to be 6-bit. 1 VZERO0, voltage 12-bit. Set this bit to 1 for the VZERO0 voltage output to be 12-bit. 3 VBIASMUX VBIAS0 voltage mux select. This bit selects the low power DAC output that connects to the VBIAS0 node. Ensure that the same value is written to the VZEROMUX bit. 0x0 R/W 0 Output, 12-bit (default). The 12-bit DAC is connected to VBIAS0 voltage. 1 Output, 6-bit. The 6-bit DAC is connected to VBIAS0 voltage. 2 REFSEL Low power DAC reference select. 0x0 R/W 0 Selects the low power 2.5 V reference as the low power DAC reference source. 1 Selects AVDD as the low power DAC reference source. 1 PWDEN Low power DAC power-down. This bit powers down the control bit for the low power DAC. 0x1 R/W 0 Low Power DAC powered on. Clear this bit to 0 to power on the low power DAC. 1 Low Power DAC powered off (default). Powers down the low power DAC and opens all switches on the low power DAC output. 0 RSTEN Enable writes to low power DAC. Enables writes to LPDACDAT0 register. 0x0 R/W 0 Disables low power DAC writes (default). If this bit is cleared to 0, LPDACDAT0 is always 0. Writes to LPDACDAT0 are disabled. 1 Enables low power DAC writes. Set this bit to 1 to enable writes to LPDACDAT0. Low Power DAC Switch Control Register—LPDACSW0 Address 0x00002124, Reset: 0x00000000, Name: LPDACSW0 Table 17. Bit Descriptions for LPDACSW0 Register Bits Bit Name Settings Description Reset Access [31:6] Reserved Reserved. 0x0 R 5 LPMODEDIS Switch control. This bit controls the switches connected to the output of the low power DAC. 0x0 R/W 0 Low power DAC switch controlled by LPDACCON0, Bit 5 (default). Clear this bit to 0 to control the switches connected to the output of the low power DAC via LPDACCON0, Bit 5. 1 Low power DAC switches override. Set this bit to 1 to overrides LPDACCON0, Bit 5. The switches connected to the Low Power DAC output are controlled via LPDACSW0, Bits[4:0]. 4 SW4 Low power DAC SW4 switch control. 0x0 R/W 0 Disconnects the direct connection of the VBIAS0 DAC output to the positive input of the potentiostat amplifier (default). 1 Connects the VBIAS0 DAC voltage output directly to the positive input of the potentiostat amplifier. 3 SW3 Low power DAC SW3 switch control. 0x1 0 Disconnects the VBIAS0 DAC voltage output from the low-pass filter/VBIAS0 pin. R/W 1 Connects the VBIAS0 DAC voltage output to the low-pass filter/VBIAS0 pin (default). 2 SW2 Low power DAC SW2 switch control. 0 Disconnects the direct connection of the VZERO0 DAC voltage output to the low power TIA positive input (default). 0x1 R/W 1 Connects the VZERO0 DAC voltage output directly to the low power TIA positive input. Data Sheet AD5940/AD5941 LOW POWER DAC analog.com Rev. G | 34 of 142 Table 17. Bit Descriptions for LPDACSW0 Register (Continued) Bits Bit Name Settings Description Reset Access 1 SW1 Low power DAC SW1 switch control. 0x0 0 Disconnects the VZERO0 DAC voltage output from the low-pass filter/VZERO0 pin. R/W 1 Connects the VZERO0 DAC voltage output to the low-pass filter/VZERO0 pin (default). 0 SW0 Low power DAC SW0 switch control. 0x0 0 Disconnects the VZERO0 DAC voltage output from the high speed TIA positive input (default). R/W 1 Connects the VZERO0 DAC voltage output to the high speed TIA positive input. Low Power DAC Data Output Register—LPDACDAT0 Address 0x00002120, Reset: 0x00000000, Name: LPDACDAT0 Table 18. Bit Descriptions for LPDACDAT0 Register Bits Bit Name Settings Description Reset Access [31:18] Reserved Reserved. 0x0 R [17:12] DACIN6 Low power DAC 6-bit output data register (1 LSB = 34.375 mV). A value between 0 and 0x3F sets the 6-bit output voltage. 0x0 R/W 0 Sets output voltage to 0.2 V. 111111 Sets output voltage to 2.366 V. [11:0] DACIN12 Low power DAC 12-bit output data register (1 LSB = 537 μV). A value between 0 and 0xFFF sets the 12-bit output voltage. 0x0 R/W 0 Sets output voltage to 0.2 V. 0xFFF Sets output voltage to 2.4 V. Low Power Reference Control Register—LPREFBUFCON Address 0x00002050, Reset: 0x00000000, Name: LPREFBUFCON Table 19. Bit Descriptions for LPREFBUFCON Register Bits Bit Name Settings Description Reset Access [31:2] Reserved Reserved. 0x0 R 1 LPBUF2P5DIS Low power output band gap buffer. This bit is normally cleared to enable the low power reference buffer. 0x0 R/W 0 Enables the low power 2.5 V buffer. 1 Powers down the low power 2.5 V buffer. 0 LPREFDIS Low power band gap power-down bit. This bit is normally cleared to enable the low power reference. 0x0 R/W 0 Low power reference enabled. 1 Low power reference powered down. Common-Mode Switch Mux Register—SWMUX Address 0x0000235C, Reset: 0x00000000, Name: SWMUX Table 20. Bit Descriptions for SWMUX Register Bits Bit Name Settings Description Reset Access [31:4] Reserved Reserved. 0x0 R 3 CMMUX Common-mode resistor select for AIN2 pin and AIN3 pin. 0x0 R/W 0 Common-mode switch off. Data Sheet AD5940/AD5941 LOW POWER DAC analog.com Rev. G | 35 of 142 Table 20. Bit Descriptions for SWMUX Register (Continued) Bits Bit Name Settings Description Reset Access 1 Enables the common-mode switches with a 10 MΩ resistor to set up the common-mode voltage on the AIN2 and AIN3 pins. The voltage is driven by the low power TIA and the AIN4/LPF0 pin. [2:0] Reserved Reserved. 0x0 R/W Data Sheet AD5940/AD5941 LOW POWER POTENTIOSTAT analog.com Rev. G | 36 of 142 The AD5940/AD5941 has a low power potentiostat that sets and controls the bias voltage of an electrochemical sensor. Typically, the output of the potentiostat is connected to CE0. The noninverting input is connected to VBIAS0 voltage and the inverting input is connected to RE0 as shown in Figure 19. For an electrochemical cell, the potentiostat maintains the bias voltage on the reference electrode (RE0) by sourcing or sinking current through the counter electrode (CE0). The output of the potentiostat can be connected to various package pins through the switch matrix (see the Programmable Switch Ma- trix section for details). There are a number of configurable switch options around the potentiostat to provide numerous configuration options (see Figure 22). The potentiostat can also be used a standard buffer output to output VBIAS0 voltage onto CE0. To achieve this, the inverting input is connected to the output of the potentiostat by closing the SW10 switch, as shown in Figure 22. Data Sheet AD5940/AD5941 LOW POWER TIA analog.com Rev. G | 37 of 142 The AD5940/AD5941 each has a low power TIA channel that ampli- fies small current inputs to voltages to be measured by the ADC. The load resistor and gain resistor are internal and programmable. Select the RTIA value that maximizes the ADC input range of ±900 mV when PGA gain is 1 or 1.5. Refer to the Specifications section for the maximum voltage for other PGA settings. To calculate the required gain resistor, use the following equation: IMAX = 0 . 9 V RTIA (9) where: IMAX is the expected full-scale input current. RTIA is the required gain resistor. There are a number of switches around the low power TIA circui- try. The LPTIASW0 register configures these switches. Figure 22 shows the available switches. When the TIAGAIN bits (Bits[9:5]) in the LPTIACON0 register are set, these switches are closed automatically. When these switches are closed, there is a force/ sense circuit with a low-pass filter resistor (RLPF) and a capacitor on the AIN4/LPF0 pin that acts as a resistor-capacitor (RC) delay circuit. The LPTIA0_P_LPF0 connects the output of the low power TIA low-pass filter to the ADC mux. Analog Devices recommends that the LPTIA0_P_LPF0 mux option be selected as the ADC input when using the low power TIA. It is recommended to connect a 100 nF capacitor between the RC0_0 pin and the RC0_1 pin to stabilize the low power TIA. LOW POWER TIA PROTECTION DIODES Back to back protection diodes are connected in parallel with the RTIA resistor. These diodes are connected or disconnected by clos- ing or opening SW0, controlled by LPTIASW0, Bit 0. These diodes are intended for use when switching RTIA gain settings to amplify small currents to prevent saturation of the TIA. These diodes have a leakage current specification dependent on the voltage across the diodes. If the differential voltage across the diodes is >200 mV, leakage can be >1 nA. If the voltage is >500 mV, leakage can be >1 μA. Current-Limit Feature of the Low Power TIA and Potentiostat Amplifier In addition to the protection diode, the low power TIA also has a built in current limiting feature. If the current sourced or sunk from the low power TIA is greater than the overcurrent limit protection specified in Table 1, the amplifiers clamp the current to this limit. If a sensor attempts to source or sink more than the overcurrent limit during startup, the amplifier clamps the output current. Do not use this feature more frequently or for longer than specified in Table 1. Low Power TIA Force/Sense Feature The LPTIACON0[9:5] bits select different gain resistor values for the low power TIA, labeled as RTIA in Figure 22. The force and sense connections shown on the feedback path of the low power TIA are used to avoid voltage (I × R) drops on the switches, which select different RTIA settings for the internal RTIA. USING AN EXTERNAL RTIA To use an external RTIA resistor, take the following steps: 1. Connect an external RTIA resistor across the RC0_0 pin and the RC0_1 pin. 2. Clear LPTIACON0, Bits[9:5] = 0 to disconnect the internal RTIA resistor from the TIA output terminal. 3. Close the SW9 switch by setting LPTIASW0, Bit 9 = 1. When using the internal RTIA resistor, open the SW9 switch. 4. Connect an external capacitor in parallel with an external RTIA resistor to maintain loop stability. The recommended value of this external capacitor is 100 nF. RECOMMENDED SWITCH SETTINGS FOR VARIOUS OPERATING MODES Table 21 describes the recommended switch settings in the low power potentiostat loop for various measurement types. For all measurement types, setting the switch to 1 closes the switch and setting the switch to 0 opens the switch. LPTIASW0[13:0] controls SW13 to SW0, as shown in Figure 22. Figure 21 shows the relationship between the RLOAD and RGAIN settings for the LPTIA. RLOAD is configured by setting LPTIACON0 [12:10]. RGAIN is configured by LPTIACON0[9:5]. When RLOAD is large, it uses resistors from the RGAIN bank, reducing the size of RGAIN. See descriptions in the LPTIACON0 bit fields (Table 22 and Table 24) for details. Figure 21. LPTIA RLOAD and RGAIN Configuration Data Sheet AD5940/AD5941 LOW POWER TIA analog.com Rev. G | 38 of 142 Table 21. Recommended Switch Settings in Low Power Potentiostat Loop Measurement Name LPDACCON0, Bit 5 LPDACSW0, Bits[5:0] LPTIASW0, Bits[13:0] Description Amperometric Mode 0 0xXX1 0x302C or 0b11 0000 0010 1100 Normal dc current measurement. External capacitors to the VBIAS0 and VZERO0 DACs are connected. Amperometric Mode with Diode Protection 0 0xXX1 0x302D or 0b11 0000 0010 1101 Normal dc current measurement with the low power TIA back to back diode protection enabled. External capacitors to VBIAS0 and VZERO0 are connected. Amperometric Mode with Short Switch Enabled 0 0xXX1 0x302E or 0b11 0000 0010 1110 Normal dc current measurement with short switch protection enabled. SW1 is closed to connect the SE0 input to the output of the low power TIA. External capacitors to VBIAS0 and VZERO0 are connected. This setting is useful if the external sensor must be charged after a power-up and many currents are flowing in and out of the SE0 pin. Amperometric Mode for Zero Biased Sensor 0 0xXX1 0x306C or 0b11 0000 0110 1100 Amperometric mode with SW6 configured to set sensors on the RE0 and SE0 electrodes to the VBIAS0 level. Potentiostat inverting and low power TIA noninverting inputs are shorted. This mode gives the best noise performance for zero bias voltage sensors. Amperometric Mode for Two-Lead Sensor 0 0xXX1 0x342C or 0b11 0100 0010 1100 Amperometric mode with SW10 closed to short CE0 to RE0 internally. Chronoamperometry (Low Power Pulse Test) Using Low Power TIA 1 0x32 0x0014 or 0b00 0000 0001 0100 VBIAS0 output generates pulse to CE0 electrode. Capacitors on low power DACs are disconnected. Low power TIA measures SE0 current response. Chronoamperometry (Full Power Pulse Test) Using High Speed TIA on SE0 1 0x31 0x0094 or 0b00 0000 1001 0100 VBIAS0 output generates pulse to CE0 electrode. Capacitors on VBIAS0 and VZERO0 are disconnected. High speed TIA measures SE0 current response. Voltammetry (Full Power Pulse Test) Using High Speed TIA 1 0x31 0x0094 or 0b00 0000 1001 0100 VBIAS0 output generates pulse to CE0 electrode. Capacitors on VBIAS0 and VZERO0 are disconnected. High speed TIA measures SE0 or DE0 current response. High speed TIA resistors and switches are configured separately. Potentiostat and Low Power TIA in Unity-Gain Mode (Test Mode) 0 0xXX1 0x04A4 or 0b00 0100 1010 0100 Potentiostat in unity-gain mode, output to CE0 pin. Low power TIA in unity-gain mode, output to RC0_1 pin. This mode is useful for checking the VBIAS0 or VZERO0 DAC outputs. 1 0xXX = don’t care. Data Sheet AD5940/AD5941 LOW POWER TIA analog.com Rev. G | 39 of 142 Figure 22. Low Bandwidth Loop Switches LOW POWER TIA CIRCUITS REGISTERS Table 22. Low Power TIA and DAC Registers Summary Address Name Description Reset Access 0x000020E4 LPTIASW0 Low power TIA switch configuration 0x00000000 R/W 0x000020EC LPTIACON0 Low power TIA control bits, Channel 0 0x00000003 R/W Low Power TIA Switch Configuration Register—LPTIASW0 Address 0x000020E4, Reset: 0x00000000, Name: LPTIASW0 Table 23. Bit Descriptions for LPTIASW0 Register Bits Bit Name Settings Description Reset Access [31:16] Reserved Reserved. 0x0 R 15 RECAL SW15 switch control, active high. 0x0 R/W 0 Opens switch. 1 Closes switch. 14 Reserved Reserved. 0x0 R/W 13 SW13 SW13 switch control, active high. 0x0 R/W 0 Opens switch. 1 Closes switch. Data Sheet AD5940/AD5941 LOW POWER TIA analog.com Rev. G | 40 of 142 Table 23. Bit Descriptions for LPTIASW0 Register (Continued) Bits Bit Name Settings Description Reset Access 12 SW12 SW12 switch control, active high. 0x0 R/W 0 Opens switch. 1 Closes switch. 11 SW11 SW11 switch control, active high. 0x0 R/W 0 Opens switch. 1 Closes switch. 10 SW10 SW10 switch control, active high. 0x0 R/W 0 Opens switch. 1 Closes switch. 9 SW9 SW9 switch control, active high. 0x0 R/W 0 Opens switch. 1 Closes switch. 8 SW8 SW8 switch control, active high. 0x0 R/W 0 Opens switch. 1 Closes switch. 7 SW7 SW7 switch control, active high. 0x0 R/W 0 Opens switch. 1 Closes switch. 6 SW6 SW6 switch control, active high. 0x0 R/W 0 Opens switch. 1 Closes switch. 5 SW5 SW5 switch control, active high. 0x0 R/W 0 Opens switch. 1 Closes switch. 4 SW4 SW4 switch control, active high. 0x0 R/W 0 Opens switch. 1 Closes switch. 3 SW3 SW3 switch control, active high. 0x0 R/W 0 Opens switch. 1 Closes switch. 2 SW2 SW2 switch control, active high. 0x0 R/W 0 Opens switch. 1 Closes switch. 1 SW1 SW1 switch control, active high. 0x0 R/W 0 Opens switch. 1 Closes switch. 0 SW0 SW0 switch control, active high. 0x0 R/W 0 Opens switch. 1 Closes switch. Data Sheet AD5940/AD5941 LOW POWER TIA analog.com Rev. G | 41 of 142 Low Power TIA Control Bits, Channel 0 Register—LPTIACON0 Address 0x000020EC, Reset: 0x00000003, Name: LPTIACON0 Table 24. Bit Descriptions for LPTIACON0 Register Bits Bit Name Settings Description Reset Access [31:16] Reserved Reserved. 0x0 R [15:13] TIARF These bits set the low-pass filter resistor (RLPF) and configure the low power TIA output low-pass filter cutoff frequency. 0x0 R/W 0 Disconnects the TIA output from the low-pass filter pin (LPF0), which is useful for diagnostics where a fast response is required from the ADC. This setting disconnects the low power TIA output from the low-pass filter capacitor. 1 Bypass resistor; 0 Ω option. 10 20 kΩ. 11 100 kΩ. 100 200 kΩ. 101 400 kΩ. 110 600 kΩ. 111 1 MΩ; recommended value for optimal dc current measurement performance. This setting is the lowest cutoff frequency setting for the low-pass filter. [12:10] TIARL These bits set RLOAD. 0x0 R/W 0 0 Ω. 1 10 Ω. 10 30 Ω. 11 50 Ω. 100 100 Ω. 101 1.6 kΩ; RTIA must be ≥ 2 kΩ. 110 3.1 kΩ; RTIA must be ≥ 4 kΩ. 111 3.6 kΩ; RTIA must be ≥ 4 kΩ. [9:5] TIAGAIN These bits set the RTIA. 0x0 R/W 0 Disconnects the RTIA. 1 200 Ω. The RTIA is combination of RLOAD and a fixed series 110 Ω. Assumes RLOAD = 10 Ω. Set by the TIARL bits. RTIA = 100 Ω − RLOAD + 110 Ω. The fixed overall RTIA = 200 Ω. 10 1 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 1 kΩ. If RLOAD > 100 Ω, RTIA = 1 kΩ − (RLOAD − 100 Ω). 11 2 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 2 kΩ. If RLOAD > 100 Ω, RTIA = 2 kΩ − (RLOAD − 100 Ω). 100 3 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 3 kΩ. If RLOAD > 100 Ω, RTIA = 3 kΩ − (RLOAD − 100 Ω). 101 4 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 4 kΩ. If RLOAD > 100 Ω, RTIA = 4 kΩ − (RLOAD − 100 Ω). 110 6 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 6 kΩ. If RLOAD > 100 Ω, RTIA = 6 kΩ − (RLOAD − 100 Ω). 111 8 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 8 kΩ. If RLOAD > 100 Ω, RTIA = 8 kΩ − (RLOAD − 100 Ω). 1000 10 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 10 kΩ. If RLOAD > 100 Ω, RTIA = 10 kΩ − (RLOAD − 100 Ω). 1001 12 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 12 kΩ. If RLOAD > 100 Ω, RTIA = 12 kΩ − (RLOAD − 100 Ω). 1010 16 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 16 kΩ. If RLOAD > 100 Ω, RTIA = 16 kΩ − (RLOAD − 100 Ω). 1011 20 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 20 kΩ. If RLOAD > 100 Ω, RTIA = 20 kΩ − (RLOAD − 100 Ω). 1100 24 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 24 kΩ. If RLOAD > 100 Ω, RTIA = 24 kΩ − (RLOAD − 100 Ω). 1101 30 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 30 kΩ. If RLOAD > 100 Ω, RTIA = 30 kΩ − (RLOAD − 100 Ω). 1110 32 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 32 kΩ. If RLOAD > 100 Ω, RTIA = 32 kΩ − (RLOAD − 100 Ω). 1111 40 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 40 kΩ. If RLOAD >100 Ω, RTIA = 40 kΩ − (RLOAD − 100 Ω). 10000 48 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 48 kΩ. If RLOAD > 100 Ω, RTIA = 48 kΩ − (RLOAD − 100 Ω). 10001 64 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 64 kΩ. If RLOAD > 100 Ω, RTIA = 64 kΩ − (RLOAD − 100 Ω). 10010 85 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 85 kΩ. If RLOAD > 100 Ω, RTIA = 85 kΩ − (RLOAD − 100 Ω). 10011 96 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 96 kΩ. If RLOAD > 100 Ω, RTIA = 96 kΩ − (RLOAD − 100 Ω). Data Sheet AD5940/AD5941 LOW POWER TIA analog.com Rev. G | 42 of 142 Table 24. Bit Descriptions for LPTIACON0 Register (Continued) Bits Bit Name Settings Description Reset Access 10100 100 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 100 kΩ. If RLOAD > 100 Ω, RTIA = 100 kΩ − (RLOAD − 100 Ω). 10101 120 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 120 kΩ. If RLOAD > 100 Ω, RTIA = 120 kΩ − (RLOAD − 100 Ω). 10110 128 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 128 kΩ. If RLOAD > 100 Ω, RTIA = 128 kΩ − (RLOAD − 100 Ω). 10111 160 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 160 kΩ. If RLOAD > 100 Ω, RTIA = 160 kΩ − (RLOAD − 100 Ω). 11000 196 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 196 kΩ. If RLOAD > 100 Ω, RTIA = 196 kΩ − (RLOAD − 100 Ω). 11001 256 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 256 kΩ. If RLOAD > 100 Ω, RTIA = 256 kΩ − (RLOAD − 100 Ω). 11010 512 kΩ. If RLOAD ≤ 100 Ω, RTIA = (100 Ω − RLOAD) + 512 kΩ. If RLOAD > 100 Ω, RTIA = 512 kΩ − (RLOAD − 100 Ω). [4:3] IBOOST Current boost control. 0x0 R/W 00 Normal mode. 01 Increase amplifier output stage current to quickly charge external capacitor load. This setting is intended for use with high current sensors. 10 Double TIA and potentiostat amplifier overall quiescent current and increase amplifier bandwidth. This setting is useful for diagnostic tests. 11 Double TIA and potentiostat amplifier overall quiescent current and increase output stage current. This setting increases amplifier bandwidth and output current capability. 2 HALFPWR Half power mode select. This control bit reduces the active power consumption of the TIA and potentiostat amplifier for Sensor Channel 0. 0x0 R/W 0 Normal mode (default). 1 Reduces and TIA current by half. 1 PAPDEN Potentiostat amplifier power-down. Low power potentiostat power-down control bit. 0x1 R/W 0 Power-up. 1 Power-down. 0 TIAPDEN TIA power-down. Low power TIA power-down control bit. 0x1 R/W 0 Power-up. 1 Power-down. Data Sheet AD5940/AD5941 HIGH SPEED DAC CIRCUITS analog.com Rev. G | 43 of 142 The 12-bit high speed DAC generates an ac excitation signal when measuring the impedance of an external sensor. Control the DAC output signal directly by writing to a data register or by using the automated waveform generator block. The high speed DAC signal is fed to an excitation amplifier designed specifically to couple the ac signal on top of the normal dc bias voltage of a sensor. HIGH SPEED DAC OUTPUT SIGNAL GENERATION There are two ways of setting the output voltage of the high speed DAC, as follows: ► A direct write to the DAC code register, HSDACDAT. This regis- ter is a 12-bit register where the most significant bit (MSB) is a sign bit. Writing 0x800 results in a 0 V output. Writing 0x200 results in negative full-scale, and writing 0xE00 results in positive full-scale. The following equation can be used for calculating the output voltage: VOUT = HSDACDAT − 211 211 × 404 . 4 mV × INAMPGNMDE × ATTENEN (10) where: VOUT is the voltage at the output of the excitation amplifier. HSDACDAT is the 12-bit HSDAC code register value. INAMPGNMDE is the gain setting of the excitation amplifier. The setting can be 2 or 0.25. ATTENEN is the attenuator setting. The setting can be 1 or 0.2. ► Use the automatic waveform generator. The waveform generator can be programmed to generate fixed frequency, fixed amplitude signals including, sine, trapezoid, and square wave signals. If the user selects the sine wave, options exist to adjust the offset and phase of the output signal. The following equation can be used to calculate the sine wave amplitude: VOUT p − p = WGAMPLITUDE 211 − 1 × 808 . 8 mV × INAMPGNMDE × ATTENEN (11) where: VOUT(p-p) is the peak-to-peak voltage of the ac signal. WGAMPLITUDE is the 12-bit HSDAC code register value. INAMPGNMDE is the gain setting of the excitation amplifier. The setting can be 2 or 0.25. ATTENEN is the attenuator setting. The setting can be 1 or 0.2. POWER MODES OF THE HIGH SPEED DAC CORE The reference source of the high speed DAC is an internal 1.82 V precision reference voltage (VREF_1V82 pin). There are three basic modes of operation for the high speed DAC that trade off between power consumption vs. output speed: low power mode, high power mode, and hibernate mode. The high speed DAC can also be placed into hibernate mode when inactive. Low Power Mode Low power mode is used when the high speed DAC output signal frequency is <80 kHz. When configuring the high speed DAC for low power mode, take the following steps: 1. Clear the PMBW register (Bit 0 = 0). 2. In this mode, the system clock to the high speed DAC and the ADC is 16 MHz. 3. Ensure that CLKSEL, Bits[1:0] = 0 to select a 16 MHz, internal, high frequency oscillator clock source. Ensure the system clock divide ratio is 1 (CLKCON0, Bits[5:0] = 0 or 1. 4. If the internal high speed oscillator is selected as the system clock source, ensure that the 16 MHz option is selected. Set HSOSCCON, Bit 2 = 1. High Power Mode High power mode increases the bandwidth supported by the high speed DAC amplifiers. Use high power mode when the high speed DAC frequency is greater than 80 kHz. To enter high power mode, a number of register writes are required. To configure the high speed DAC for high power mode, take the following steps: 1. Set the PMBW register, Bit 0 = 1. Power consumption is increased, but the output signal bandwidth increases to a maxi- mum of 200 kHz. In high power mode, the system clock to the DAC and the ADC is 32 MHz. 2. Ensure that CLKSEL Bits[1:0] select a 32 MHz clock source. For example, to select an internal high speed oscillator, set CLKSEL Bits[1:0] (SYSCLKSEL) = 00. Ensure that the system clock divide ratio is 1 (CLKCON0 Bits[5:0] = 0 or 1). 3. If the internal high speed oscillator is selected as the system clock source, ensure that the 32 MHz option is selected. Clear HSOSCCON, Bit 2 = 0. Hibernate Mode When the AD5940/AD5941 enter hibernate mode, the clocks to the high speed DAC circuits are clock gated to save power. When in active mode and the high speed DAC is not in use, disable the clocks to save power. HIGH SPEED DAC FILTER OPTIONS The output stage of the high speed DAC features a configurable reconstruction filter. The configuration of the reconstruction filter is dependent on the output signal frequency of the DAC. Bits[3:2] in the PMBW register configure the 3 dB cutoff frequency of the reconstruction filter. Ensure that the cutoff frequen