EFR32MG29 Wireless SoC Family Data Sheet

Ordering Code Protocol Stack Max TX Power DC-DC Flash (KB) RAM (KB) GPIO Package Temp Range EFR32MG29B230F1024CM40- C • Zigbee PRO • Zigbee Green Pow- er • Bluetooth 5.x • Direction Finding (AoA Transmitter) • Proprietary 6 dBm Boost 1024 256 25 QFN40 -20 to 55 °C EFR32MG29B140F1024IM40-C • Zigbee PRO • Zigbee Green Pow- er • Bluetooth 5.x • Direction Finding (AoA Transmitter) • Proprietary 8 dBm Buck 1024 256 26 QFN40 -40 to 125 °C Bluetooth 5.x: As the Bluetooth standard evolves, Silicon Labs is regularly adding new features. For more information on supported Bluetooth capabilities, visit https://www.silabs.com/bluetooth-hardware. EFR32MG29 Wireless SoC Family Data Sheet Ordering Information silabs.com | Building a more connected world. Rev. 1.1 | 3 Product Family Security Features Memory Temperature Grade Size Package Pins Revision Tape & Reel EFR32MG29 B 140 F 1024 I M 40 C R - Field Options Product Family • EFR32MG29: Wireless SoC Family Security • B: Secure Vault High Features [f1][f2][f3] • f1 • 1: DC-DC Buck Converter • 2: DC-DC Boost Converter • f2 • 3: 6 dBm PA Transmit Power • 4: 8 dBm PA Transmit Power • f3 • 0: 256 KB RAM Memory • F: Flash Size • Memory Size in KBytes Temperature Grade • C: -20 to +55 °C • I: -40 to +125 °C Package • M: QFN Pins • Number of Package Pins Revision • C: Revision C Tape & Reel • R: Tape & Reel (optional) Figure 2.1. Ordering Code Key EFR32MG29 Wireless SoC Family Data Sheet Ordering Information silabs.com | Building a more connected world. Rev. 1.1 | 4 Table of Contents 1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 Radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2.1 Antenna Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2.2 Fractional-N Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . 9 3.2.3 Receiver Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2.4 Transmitter Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2.5 Packet and State Trace . . . . . . . . . . . . . . . . . . . . . . . . .10 3.2.6 Data Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.2.7 Radio Controller (RAC). . . . . . . . . . . . . . . . . . . . . . . . . .10 3.2.8 RFSENSE Interface . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.3 General Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . .10 3.4 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.4.1 Clock Management Unit (CMU) . . . . . . . . . . . . . . . . . . . . . . .10 3.4.2 Internal and External Oscillators. . . . . . . . . . . . . . . . . . . . . . .11 3.5 Counters/Timers and PWM . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.5.1 Timer/Counter (TIMER) . . . . . . . . . . . . . . . . . . . . . . . . .11 3.5.2 Low-Energy Timer (LETIMER) . . . . . . . . . . . . . . . . . . . . . . .11 3.5.3 Real Time Clock with Capture (RTCC) . . . . . . . . . . . . . . . . . . . .11 3.5.4 Back-Up Real Time Counter (BURTC) . . . . . . . . . . . . . . . . . . . .11 3.5.5 Watchdog Timer (WDOG) . . . . . . . . . . . . . . . . . . . . . . . . .11 3.6 Communications and Other Digital Peripherals . . . . . . . . . . . . . . . . . . .12 3.6.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) . . . . . . . . . .12 3.6.2 Enhanced Universal Synchronous/Asynchronous Receiver/Transmitter (EUSART) . . . . .12 3.6.3 Inter-Integrated Circuit Interface (I2C) . . . . . . . . . . . . . . . . . . . . .12 3.6.4 Peripheral Reflex System (PRS) . . . . . . . . . . . . . . . . . . . . . .12 3.6.5 Pulse Density Modulation (PDM) Interface . . . . . . . . . . . . . . . . . . .12 3.7 Security Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.7.1 Secure Boot with Root of Trust and Secure Loader (RTSL) . . . . . . . . . . . . .13 3.7.2 Cryptographic Accelerator. . . . . . . . . . . . . . . . . . . . . . . . .14 3.7.3 True Random Number Generator (TRNG) . . . . . . . . . . . . . . . . . . .14 3.7.4 Secure Debug with Lock/Unlock. . . . . . . . . . . . . . . . . . . . . . .14 3.7.5 Differential Power Analysis (DPA) Countermeasures . . . . . . . . . . . . . . . .14 3.7.6 Secure Key Management with Physically Unclonable Function (PUF) . . . . . . . . . .14 3.7.7 Anti-Tamper . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3.7.8 Secure Attestation . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3.7.9 External Tamper Detection (ETAMPDET) . . . . . . . . . . . . . . . . . . .15 3.8 Analog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3.8.1 Analog to Digital Converter (IADC) . . . . . . . . . . . . . . . . . . . . . .15 3.8.2 Analog Comparator (ACMP) . . . . . . . . . . . . . . . . . . . . . . . .15 silabs.com | Building a more connected world. Rev. 1.1 | 5 3.9 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 3.9.1 Energy Management Unit (EMU) . . . . . . . . . . . . . . . . . . . . . .16 3.9.2 Voltage Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 3.9.3 Buck or Boost DC-DC Converter . . . . . . . . . . . . . . . . . . . . . .16 3.9.4 Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 3.10 Reset Management Unit (RMU) . . . . . . . . . . . . . . . . . . . . . . . .17 3.11 Core and Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.11.1 Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.11.2 Memory System Controller (MSC) . . . . . . . . . . . . . . . . . . . . .18 3.11.3 Linked Direct Memory Access Controller (LDMA) . . . . . . . . . . . . . . . .18 3.12 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 3.13 Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . .20 4. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .21 4.2 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . .22 4.3 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . .23 4.4 Buck-Mode DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . .25 4.4.1 Buck DC-DC Operating Limits . . . . . . . . . . . . . . . . . . . . . . .27 4.5 Boost-Mode DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . .28 4.6 Coulomb Counter Calibration Load (Buck DC-DC Only) . . . . . . . . . . . . . . . .29 4.7 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .29 4.8 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 4.8.1 MCU Current Consumption Using Buck DC-DC at 3.0 V VREGVDD Input . . . . . . . .30 4.8.2 MCU Current Consumption Using Boost DC-DC at 1.5 V VBAT Input . . . . . . . . . .32 4.8.3 MCU Current Consumption at 3.0 V . . . . . . . . . . . . . . . . . . . . .34 4.8.4 MCU Current Consumption at 1.8 V . . . . . . . . . . . . . . . . . . . . .36 4.8.5 Radio Current Consumption at 3.0 V Using Buck-Mode DCDC . . . . . . . . . . . .38 4.8.6 Radio Current Consumption at 1.5 V Using Boost-Mode DCDC . . . . . . . . . . . .41 4.8.7 Radio Current Consumption at 3.0 V . . . . . . . . . . . . . . . . . . . . .44 4.8.8 Radio Current Consumption at 1.8 V . . . . . . . . . . . . . . . . . . . . .47 4.9 Flash Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 4.10 Energy Mode Wake-up and Entry Times . . . . . . . . . . . . . . . . . . . . .51 4.11 Boot Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 4.12 Crypto Operation Timing for SE Manager API . . . . . . . . . . . . . . . . . . .53 4.13 Crypto Operation Average Current for SE Manager API . . . . . . . . . . . . . . . .55 4.14 RFSENSE Low-energy Wake-on-RF . . . . . . . . . . . . . . . . . . . . . .58 4.15 2.4 GHz RF Transceiver Characteristics for QFN40 Package . . . . . . . . . . . . . .59 4.15.1 RF Transmitter Characteristics for QFN40 Package. . . . . . . . . . . . . . . .59 4.15.2 RF Receiver Characteristics for QFN40 Package . . . . . . . . . . . . . . . .69 4.16 Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 4.16.1 High-Frequency Crystal Oscillator. . . . . . . . . . . . . . . . . . . . . .75 4.16.2 Low-Frequency Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . .76 silabs.com | Building a more connected world. Rev. 1.1 | 6 4.16.3 High-Frequency RC Oscillator (HFRCO) . . . . . . . . . . . . . . . . . . .77 4.16.4 Fast Start_Up RC Oscillator (FSRCO) . . . . . . . . . . . . . . . . . . . .78 4.16.5 Precision Low-Frequency RC Oscillator (LFRCO) . . . . . . . . . . . . . . . .79 4.16.6 Ultra Low-Frequency RC Oscillator . . . . . . . . . . . . . . . . . . . . .79 4.17 GPIO with 3 V Nominal IOVDD . . . . . . . . . . . . . . . . . . . . . . . .80 4.18 GPIO with 1.5 V Nominal IOVDD . . . . . . . . . . . . . . . . . . . . . . .82 4.19 Analog to Digital Converter (IADC) . . . . . . . . . . . . . . . . . . . . . . .83 4.20 Analog Comparator (ACMP) . . . . . . . . . . . . . . . . . . . . . . . . .86 4.21 External Trace Tamper Detection Supply Current . . . . . . . . . . . . . . . . . .87 4.22 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . .88 4.23 Brown Out Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . .89 4.23.1 DVDD BOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 4.23.2 LE DVDD BOD . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 4.23.3 AVDD and IOVDD BODs . . . . . . . . . . . . . . . . . . . . . . . .90 4.24 PDM Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . .91 4.24.1 Pulse Density Modulator (PDM), Common DBUS . . . . . . . . . . . . . . . .91 4.25 USART SPI Main Timing . . . . . . . . . . . . . . . . . . . . . . . . . .92 4.25.1 USART SPI Main Timing, Voltage Scaling = VSCALE2, IOVDD ≥ 1.8 V . . . . . . . . .93 4.25.2 USART SPI Main Timing, Voltage Scaling = VSCALE1, IOVDD ≥ 1.8 V . . . . . . . . .93 4.25.3 USART SPI Main Timing, Voltage Scaling = VSCALE2, 1.2 V ≤ IOVDD < 1.8 V . . . . . .94 4.25.4 USART SPI Main Timing, Voltage Scaling = VSCALE1, 1.2 V ≤ IOVDD < 1.8 V . . . . . .94 4.26 USART SPI Secondary Timing . . . . . . . . . . . . . . . . . . . . . . . .95 4.26.1 USART SPI Secondary Timing, Voltage Scaling = VSCALE2, IOVDD ≥ 1.8 V . . . . . . .95 4.26.2 USART SPI Secondary Timing, Voltage Scaling = VSCALE1, IOVDD ≥ 1.8 V . . . . . . .96 4.26.3 USART SPI Secondary Timing, Voltage Scaling = VSCALE2, 1.2 V ≤ IOVDD < 1.8 V . . . .96 4.26.4 USART SPI Secondary Timing, Voltage Scaling = VSCALE1, 1.2 V ≤ IOVDD < 1.8 V . . . .97 4.27 EUSART SPI Main Timing. . . . . . . . . . . . . . . . . . . . . . . . . .98 4.27.1 EUSART SPI Main Timing, Voltage Scaling = VSCALE2, IOVDD ≥ 1.8 V . . . . . . . .98 4.27.2 EUSART SPI Main Timing, Voltage Scaling = VSCALE1, IOVDD ≥ 1.8 V . . . . . . . .99 4.27.3 EUSART SPI Main Timing, Voltage Scaling = VSCALE2, 1.2 V ≤ IOVDD < 1.8 V . . . . . .99 4.27.4 EUSART SPI Main Timing, Voltage Scaling = VSCALE1, 1.2 V ≤ IOVDD < 1.8 V . . . . . 100 4.28 EUSART SPI Secondary Timing . . . . . . . . . . . . . . . . . . . . . .101 4.28.1 EUSART SPI Secondary Timing, Voltage Scaling = VSCALE2, IOVDD ≥ 1.8 V . . . . .101 4.28.2 EUSART SPI Secondary Timing, Voltage Scaling = VSCALE1, IOVDD ≥ 1.8 V . . . . .102 4.28.3 EUSART SPI Secondary Timing, Voltage Scaling = VSCALE0, IOVDD ≥ 1.8 V . . . . .102 4.28.4 EUSART SPI Secondary Timing, Voltage Scaling = VSCALE2, 1.2 V ≤ IOVDD < 1.8 V . . . 103 4.28.5 EUSART SPI Secondary Timing, Voltage Scaling = VSCALE1, 1.2 V ≤ IOVDD < 1.8 V . . . 103 4.29 I2C Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . 104 4.29.1 I2C Standard-mode (Sm) . . . . . . . . . . . . . . . . . . . . . . .104 4.29.2 I2C Fast-mode (Fm) . . . . . . . . . . . . . . . . . . . . . . . . .105 4.29.3 I2C Fast-mode Plus (Fm+) . . . . . . . . . . . . . . . . . . . . . . . 106 4.30 Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . 106 4.30.1 Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 4.30.2 RF Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 110 silabs.com | Building a more connected world. Rev. 1.1 | 7 4.30.3 DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . 111 4.30.4 IADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 4.30.5 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 5. Typical Connections . . . . . . . . . . . . . . . . . . . . . . . . . . .115 5.1 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 5.2 RF Matching Networks . . . . . . . . . . . . . . . . . . . . . . . . . .119 5.2.1 2.4 GHz Matching Network . . . . . . . . . . . . . . . . . . . . . . .119 5.3 Other Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 6. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.1 QFN40 with Buck DC-DC Device Pinout . . . . . . . . . . . . . . . . . . . .120 6.2 QFN40 with Boost DC-DC Device Pinout . . . . . . . . . . . . . . . . . . . . 122 6.3 Alternate Function Table. . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.4 Analog Peripheral Connectivity . . . . . . . . . . . . . . . . . . . . . . .125 6.5 Digital Peripheral Connectivity . . . . . . . . . . . . . . . . . . . . . . . . 126 7. QFN40 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . . 129 7.1 QFN40 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 129 7.2 QFN40 PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . .131 7.3 QFN40 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . .132 8. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 silabs.com | Building a more connected world. Rev. 1.1 | 8 3. System Overview 3.1 Introduction The EFR32 product family combines an energy-friendly MCU with a high-performance radio transceiver. The devices are well suited for secure connected IoT multi-protocol devices which require high performance and low energy consumption. This section gives a short introduction to the full radio and MCU system. A detailed functional description is available in the EFR32xG29 Reference Manual. 3.2 Radio The EFR32MG29 Wireless features a highly configurable radio transceiver which supports Zigbee and Bluetooth Low Energy wireless protocols. 3.2.1 Antenna Interface The 2.4 GHz antenna interface consists of a single-ended pin (RF2G4_IO). The external components for the antenna interface in typi- cal applications are shown in the RF Matching Networks section. 3.2.2 Fractional-N Frequency Synthesizer The EFR32MG29 contains a high-performance, low phase noise, fully integrated fractional-N frequency synthesizer. The synthesizer is used in receive mode to generate the LO frequency for the down-conversion mixer. It is also used in transmit mode to directly generate the modulated RF carrier. The fractional-N architecture provides excellent phase noise performance, frequency resolution better than 100 Hz, and low energy consumption. The synthesizer’s fast frequency settling allows for very short receiver and transmitter wake up times to reduce system energy consumption. 3.2.3 Receiver Architecture The EFR32MG29 uses a low-IF receiver architecture, which consists of a Low-Noise Amplifier (LNA) followed by an I/Q down-conver- sion mixer. The I/Q signals are further filtered and amplified before being sampled by the IF Analog-to-Digital Converter (IFADC). The IF frequency is configurable from 150 to 1371 kHz. The IF can further be configured for high-side or low-side injection, providing flexibility with respect to known interferers at the image frequency. The Automatic Gain Control (AGC) module adjusts the receiver gain to optimize performance and avoid saturation for excellent selec- tivity and blocking performance. The 2.4 GHz radio is calibrated at production to improve image rejection performance. Demodulation is performed in the digital domain. The demodulator performs configurable decimation and channel filtering to allow re- ceive bandwidths ranging from 0.1 to 2530 kHz. High carrier frequency and baud rate offsets are tolerated by active estimation and compensation. Advanced features supporting high-quality communication under adverse conditions include forward error correction by block and convolutional coding as well as Direct Sequence Spread Spectrum (DSSS). A Received Signal Strength Indicator (RSSI) is available for signal quality metrics, level-based proximity detection, and RF channel ac- cess by Collision Avoidance (CA) or Listen Before Talk (LBT) algorithms. An RSSI capture value is associated with each received frame and the dynamic RSSI measurement can be monitored throughout reception. 3.2.4 Transmitter Architecture The EFR32MG29 uses a direct-conversion transmitter architecture. For constant envelope modulation formats, the modulator controls phase and frequency modulation in the frequency synthesizer. Transmit symbols or chips are optionally shaped by a digital shaping filter. The shaping filter is fully configurable, including the BT product, and can be used to implement Gaussian or Raised Cosine shap- ing. Carrier Sense Multiple Access - Collision Avoidance (CSMA-CA) or Listen Before Talk (LBT) algorithms can be automatically timed by the EFR32MG29. These algorithms are typically defined by regulatory standards to improve interoperability in a given bandwidth be- tween devices that otherwise lack synchronized RF channel access. EFR32MG29 Wireless SoC Family Data Sheet System Overview silabs.com | Building a more connected world. Rev. 1.1 | 9 3.2.5 Packet and State Trace The EFR32MG29 Frame Controller has a packet and state trace unit that provides valuable information during the development phase. It features: • Non-intrusive trace of transmit data, receive data, and state information • Data observability on a single-pin UART data output or on a two-pin SPI data output • Configurable data output bitrate / baudrate • Multiplexed transmitted data, received data, and state / meta information in a single serial data stream 3.2.6 Data Buffering The EFR32MG29 features an advanced Radio Buffer Controller (BUFC) capable of handling up to four buffers of adjustable size from 64 to 4096 bytes. Each buffer can be used for RX, TX, or for both. The buffer data is located in RAM, enabling zero-copy operations. 3.2.7 Radio Controller (RAC) The RAC controls the top-level state of the radio subsystem in the EFR32MG29. It performs the following tasks: • Precisely timed control of enabling and disabling of the receiver and transmitter circuitry • Run-time calibration of receiver, transmitter, and frequency synthesizer • Detailed frame transmission timing with optional LBT or CSMA-CA 3.2.8 RFSENSE Interface The RFSENSE block allows the device to remain in EM2, EM3, or EM4 and wake when RF energy above a specified threshold is de- tected. When operated in selective mode, the RFSENSE block performs OOK preamble and sync word detection, preventing false wake-up events. 3.3 General Purpose Input/Output (GPIO) EFR32MG29 has up to 26 GPIO pins. Each GPIO pin can be individually configured as either an output or input. More advanced con- figurations including open-drain, open-source, and glitch-filtering can be configured for each individual GPIO pin. The GPIO pins can be overridden by peripheral connections, like SPI communication. Each peripheral connection can be routed to several GPIO pins on the device. The input value of a GPIO pin can be routed through the Peripheral Reflex System (PRS) to other peripherals. The GPIO sub- system supports asynchronous external pin interrupts. All of the pins on ports A and port B are EM2 capable. These pins may be used by low-energy peripherals in EM2/3 and may also be used as EM2/3 pin wake-ups. Pins on ports C and D are latched/retained in their current state when entering EM2 until EM2 exit upon which internal peripherals could once again drive those pads. A few GPIOs also have wake functionality down to EM4. These pins are listed in the Alternate Function Table with the function GPIO.EM4WU. 3.4 Clocking 3.4.1 Clock Management Unit (CMU) The CMU controls oscillators and clocks in the EFR32MG29. Individual enabling and disabling of clocks to all peripheral modules is performed by the CMU. The CMU also controls enabling and configuration of the oscillators. A high degree of flexibility allows software to optimize energy consumption in any specific application by minimizing power dissipation in unused peripherals and oscillators. EFR32MG29 Wireless SoC Family Data Sheet System Overview silabs.com | Building a more connected world. Rev. 1.1 | 10 3.4.2 Internal and External Oscillators The EFR32MG29 supports two crystal oscillators and fully integrates four RC oscillators: • A high-frequency crystal oscillator (HFXO) with integrated load capacitors, tunable in small steps, provides a precise timing refer- ence for the MCU. The HFXO provides excellent RF clocking performance using a 38.4 MHz crystal. The HFXO can also support an external clock source such as a TCXO for applications that require an extremely accurate clock frequency over temperature. • A 32.768 kHz crystal oscillator (LFXO) provides an accurate timing reference for low-energy modes. • An integrated high-frequency RC oscillator (HFRCO) is available for the MCU system, when crystal accuracy is not required. The HFRCO employs fast start-up at minimal energy consumption combined with a wide frequency range, from 1 to 76.8 MHz. • An integrated fast start-up RC oscillator (FSRCO) that runs at a fixed 20 MHz • An integrated low-frequency 32.768 kHz RC oscillator (LFRCO) for low-power operation without an external crystal. Precision mode enables periodic recalibration against the 38.4 MHz HFXO crystal to improve accuracy to ±500 ppm, suitable for BLE sleep interval timing. • An integrated ultra-low-frequency 1 kHz RC oscillator (ULFRCO) is available to provide a timing reference at the lowest energy con- sumption in low-energy modes. 3.5 Counters/Timers and PWM 3.5.1 Timer/Counter (TIMER) TIMER peripherals keep track of timing, count events, generate PWM outputs and trigger timed actions in other peripherals through the Peripheral Reflex System (PRS). The core of each TIMER is a 16-bit or 32-bit counter with up to 3 compare/capture channels. Each channel is configurable in one of three modes: • In capture mode, the counter state is stored in a buffer at a selected input event. • In compare mode, the channel output reflects the comparison of the counter to a programmed threshold value. • In PWM mode, the TIMER supports generation of pulse-width modulation (PWM) outputs of arbitrary waveforms defined by the se- quence of values written to the compare registers. Complementary outputs with dead-time insertion are available on select TIMER output channels. See 3.13 Configuration Summary for information on the feature set of each timer. 3.5.2 Low-Energy Timer (LETIMER) The unique LETIMER is a 24-bit timer that is available in energy mode EM0 Active, EM1 Sleep, EM2 Deep Sleep, and EM3 Stop. This allows it to be used for timing and output generation when most of the device is powered down, allowing simple tasks to be performed while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of wave- forms with minimal software intervention. The LETIMER is connected to the Peripheral Reflex System (PRS) and can be configured to start counting on compare matches from other peripherals such as the Real Time Clock. 3.5.3 Real Time Clock with Capture (RTCC) The RTCC is a 32-bit counter that provides timekeeping down to EM3. The RTCC can be clocked by any of the on-board, low-frequen- cy oscillators, and it is capable of providing system wake-up at user-defined intervals. A secondary RTC is used by the RF protocol stack for event scheduling, leaving the primary RTCC block available exclusively for appli- cation software. 3.5.4 Back-Up Real Time Counter (BURTC) The Back-Up Real Time Counter (BURTC) is a 32-bit counter providing timekeeping in all energy modes, including EM4. The BURTC can be clocked by any of the on-board low-frequency oscillators, and it is capable of providing system wake-up at user-defined inter- vals. 3.5.5 Watchdog Timer (WDOG) The watchdog timer can act both as an independent watchdog or as a watchdog synchronous with the CPU clock. It has windowed monitoring capabilities, and can generate a reset or different interrupts depending on the failure mode of the system. The watchdog can also monitor autonomous systems driven by the Peripheral Reflex System (PRS). EFR32MG29 Wireless SoC Family Data Sheet System Overview silabs.com | Building a more connected world. Rev. 1.1 | 11 3.6 Communications and Other Digital Peripherals 3.6.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) The USART is a flexible serial I/O module. It supports full duplex asynchronous UART communication with hardware flow control as well as RS-485, SPI, MicroWire, and 3-wire. It can also interface with devices supporting: • ISO7816 SmartCards • IrDA • I2S 3.6.2 Enhanced Universal Synchronous/Asynchronous Receiver/Transmitter (EUSART) The EUSART supports full duplex asynchronous UART communication with hardware flow control, RS-485, and IrDA support. The EU- SART also supports high-speed SPI. In EM0 and EM1, the EUSART provides a high-speed, buffered communication interface. When routed to GPIO ports A or B, the EUSART0 may also be used in a low-energy mode and operate in EM2. A 32.768 kHz clock source allows full duplex UART communication up to 9600 baud. EUSART0 can also act as a SPI secondary device in EM2 and EM3, and wake the system when data is received from an external bus controller. 3.6.3 Inter-Integrated Circuit Interface (I2C) The I2C module provides an interface between the MCU and a serial I2C bus. It is capable of acting as a main or secondary interface and supports multi-drop buses. Standard-mode, fast-mode, and fast-mode plus speeds are supported, allowing transmission rates from 10 kbit/s up to 1 Mbit/s. Bus arbitration and timeouts are also available, allowing implementation of an SMBus-compliant system. The interface provided to software by the I2C module allows precise timing control of the transmission process and highly automated trans- fers. Automatic recognition of addresses is provided in active and low-energy modes. Not all instances of I2C are available in all energy modes. 3.6.4 Peripheral Reflex System (PRS) The PRS provides a communication network between different peripheral modules without software involvement. Peripheral modules producing reflex signals are called producers. The PRS routes reflex signals from producers to consumer peripherals which in turn per- form actions in response. Edge triggers and other functionality, such as simple logic operations (AND, OR, NOT), can be applied by the PRS to the signals. The PRS allows peripherals to act autonomously without waking the MCU core, saving power. 3.6.5 Pulse Density Modulation (PDM) Interface The PDM module provides a serial interface and decimation filter for Pulse Density Modulation (PDM) microphones, isolated Sigma- delta ADCs, digital sensors, and other PDM or sigma delta bit stream peripherals. A programmable Cascaded Integrator Comb (CIC) filter is used to decimate the incoming bit streams. PDM supports stereo or mono input data and DMA transfer. EFR32MG29 Wireless SoC Family Data Sheet System Overview silabs.com | Building a more connected world. Rev. 1.1 | 12 3.7 Security Features A dedicated hardware secure engine containing its own CPU enables the Secure Vault functions. It isolates cryptographic functions and data from the host Cortex-M33 core, and provides several additional security features. The EFR32MG29 family includes devices with Secure Vault High capabilities, which are summarized in the following table. Table 3.1. Secure Vault Features Feature Secure Vault High True Random Number Generator (TRNG) Yes Secure Boot with Root of Trust and Secure Loader (RTSL) Yes Secure Debug with Lock/Unlock Yes DPA Countermeasures Yes Anti-Tamper Yes Secure Attestation Yes Secure Key Management Yes Symmetric Encryption • AES 128 / 192 / 256 bit • ECB, CTR, CBC, CFB, CCM, GCM, CBC-MAC, and GMAC • ChaCha20 Public Key Encryption - ECDSA / ECDH / EdDSA • p192, p256, p384 and p521 • Curve25519 (ECDH) • Ed25519 (EdDSA) Key Derivation • ECJ-PAKE p192, p256, p384, and p521 • PBKDF2 • HKDF Hashes • SHA-1 • SHA-2 256, 384, and 512 • Poly1305 Additionally, the EFR32MG29 includes an External Tamper Detection (ETAMPDET) peripheral which provides additional physical se- curity for the end product. 3.7.1 Secure Boot with Root of Trust and Secure Loader (RTSL) The Secure Boot with RTSL authenticates a chain of trusted firmware that begins from an immutable memory (ROM). It prevents malware injection, prevents rollback, ensures that only authentic firmware is executed, and protects Over-The-Air (OTA) up- dates. For more information about this feature, see AN1218: Series 2 Secure Boot with RTSL. EFR32MG29 Wireless SoC Family Data Sheet System Overview silabs.com | Building a more connected world. Rev. 1.1 | 13 3.7.2 Cryptographic Accelerator The Cryptographic Accelerator is an autonomous hardware accelerator with Differential Power Analysis (DPA) countermeasures to pro- tect keys. It supports AES encryption and decryption with 128/192/256-bit keys, ChaCha20 encryption, and Elliptic Curve Cryptography (ECC) to support public key operations and hashes. Supported block cipher modes of operation for AES include: • Electronic Code Book (ECB) • Counter Mode (CTR) • Cipher Block Chaining (CBC) • Cipher Feedback (CFB) • Galois Counter Mode (GCM) • Counter with CBC-MAC (CCM) • Cipher Block Chaining Message Authentication Code (CBC-MAC) • Galois Message Authentication Code (GMAC) The Cryptographic Accelerator accelerates Elliptical Curve Cryptography and supports the National Institute of Standards and Technol- ogy (NIST) recommended curves including P-192, P-256, P-384, and P-521 for Elliptic Curve Diffie-Hellman (ECDH) key derivation, and Elliptic Curve Digital Signature Algorithm (ECDSA) sign and verify operations. Also supported is the non-NIST Curve25519 for ECDH and Ed25519 for Edwards-curve Digital Signature Algorithm (EdDSA) sign and verify operations. Secure Vault also supports Elliptic Curve variant of Password Authenticated Key Exchange by Juggling (ECJ-PAKE) and Password- Based Key Derivation Function 2 (PBKDF2). Supported hashes include SHA-1, SHA-2/256/384/512 and Poly1305. This implementation provides a fast and energy efficient solution to state of the art cryptographic needs. 3.7.3 True Random Number Generator (TRNG) The TRNG module is a non-deterministic random number generator that harvests entropy from a thermal energy source. It includes start-up health tests for the entropy source as required by NIST SP800-90B and AIS-31, as well as online health tests required for NIST SP800-90C. The TRNG is suitable for periodically generating entropy to seed an approved pseudo random number generator. 3.7.4 Secure Debug with Lock/Unlock For obvious security reasons, it is critical for a product to have its debug interface locked before being released in the field. Secure Vault also provides a secure debug unlock function that allows authenticated access based on public key cryptography. This functionality is particularly useful for supporting failure analysis while maintaining confidentiality of IP and sensitive end-user data. For more information about this feature, see AN1190: Series 2 Secure Debug. 3.7.5 Differential Power Analysis (DPA) Countermeasures The AES and ECC accelerators have DPA countermeasures support. This makes it very expensive from a time and effort standpoint to use DPA to recover secret keys. 3.7.6 Secure Key Management with Physically Unclonable Function (PUF) Key material in Secure Vault High products is protected by "key wrapping" with a standardized symmetric encryption mechanism. This method has the advantage of protecting a virtually unlimited number of keys, limited only by the storage that is accessible by the Cor- tex-M33, which includes off-chip storage as well. The symmetric key used for this wrapping and unwrapping must be highly secure be- cause it can expose all other key materials in the system. The Secure Vault Key Management system uses a PUF to generate a persis- tent device-unique seed key on power up to dynamically generate this critical wrapping/unwrapping key which is only visible to the AES encryption engine and is not retained when the device loses power. EFR32MG29 Wireless SoC Family Data Sheet System Overview silabs.com | Building a more connected world. Rev. 1.1 | 14 3.7.7 Anti-Tamper Secure Vault High devices provide internal tamper protection which monitors parameters such as voltage, temperature, and electro- magnetic pulses as well as detecting tamper of the security sub-system itself. Additionally, 8 external configurable tamper pins support external tamper sources, such as enclosure tamper switches. For each tamper event, the user is able to select the severity of the tamper response ranging from an interrupt, to a reset, to destroying the PUF reconstruction data which will make all protected key materials un-recoverable and effectively render the device inoperable. The tamper system also has an internal resettable event counter with programmable trigger threshold and refresh periods to mitigate false positive tamper events. For more information about this feature, see AN1247: Anti-Tamper Protection Configuration and Use. 3.7.8 Secure Attestation Secure Vault High products support Secure Attestation, which begins with a secure identity that is created during the Silicon Labs man- ufacturing process. During device production, each device generates its own public/private keypair and securely stores the wrapped private key into immutable OTP memory and this key never leaves the device. The corresponding public key is extracted from the de- vice and inserted into a binary DER-encoded X.509 device certificate, which is signed into a Silicon Labs CA chain and then program- med back into the chip into an immutable OTP memory. The secure identity can be used to authenticate the chip at any time in the life of the product. The production certification chain can be requested remotely from the product. This certification chain can be used to verify that the device was authentically produced by Silicon Labs. The device unique public key is also bound to the device certificate in the certification chain. A challenge can be sent to the chip at any point in time to be signed by the device private key. The public key in the device certificate can then be used to verify the chal- lenge response, proving that the device has access to the securely-stored private key, which prevents counterfeit products or imperso- nation attacks. For more information about this feature, see AN1268: Authenticating Silicon Labs Devices Using Device Certificates. 3.7.9 External Tamper Detection (ETAMPDET) The ETAMPDET module enables detection of external tampering, such as unauthorized enclosure opening. ETAMPDET operates in all energy modes down to EM4. Up to two signals can be generated and monitored to identify external tamper events. When a tamper event occurs, an interrupt is generated to allow software to take system-appropriate actions. 3.8 Analog 3.8.1 Analog to Digital Converter (IADC) The IADC is a hybrid architecture combining techniques from both SAR and Delta-Sigma style converters. It has a resolution of 12 bits at 1 Msps and 16 bits at up to 76.9 ksps. Hardware oversampling reduces system-level noise over multiple front-end samples. The IADC includes integrated voltage reference options. Inputs are selectable from a wide range of sources, including pins configurable as either single-ended or differential. 3.8.2 Analog Comparator (ACMP) The ACMP is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is higher. Inputs are selected from among internal references and external pins. The tradeoff between response time and current consumption is configura- ble by software. Two 6-bit reference dividers allow for a wide range of internally programmable reference sources. The ACMP can also be used to monitor the supply voltage. An interrupt can be generated when the supply falls below or rises above the programmable threshold. EFR32MG29 Wireless SoC Family Data Sheet System Overview silabs.com | Building a more connected world. Rev. 1.1 | 15 3.9 Power The EFR32MG29 has an Energy Management Unit (EMU) and efficient integrated regulators to generate internal supply voltages. Only a single external supply voltage is required, from which all internal voltages are created. Devices are available with an integrated DC- DC buck or DC-DC boost regulator. The DC-DC buck regulator is capable of bucking higher voltages down to 1.8 V, while the DC-DC boost option boosts lower battery voltages up to a higher voltage. The DC-DC boost converter has adjustable output, from 1.8 to 2.4 V in 100 mV steps. If used in an application, the DC-DC regulator requires one external inductor and one external capacitor. The EFR32MG29 device family includes support for internal supply voltage scaling, as well as different power domain groups for pe- ripherals. These enhancements allow for further supply current reductions and lower overall power consumption. 3.9.1 Energy Management Unit (EMU) The EMU manages transitions of energy modes in the device. Each energy mode defines which peripherals and features are available and the amount of current the device consumes. The EMU can also be used to implement system-wide voltage scaling and turn off the power to unused RAM blocks to optimize the energy consumption in the target application. The DC-DC regulator operation is tightly integrated with the EMU. 3.9.2 Voltage Scaling The EFR32MG29 supports supply voltage scaling for the regulator powering DECOUPLE, with independent selections for EM0 / EM1 and EM2 / EM3. Voltage scaling helps to optimize the energy efficiency of the system by operating at lower voltages when possible. The EM0 / EM1 voltage scaling level defaults to VSCALE2, which allows the core to operate in active mode at full speed. The inter- mediate level, VSCALE1, allows operation in EM0 and EM1 at up to 40 MHz. The lowest level, VSCALE0, can be used to conserve power further in EM2 and EM3. The EMU will automatically switch the target voltage scaling level when transitioning between energy modes. 3.9.3 Buck or Boost DC-DC Converter Each device in the family includes either a buck DC-DC or boost DC-DC converter. The DC-DC converter covers a wide range of load currents, providing high efficiency in energy modes EM0, EM1, EM2 and EM3 for device and radio operation. RF noise mitigation allows operation of the DC-DC converter without significantly degrading sensitivity of radio components. It employs soft switching at boot and DC-DC regulating-to-bypass transitions to limit the max supply slew rate and mitigate inrush current. The buck DC-DC configuration provides up to 60 mA output current at 1.8 V from a 2.2 - 3.8 V supply in energy modes EM0,EM1, EM2, and EM3. An on-chip supply-monitor signals when the supply voltage is low to allow bypass of the regulator, and extend the operating range down to 1.8 V. In bypass mode, the DC-DC operation is shut down and the input supply is switched directly to the output. The bypass mode of the buck DC-DC may be enabled to allow the system to go into EM4 and save energy. An integrated Coulomb Counter may be used to monitor the energy flowing through the buck DC-DC. The boost DC-DC configuration has an input range of 1.2 to 1.7 V, an adjustable output range of 1.8 to 2.4 V, and up to 25 mA output current, enabling operation directly from single-cell low-voltage batteries. The boost DC-DC converter is operational in energy modes EM0, EM1, EM2, and EM3. It can be completely shut down using the dedicated BOOST_EN pin, saving system power during storage and shipping. BOOST_EN may also be used to re-enable the boost converter and power up the system. EFR32MG29 Wireless SoC Family Data Sheet System Overview silabs.com | Building a more connected world. Rev. 1.1 | 16 3.9.4 Power Domains Peripherals may exist on one of several independent power domains which are powered down to minimize supply current when not in use. Power domains are managed automatically by the EMU. The lowest-energy power domain is the "high-voltage" power domain (PDHV), which supports extremely low-energy infrastructure and peripherals. Circuits powered from PDHV are always on and available in all energy modes down to EM4. The next power domain is the low-power domain (PD0), which is further divided to power subsets of peripherals. All PD0 power do- mains are shut down in EM4. Circuits powered from PD0 power domains may be available in EM0, EM1, EM2, and EM3. Low-power domain A (PD0A) is the base power domain for EM2 and EM3 and will always remain on in EM0-EM3. It powers the most commonly used EM2 and EM3-capable peripherals and infrastructure required to operate in EM2 and EM3. Auxiliary PD0 power do- mains (PD0B, PD0C) power additional EM2 and EM3-capable peripherals on demand. If any peripherals on one of the auxiliary power domains is enabled, that power domain will be active in EM2 and EM3. Otherwise, the auxiliary PD0 power domains will be shut down to reduce current. The active power domain (PD1) powers the rest of the device circuitry, including the CPU core and EM0 / EM1 peripherals. PD1 is always powered on in EM0 and EM1. PD1 is always shut down in EM2, EM3, and EM4. Table 3.2 Peripheral Power Subdomains on page 17 shows the peripherals on the PDHV and PD0x domains. Any peripheral not lis- ted is on PD1. Table 3.2. Peripheral Power Subdomains Always On in EM2/EM3 Selectively On in EM2/3 PDHV1 PD0A PD0B PD0C LFRCO (Non-precision mode) RTCC LETIMER0 LFRCO (Precision Mode) LFXO FSRCO IADC0 BURTC WDOG0 ACMP0 RFSENSE I2C0 ULFRCO EUSART0 ETAMPDET PRS BURAM DEBUG GPIO Note: 1. Peripherals on PDHV are also available in EM4. 3.10 Reset Management Unit (RMU) The RMU is responsible for handling reset of the EFR32MG29. A wide range of reset sources are available, including several power supply monitors, pin reset, software-controlled reset, core lockup reset, and watchdog reset. EFR32MG29 Wireless SoC Family Data Sheet System Overview silabs.com | Building a more connected world. Rev. 1.1 | 17 3.11 Core and Memory 3.11.1 Processor Core The ARM Cortex-M processor includes a 32-bit RISC processor integrating the following features and tasks in the system: • ARM Cortex-M33 RISC processor achieving 1.50 Dhrystone MIPS/MHz • ARM TrustZone security technology • Embedded Trace Macrocell (ETM) for real-time trace and debug • Up to 1024 KB flash program memory • Up to 256 KB RAM data memory • Configuration and event handling of all modules • 2-pin Serial-Wire debug interface 3.11.2 Memory System Controller (MSC) The MSC is the program memory unit of the microcontroller. The flash memory is readable and writable from both the Cortex-M33 and LDMA. In addition to the main flash array where program code is normally written, the MSC provides an information block where addi- tional information, such as special user information or flash-lock bits, is stored. There is also a read-only page in the information block containing system and device calibration data. Read and write operations are supported in energy modes EM0 Active and EM1 Sleep. 3.11.3 Linked Direct Memory Access Controller (LDMA) The LDMA controller allows the system to perform memory operations independently of software. This reduces both energy consump- tion and software workload. The LDMA allows operations to be linked together and staged, enabling sophisticated operations to be im- plemented. EFR32MG29 Wireless SoC Family Data Sheet System Overview silabs.com | Building a more connected world. Rev. 1.1 | 18 3.12 Memory Map The EFR32MG29 memory map is shown in the following figure. RAM and flash sizes are for the largest memory configuration. M33 Peripherals 0xe00fffff 0xe0000000 0xfffffffe 0xe0100000 0xdfffffff 0xb0005000 FRCRAM (non-secure) 0xb0004fff 0xb0004000 SEQRAM (non-secure) 0xb0003fff 0xb0000000 0xafffffff 0xa0005000 FRCRAM (secure) 0xa0004fff 0xa0004000 SEQRAM (secure) 0xa0003fff 0xa0000000 0x9fffffff 0x60000000 Peripherals (non-secure) 0x5fffffff 0x50000000 Peripherals (secure) 0x4fffffff 0x40000000 RAM (DMEM) 0x2003ffff 0x20000000 Flash 0x1fffffff 0x08000000 0x3fffffff 0x20040000 0x07FFFFFF 0x00000000 FLASH 0x08000000 0x08100000 FLASH_USERDATA 0x0fe00000 0x0fe00400 FLASH_DEVINFO 0x0fe08000 0x0fe08400 FLASH_CHIPCONFIG 0x0fe08a00 0xe0000000 0xe0001000 0xe0002000 0xe0003000 0xe000e000 0xe000f000 0xe0040000 0xe0041000 0xe0042000 0xe00ff000 0xe0100000 Instrumentation Trace Macrocell (ITM) Data Watchpoint and Trace (DWT) Flash Patch and Breakpoint (FPB) System Control Space Trace Port Interface Unit (TPIU) Embedded Trace Macrocell (ETM) M33 ROM Table Figure 3.1. EFR32MG29 Memory Map — Core Peripherals and Code Space EFR32MG29 Wireless SoC Family Data Sheet System Overview silabs.com | Building a more connected world. Rev. 1.1 | 19 3.13 Configuration Summary The features of the EFR32MG29 are a subset of the feature set described in the device reference manual. The following table de- scribes device specific implementation of the features. Remaining modules support full configuration. Table 3.3. Configuration Summary Module Lowest Energy Mode Configuration I2C0 EM31 I2C1 EM1 IADC0 EM3 LETIMER0 EM21 PDM EM1 2-channel TIMER0 EM1 32-bit, 3-channels, +DTI TIMER1 EM1 32-bit, 3-channels, +DTI TIMER2 EM1 16-bit, 3-channels, +DTI TIMER3 EM1 16-bit, 3-channels, +DTI TIMER4 EM1 16-bit, 3-channels, +DTI EUSART0 EM1 - Full high-speed operation, all modes EM21 - Low-energy UART operation, 9600 Baud EM2 or EM31 - Low-energy SPI secondary receiver EUSART1 EM1 - Full high-speed operation, all modes USART0 EM1 +IrDA, +I2S, +SmartCard USART1 EM1 +IrDA, +I2S, +SmartCard Note: 1. EM2 and EM3 operation is only supported for digital peripheral I/O on Port A and Port B. All GPIO ports support digital peripheral operation in EM0 and EM1. EFR32MG29 Wireless SoC Family Data Sheet System Overview silabs.com | Building a more connected world. Rev. 1.1 | 20 4. Electrical Specifications 4.1 Electrical Characteristics All electrical parameters in all tables are specified under the following conditions, unless stated otherwise: • Typical values are based on TA=25 °C and all supplies at 3.0 V, by production test and/or technology characterization. • Radio performance numbers are measured in conducted mode, based on Silicon Laboratories reference designs using output pow- er-specific external RF impedance-matching networks for interfacing to a 50 Ω antenna. • Minimum and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature, unless stated otherwise. Power Supply Pin Dependencies Due to on-chip circuitry, some EFR32 power supply pins have a dependent relationship with one or more other power supply pins. These internal relationships between the external voltages applied to the various EFR32 supply pins are defined in the following list. Exceeding these constraints can result in damage to the device and/or increased current draw. Buck DC-DC or DC-DC not used • VREGVDD and DVDD • In systems using the DCDC converter, DVDD (the buck converter output) should not be driven externally and VREGVDD (the buck converter input) must be greater than DVDD (VREGVDD ≥ DVDD). • In systems not using the DCDC converter, DVDD must be shorted to VREGVDD on the PCB (VREGVDD = DVDD). • DVDD ≥ DECOUPLE • PAVDD ≥ RFVDD • AVDD, IOVDD: No dependency with each other or any other supply pin. Boost DC-DC • VBAT: DCDC converter input. Connect to recommended supply and LDCDC. • DVDD: DVDD is the boost converter output and should be bypassed with the recommended CDCDC, it should not be driven by an off-chip regulator. • DVDD ≥ DECOUPLE • PAVDD ≥ RFVDD • AVDD, IOVDD: No dependency with each other or any other supply pin EFR32MG29 Wireless SoC Family Data Sheet Electrical Specifications silabs.com | Building a more connected world. Rev. 1.1 | 21 4.2 Absolute Maximum Ratings Stresses above those listed in the following table may cause permanent damage to the device. This is a stress rating only and function- al operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 4.1. Absolute Maximum Ratings Parameter Symbol Test Condition Min Typ Max Unit Storage temperature range TSTG -50 — +150 °C Voltage on DVDD, AVDD, IOVDD, RFVDD, PAVDD or VREGVDD supply pins VDDMAX -0.3 — 3.8 V Voltage on VBAT supply pin VVBATMAX -0.3 — 3.8 V Junction temperature TJMAX -C grade — — 55 °C -I grade — — 125 °C Voltage ramp rate on any supply pin VDDRAMPMAX — — 1.0 V / μs Voltage on HFXO pins VHFXOPIN -0.3 — 1.2 V DC voltage on any GPIO pin VDIGPIN -0.3 — VIOVDD + 0.3 V DC voltage on RESETn pin1 VRESETn -0.3 — 3.8 V Input RF level on RF pins RF2G4_IO PRFMAX2G4 — — +10 dBm Absolute voltage on RF pin RF2G4_IO VMAX2G4 -0.3 — VPAVDD + 0.3 V Total current into VDD power lines IVDDMAX Source — — 200 mA Total current into VSS ground lines IVSSMAX Sink — — 200 mA Current per I/O pin IIOMAX Sink — — 50 mA Source — — 50 mA Current for all I/O pins IIOALLMAX Sink — — 200 mA Source — — 200 mA Note: 1. The RESETn pin has a pull-up device to the DVDD supply. For minimum leakage, RESETn should not exceed the voltage at DVDD. EFR32MG29 Wireless SoC Family Data Sheet Electrical Specifications silabs.com | Building a more connected world. Rev. 1.1 | 22 4.3 General Operating Conditions Table 4.2. General Operating Conditions Parameter Symbol Test Condition Min Typ Max Unit Operating ambient tempera- ture range TA -C temperature grade 1 -20 — +55 °C -I temperature grade 1 -40 — +125 °C VREGVDD operating supply voltage (Buck DCDC or DCDC not used) VVREGVDD Buck Mode DCDC in regulation, 60 mA load 2.2 3.0 3.8 V Buck Mode DCDC in bypass, 60 mA load 1.8 3.0 3.8 V DCDC not in use. DVDD external- ly shorted to VREGVDD 1.71 3.0 3.8 V VBAT operating supply volt- age (Boost DCDC) VVBAT Boost Mode DCDC in regulation 2 1.2 1.5 VOUT_BST - 0.1 V DVDD supply voltage VDVDD EM0/1 1.71 3.0 3.8 V EM2/3/4 3 1.71 3.0 3.8 V AVDD supply voltage VAVDD 1.71 3.0 3.8 V IOVDD0 operating supply voltage VIOVDD0 IOVDD0BODEN = 0 4 1.175 3.0 3.8 V IOVDD0BODEN = 1 4 1.71 3.0 3.8 V RFVDD operating supply voltage VRFVDD 1.71 3.0 VPAVDD V PAVDD operating supply voltage VPAVDD 1.71 3.0 3.8 V DECOUPLE output capaci- tor5 CDECOUPLE 1.0 μF ± 10% X8L capacitor used for performance characterization. 1.0 — 2.75 μF HCLK and core frequency fHCLK VSCALE2, MODE = WS1 — — 80 MHz VSCALE2, MODE = WS0 — — 40 MHz VSCALE1, MODE = WS0 — — 40 MHz PCLK frequency fPCLK VSCALE2 or VSCALE1 — — 40 MHz EM01 Group A clock fre- quency fEM01GRPACLK VSCALE2 — — 80 MHz VSCALE1 — — 40 MHz EM01 Group B clock fre- quency fEM01GRPBCLK VSCALE2 — — 80 MHz VSCALE1 — — 40 MHz EM01 Group C clock fre- quency fEM01GRPCCLK VSCALE2 — — 80 MHz VSCALE1 — — 40 MHz HCLK radio frequency6 fHCLKRADIO VSCALE2 or VSCALE1 — 38.4 — MHz External clock input fCLKIN VSCALE2 or VSCALE1 — — 40 MHz DPLL reference clock fDPLLREFCLK VSCALE2 or VSCALE1 — — 40 MHz EFR32MG29 Wireless SoC Family Data Sheet Electrical Specifications silabs.com | Building a more connected world. Rev. 1.1 | 23 Parameter Symbol Test Condition Min Typ Max Unit Note: 1. The device may operate continuously at the maximum allowable ambient TA rating as long as the absolute maximum TJMAX is not exceeded. For an application with significant power dissipation, the allowable TA may be lower than the maximum TA rating. TA = TJMAX - (THETAJA x PowerDissipation). Refer to the Absolute Maximum Ratings table and the Thermal Characteristics table for TJMAX and THETAJA. 2. The VBAT supply may be as high as the Boost DCDC output, but DCDC and RF performance specifications willl degrade. 3. The DVDD supply is monitored by the DVDD BOD in EM0/1 and the LE DVDD BOD in EM2/3/4. 4. The IOVDD BOD enable bit is in the EMU_BOD3SENSE register. The BOD is disabled on reset. 5. Murata GCM21BL81C105KA58L used for performance characterization. Actual capacitor values can be significantly de-rated from their specified nominal value by the rated tolerance, as well as the application's AC voltage, DC bias, and temperature. The minimum capacitance counting all error sources should be no less than 0.6 μF. 6. The recommended radio crystal frequency is 38.4 MHz and all radio performance is specified at this frequency. See HFXO speci- fications for more detail on crystal tolerance. EFR32MG29 Wireless SoC Family Data Sheet Electrical Specifications silabs.com | Building a more connected world. Rev. 1.1 | 24 4.4 Buck-Mode DC-DC Converter Test conditions: LDCDC = 2.2 μH, CDCDC = 4.7 μF, VVREGVDD = 3.0 V, VOUT = 1.8 V, IPKVAL in EM0/1 modes is set to 150 mA, and in EM2/3 modes is set to 90 mA, unless otherwise indicated. Table 4.3. Buck-Mode DC-DC Converter Parameter Symbol Test Condition Min Typ Max Unit Input voltage range at VREGVDD pin VVREGVDD DCDC in regulation, ILOAD = 60 mA, EM0/EM1 mode 2.2 3.0 3.8 V DCDC in regulation, ILOAD = 5 mA, EM0/EM1 or EM2/EM3 mode 1.8 3.0 3.8 V Bypass mode 1.8 3.0 3.8 V Regulated output voltage VOUT — 1.8 — V Regulation DC accuracy ACCDC VVREGVDD ≥ 2.2 V, Steady state in EM0/EM1 mode or EM2/EM3 mode -2.5 — 3.3 % Regulation total accuracy ACCTOT With mode transitions between EM0/EM1 and EM2/EM3 modes -5 — 7 % Steady-state output ripple VR ILOAD = 20 mA in EM0/EM1 mode — 14.3 — mVpp DC line regulation VREG ILOAD = 60 mA in EM0/EM1 mode, VVREGVDD ≥ 2.2 V — 5.5 — mV/V DC load regulation IREG Load current between 100 μA and 60 mA in EM0/EM1 mode — 0.27 — mV/mA Efficiency EFF Load current between 100 μA and 60 mA in EM0/EM1 mode, or be- tween 10 μA and 5 mA in EM2/EM3 mode — 91 — % Output load current1 ILOAD EM0/EM1 mode, DCDC in regula- tion — — 60 mA EM2/EM3 mode, DCDC in regula- tion — — 5 mA Bypass mode — — 60 mA Nominal output capacitor CDCDC 4.7 μF ± 10% X7R capacitor used for performance characterization2 4.7 — 10 μF Nominal inductor LDCDC ± 20% tolerance — 2.2 — μH Nominal input capacitor CIN CDCDC — — μF Resistance in bypass mode RBYP Bypass switch from VREGVDD to DVDD, VVREGVDD = 1.8 V — 1.75 3 Ω Powertrain PFET switch from VREGVDD to VREGSW, VVREGVDD = 1.8 V — 0.86 1.5 Ω Supply monitor threshold programming range VCMP_RNG Programmable in 0.1 V steps 2.0 — 2.3 V Supply monitor threshold ac- curacy VCMP_ACC Supply falling edge trip point -5 — 5 % EFR32MG29 Wireless SoC Family Data Sheet Electrical Specifications silabs.com | Building a more connected world. Rev. 1.1 | 25 Parameter Symbol Test Condition Min Typ Max Unit Supply monitor threshold hysteresis VCMP_HYST Positive hysteresis on the supply rising edge referred to the falling edge trip point — 4 — % Supply monitor response time tCMP_DELAY Supply falling edge at -100 mV / μs — 0.6 — μs Note: 1. ILOAD is the total current sourced by the DCDC, including on-chip and off-chip circuits powered from the DVDD supply rail. 2. Actual capacitor values can be significantly de-rated from their specified nominal value by the rated tolerance, as well as the ap- plication's AC voltage, DC bias, and temperature. The minimum capacitance counting all error sources should be no less than 2.4 μF. EFR32MG29 Wireless SoC Family Data Sheet Electrical Specifications silabs.com | Building a more connected world. Rev. 1.1 | 26 4.4.1 Buck DC-DC Operating Limits The maximum supported voltage on the VREGVDD supply pin is limited under certain conditions. Maximum input voltage is a function of temperature and the average load current over a 10-year lifetime. Figure 4.1 Lifetime Average Load Current limit vs. Maximum Input Voltage on page 27 shows the safe operating region under specific conditions. Exceeding this safe operating range may impact the reliability and performance of the DC-DC converter. The average load current for an application can typically be determined by examining the current profile during the time the device is powered. For example, a continuously powered application that sleeps 99% of the time, consumes 2 uA while asleep and 10 mA during the 1% it is active, with an average lifetime load current of about 102 uA. Average Lifetime I LOAD (mA) Maximum VVREGVDD (V) 60 5 3.3 3.8 Tj ≤ 125 °C Figure 4.1. Lifetime Average Load Current limit vs. Maximum Input Voltage The minimum input voltage for the DC-DC in EM0/EM1 mode is a function of the maximum load current, and the peak current setting. Figure 4.2 Transient Maximum Load Current vs. Minimum Input Voltage on page 27 shows the max load current vs. input voltage for different DC-DC peak inductor current settings. Maximum I LOAD (mA) Minimum VVREGVDD (V) 60 5 2.2 1.8 36 IPEAK = 150 mA IPEAK = 90 mA Figure 4.2. Transient Maximum Load Current vs. Minimum Input Voltage EFR32MG29 Wireless SoC Family Data Sheet Electrical Specifications silabs.com | Building a more connected world. Rev. 1.1 | 27 4.5 Boost-Mode DC-DC Converter Test conditions: LDCDC = 2.2 μH, CDCDC = 10 μF, VVBAT = 1.5 V, VOUT = 1.8 V, IPKVAL in EM0/1 modes is set to 180 mA, and in EM2/3 modes is set to 150 mA, unless otherwise indicated. Table 4.4. Boost-Mode DC-DC Converter Parameter Symbol Test Condition Min Typ Max Unit Input voltage range at VBAT pin VVBAT CLOAD = 10 μF 1.2 — 1.7 V Nominal regulated output voltage VOUT_BST Adjustable in 100 mV increments 1.8 — 2.4 V Regulation DC accuracy ACCDC 1.2 V ≤ VVBAT ≤ 1.7 V, Steady state in EM0/EM1 mode or EM2/EM3 mode -2 — 2.5 % Regulation total accuracy ACCTOT With mode transitions between EM0/EM1 and EM2/EM3 modes -5 — 7 % Steady-state output ripple VR ILOAD = 20 mA in EM0/EM1 mode — 15 — mVpp DC line regulation VREG ILOAD = 25 mA in EM0/EM1 mode, 1.2 V ≤ VVBAT ≤ 1.6 V — 15 — mV/V DC load regulation IREG Load current between 100 μA and MAX(ILOAD) in EM0/EM1 mode — -0.25 — mV/mA Efficiency EFF Load current between 100 μA and MAX(ILOAD) mA in EM0/EM1 mode, or between 10 μA and 5 mA in EM2/EM3 mode — 91 — % Output load current1 ILOAD EM0/EM1 mode, DCDC in regula- tion, VOUT = 1.8 V, VVBAT = 1.2 V — — 25 mA EM2/EM3 mode, DCDC in regula- tion, VOUT = 1.8 V, VVBAT = 1.2 V — — 5 mA External load during startup2 ILOAD_START Off-chip load applied at DVDD supply rail — — 0.5 mA Peak current during startup IPEAK_START CLOAD = 10 μF — — 10 mA Nominal output capacitor CDCDC 10 μF ± 10% X8L capacitor used for performance characterization3 7.5 10 — μF Nominal inductor LDCDC ± 20% tolerance — 2.2 — μH Nominal input capacitor CIN 4.7 — — μF Time to switch from EM2/3 mode to EM0/1 mode4 tMODE_SWITCH — 16 32 μs Input high voltage on BOOST_EN VIH_BOOST_EN 0.8 * VBAT — — V Input low voltage on BOOST_EN VIL_BOOST_EN — — 0.3 * VBAT V Hysteresis of input voltage on BOOST_EN VHYST_BOOST_E N 0.03 * VBAT — — V Time from BOOST_EN high to output regulation at 1.8 V tSTART With 500 μA off-chip ILOAD_START on DVDD — 8 20 ms EFR32MG29 Wireless SoC Family Data Sheet Electrical Specifications silabs.com | Building a more connected world. Rev. 1.1 | 28 Parameter Symbol Test Condition Min Typ Max Unit Peak output voltage during startup (during tSTART) VSTART — 2.35 2.8 V Note: 1. ILOAD is the total current sourced by the DCDC, including on-chip and off-chip circuits powered from the DVDD supply rail. Maxi- mum output load current is a function of input and output voltage. 2. ILOAD_START is the allowable current sourced by the DCDC during startup to off-chip circuits powered from the DVDD supply rail. 3. Actual capacitor values can be significantly de-rated from their specified nominal value by the rated tolerance, as well as the ap- plication's AC voltage, DC bias, and temperature. The minimum capacitance counting all error sources should be no less than 6.7 μF. 4. Mode switch is initiated when a wake event is recognized and occurs in parallel to the normal system wake time. During the mode switch, ILOAD should be limited to 20 mA or less. 4.6 Coulomb Counter Calibration Load (Buck DC-DC Only) Table 4.5. Coulomb Counter Calibration Load (Buck DC-DC Only) Parameter Symbol Test Condition Min Typ Max Unit Operating temperature range TCCLOAD -20 — 70 °C Load current accuracy vs. production measurement1 ILOAD_ACC CCLVL = LOAD2 (1.0 mA nomi- nal) -9 — 9 % CCLVL = LOAD7 (8.0 mA nomi- nal) -10 — 10 % Note: 1. Calibration load currents vary from part-to-part. The magnitude of the calibration load currents at 25 °C are measured in produc- tion on each device, and the measurement is written into DEVINFO space in the CCLOADxx locations. Accuracy is specified rela- tive to the measured value across TCCLOAD. 4.7 Thermal Characteristics Table 4.6. Thermal Characteristics Package Board Parameter Symbol Test Condition Value Unit 40QFN (5x5mm) JEDEC - High Thermal Cond. (2s2p)1 Thermal Resistance, Junction to Ambient ΘJA Still Air 27.1 °C/W Thermal Resistance, Junction to Board ѰJB 7.2 °C/W Thermal Resistance, Junction to Top Center ѰJT 0.27 °C/W Thermal Resistance, Junction to Board ΘJB 15.5 °C/W Note: 1. Based on 4 layer PCB with dimension 3" x 4.5", PCB Thickness of 1.6 mm, per JEDEC. PCB Center Land with 9 Via to top inter- nal plane of PCB. EFR32MG29 Wireless SoC Family Data Sheet Electrical Specifications silabs.com | Building a more connected world. Rev. 1.1 | 29 4.8 Current Consumption 4.8.1 MCU Current Consumption Using Buck DC-DC at 3.0 V VREGVDD Input Unless otherwise indicated, typical conditions are: VREGVDD = 3.0 V. AVDD = DVDD = IOVDD = RFVDD = PAVDD = 1.8 V from DC- DC. Voltage scaling level = VSCALE1. TA = 25 °C. Minimum and maximum values in this table represent the worst conditions across process variation at TA = 25 °C. Table 4.7. MCU Current Consumption Using Buck DC-DC at 3.0 V VREGVDD Input Parameter Symbol Test Condition Min Typ Max Unit Current consumption in EM0 mode with all peripherals dis- abled IACTIVE 76.8 MHz HFRCO w/ DPLL refer- enced to 38.4 MHz crystal, CPU running Prime from flash, VSCALE2 — 32 — μA/MHz 76.8 MHz HFRCO w/ DPLL refer- enced to 38.4 MHz crystal, CPU running while loop from flash, VSCALE2 — 30 — μA/MHz 76.8 MHz HFRCO w/ DPLL refer- enced to 38.4 MHz crystal, CPU running CoreMark loop from flash, VSCALE2 — 40 — μA/MHz 38.4 MHz crystal, CPU running Prime from flash — 33 — μA/MHz 38.4 MHz crystal, CPU running while loop from flash — 31 — μA/MHz 38.4 MHz crystal, CPU running CoreMark loop from flash — 41 — μA/MHz 38 MHz HFRCO, CPU running while loop from flash — 27 — μA/MHz 26 MHz HFRCO, CPU running while loop from flash — 30 — μA/MHz 16 MHz HFRCO, CPU running while loop from flash — 36 — μA/MHz 1 MHz HFRCO, CPU running while loop from flash — 283 — μA/MHz Current consumption in EM1 mode with all peripherals dis- abled IEM1 76.8 MHz HFRCO w/ DPLL refer- enced to 38.4 MHz crystal, VSCALE2 — 20 — μA/MHz 38.4 MHz crystal — 21 — μA/MHz 38 MHz HFRCO — 17 — μA/MHz 26 MHz HFRCO — 20 — μA/MHz 16 MHz HFRCO — 26 — μA/MHz 1 MHz HFRCO — 273 — μA/MHz Current consumption in EM2 mode, VSCALE1 IEM2_VS1 256 KB RAM retention and RTC running from LFRCO — 4.6 — μA 16 KB RAM retention and RTC running from LFRCO — 1.9 — μA EFR32MG29 Wireless SoC Family Data Sheet Electrical Specifications silabs.com | Building a more connected world. Rev. 1.1 | 30 Parameter Symbol Test Condition Min Typ Max Unit Current consumption in EM2 mode, VSCALE0 IEM2_VS 256 KB RAM retention and RTC running from LFXO — 3.4 — μA 256 KB RAM retention and RTC running from LFRCO — 3.4 — μA 192 KB RAM retention and RTC running from LFXO — 2.9 — μA 192 KB RAM retention and RTC running from LFRCO — 2.9 — μA 192 KB RAM retention with RTC, BURTC, and WDOG running from LFRCO in precision mode — 3.3 — μA 32 KB RAM retention and RTC running from LFXO — 1.7 — μA 32 KB RAM retention and RTC running from LFRCO in precision mode — 2.0 — μA 16 KB RAM retention and RTC running from LFXO — 1.5 — μA 16 KB RAM retention and RTC running from LFRCO — 1.5 — μA 16 KB RAM retention and RTC running from LFXO, Radio RAM and CPU cache not retained — 1.3 — μA 16 KB RAM retention and RTC running from LFXO, CPU cache not retained — 1.5 — μA 16 KB RAM retention and RTC running from LFXO, Radio RAM, CPU cache, and EM0/1 peripheral states not retained — 1.3 — μA Current consumption in EM3 mode, VSCALE0 IEM3_VS 16 KB RAM retention and RTC running from ULFRCO — 1.35 — μA Change in current consump- tion for retained RAM bank in EM2 or EM3 IEM23_RAM Per 16 KB RAM bank — 0.124 — μA Additional current in EM2 or EM3 when any peripheral in PD0B is enabled1 IPD0B_VS — 1.8 — μA Note: 1. Extra current consumed by power domain. Does not include current associated with the enabled peripherals. See 3.9.4 Power Domains for a list of the peripherals in each power domain. EFR32MG29 Wireless SoC Family Data Sheet Electrical Specifications silabs.com | Building a more connected world. Rev. 1.1 | 31 4.8.2 MCU Current Consumption Using Boost DC-DC at 1.5 V VBAT Input Unless otherwise indicated, typical conditions are: VBAT = 1.5 V, AVDD = DVDD = IOVDD = RFVDD = PAVDD = 1.8 V from DC-DC. Voltage scaling level = VSCALE1. TA = 25 °C. Minimum and maximum values in this table represent the worst conditions across proc- ess variation at TA = 25 °C. Table 4.8. MCU Current Consumption Using Boost DC-DC at 1.5 V VBAT Input Parameter Symbol Test Condition Min Typ Max Unit Current consumption in EM0 mode with all peripherals dis- abled IACTIVE 76.8 MHz HFRCO w/ DPLL refer- enced to 38.4 MHz crystal, CPU running Prime from flash, VSCALE2 — 50 — μA/MHz 76.8 MHz HFRCO w/ DPLL refer- enced to 38.4 MHz crystal, CPU running while loop from flash, VSCALE2 — 47 — μA/MHz 76.8 MHz HFRCO w/ DPLL refer- enced to 38.4 MHz crystal, CPU running CoreMark loop from flash, VSCALE2 — 62 — μA/MHz 38.4 MHz crystal, CPU running Prime from flash — 52 — μA/MHz 38.4 MHz crystal, CPU running while loop from flash — 49 — μA/MHz 38.4 MHz crystal, CPU running CoreMark loop from flash — 64 — μA/MHz 38 MHz HFRCO, CPU running while loop from flash — 41 — μA/MHz 26 MHz HFRCO, CPU running while loop from flash — 45 — μA/MHz 16 MHz HFRCO, CPU running while loop from flash — 55 — μA/MHz 1 MHz HFRCO, CPU running while loop from flash — 429 — μA/MHz Current consumption in EM1 mode with all peripherals dis- abled IEM1 76.8 MHz HFRCO w/ DPLL refer- enced to 38.4 MHz crystal, VSCALE2 — 33 — μA/MHz 38.4 MHz crystal — 35 — μA/MHz 38 MHz HFRCO — 27 — μA/MHz 26 MHz HFRCO — 31 — μA/MHz 16 MHz HFRCO — 41 — μA/MHz 1 MHz HFRCO — 415 — μA/MHz Current consumption in EM2 mode, VSCALE1 IEM2_VS1 256 KB RAM retention and RTC running from LFRCO — 5.9 — μA 16 KB RAM retention and RTC running from LFRCO — 2.8 — μA EFR32MG29 Wireless SoC Family Data Sheet Electrical Specifications silabs.com | Building a more connected world. Rev. 1.1 | 32 Parameter Symbol Test Condition Min Typ Max Unit Current consumption in EM2 mode, VSCALE0 IEM2_VS 256 KB RAM retention and RTC running from LFXO — 4.3 — μA 256 KB RAM retention and RTC running from LFRCO — 4.4 — μA 192 KB RAM retention and RTC running from LFXO — 3.7 — μA 192 KB RAM retention and RTC running from LFRCO — 3.8 — μA 192 KB RAM retention with RTC, BURTC, and WDOG running from LFRCO in precision mode — 4.6 — μA 32 KB RAM retention and RTC running from LFXO — 2.3 — μA 32 KB RAM retention and RTC running from LFRCO in precision mode — 3.0 — μA 16 KB RAM retention and RTC running from LFXO — 2.2 — μA 16 KB RAM retention and RTC running from LFRCO — 2.2 — μA 16 KB RAM retention and RTC running from LFXO, Radio RAM and CPU cache not retained — 1.9 — μA 16 KB RAM retention and RTC running from LFXO, CPU cache not retained — 2.1 — μA 16 KB RAM retention and RTC running from LFXO, Radio RAM, CPU cache, and EM0/1 peripheral states not retained — 1.9 — μA Current consumption in EM3 mode, VSCALE0 IEM3_VS 16 KB RAM retention and RTC running from ULFRCO — 1.9 — μA Current with Boost DCDC shut down (BOOST_EN = 0) ISHDN IOVDD, AVDD, RFVDD, and PAVDD connected to DVDD (un- powered) — 18 30 nA IOVDD powered. AVDD, RFVDD, and PAVDD connected to DVDD (unpowered) — 36 50 nA Current consumption during reset IRST Hard pin reset held — 516 — μA Additional current in EM2 or EM3 when any peripheral in PD0B is enabled1 IPD0B_VS — 2.1 — μA Change in current consump- tion for retained RAM bank in EM2 or EM3 IEM23_RAM Per 16 KB RAM bank — 0.143 — μA Note: 1. Extra current consumed by power domain. Does not include current associated with the enabled peripherals. See 3.9.4 Power Domains for a list of the peripherals in each power domain. EFR32MG29 Wireless SoC Family Data Sheet Electrical Specifications silabs.com | Building a more connected world. Rev. 1.1 | 33 4.8.3 MCU Current Consumption at 3.0 V Unless otherwise indicated, typical conditions are: AVDD = DVDD = IOVDD = RFVDD = PAVDD = VREGVDD = 3.0 V. DC-DC not used. Voltage scaling level = VSCALE1. TA = 25 °C. Minimum and maximum values in this table represent the worst conditions across process variation at TA = 25 °C. Table 4.9. MCU Current Consumption at 3.0 V Parameter Symbol Test Condition Min Typ Max Unit Current consumption in EM0 mode with all peripherals dis- abled IACTIVE 76.8 MHz HFRCO w/ DPLL refer- enced to 38.4 MHz crystal, CPU running Prime from flash, VSCALE2 — 47 — μA/MHz 76.8 MHz HFRCO w/ DPLL refer- enced to 38.4 MHz crystal, CPU running while loop from flash, VSCALE2 — 44 — μA/MHz 76.8 MHz HFRCO w/ DPLL refer- enced to 38.4 MHz crystal, CPU running CoreMark loop from flash, VSCALE2 — 59 — μA/MHz 38.4 MHz crystal, CPU running Prime from flash — 48 — μA/MHz 38.4 MHz crystal, CPU running while loop from flash — 45 — μA/MHz 38.4 MHz crystal, CPU running CoreMark loop from flash — 60 — μA/MHz 38 MHz HFRCO, CPU running while loop from flash — 39 81 μA/MHz 26 MHz HFRCO, CPU running while loop from flash — 43 — μA/MHz 16 MHz HFRCO, CPU running while loop from flash — 53 — μA/MHz 1 MHz HFRCO, CPU running while loop from flash — 408 1960 μA/MHz Current consumption in EM1 mode with all peripherals dis- abled IEM1 76.8 MHz HFRCO w/ DPLL refer- enced to 38.4 MHz crystal, VSCALE2 — 29 — μA/MHz 38.4 MHz crystal — 31 — μA/MHz 38 MHz HFRCO — 25 67 μA/MHz 26 MHz HFRCO — 29 — μA/MHz 16 MHz HFRCO — 38 — μA/MHz 1 MHz HFRCO — 393 1950 μA/MHz Current consumption in EM2 mode, VSCALE1 IEM2_VS1 256 KB RAM retention and RTC running from LFRCO — 6.6 — μA 16 KB RAM retention and RTC running from LFRCO — 2.7 — μA EFR32MG29 Wireless SoC Family Data Sheet Electrical Specifications silabs.com | Building a more connected world. Rev. 1.1 | 34 Parameter Symbol Test Condition Min Typ Max Unit Current consumption in EM2 mode, VSCALE0 IEM2_VS 256 KB RAM retention and RTC running from LFXO — 4.8 — μA 256 KB RAM retention and RTC running from LFRCO — 4.8 16 μA 192 KB RAM retention and RTC running from LFXO — 4.1 — μA 192 KB RAM retention and RTC running from LFRCO — 4.1 — μA 192 KB RAM retention with RTC, BURTC, and WDOG running from LFRCO in precision mode — 4.7 — μA 32 KB RAM retention and RTC running from LFXO — 2.3 — μA 32 KB RAM retention and RTC running from LFRCO in precision mode — 2.8 — μA 16 KB RAM retention and RTC running from LFXO — 2.1 — μA 16 KB RAM retention and RTC running from LFRCO — 2.1 — μA 16 KB RAM retention and RTC running from LFXO, Radio RAM and CPU cache not retained — 1.7 — μA 16 KB RAM retention and RTC running from LFXO, CPU cache not retained — 2.0 — μA 16 KB RAM retention and RTC running from LFXO, Radio RAM, CPU cache, and EM0/1 peripheral states not retained — 1.7 — μA Current consumption in EM3 mode, VSCALE0 IEM3_VS 16 KB RAM retention and RTC running from ULFRCO — 1.8 6 μA Change in current consump- tion for retained RAM bank in EM2 or EM3 IEM23_RAM Per 16 KB RAM bank — 0.179 — μA Current consumption in EM4 mode IEM4 No BURTC, no LF oscillator — 0.16 0.4 μA BURTC with LFXO — 0.52 — μA Current consumption during reset IRST Hard pin reset held — 536 — μA Additional current in EM2 or EM3 when any peripheral in PD0B is enabled1 IPD0B_VS — 2.7 — μA Note: 1. Extra current consumed by power domain. Does not include current associated with the enabled peripherals. See 3.9.4 Power Domains for a list of the peripherals in each power domain. EFR32MG29 Wireless SoC Family Data Sheet Electrical Specifications silabs.com | Building a more connected world. Rev. 1.1 | 35 4.8.4 MCU Current Consumption at 1.8 V Unless otherwise indicated, typical conditions are: AVDD = DVDD = IOVDD = RFVDD = PAVDD = VREGVDD = 1.8 V. DC-DC not used. Voltage scaling level = VSCALE1. TA = 25 °C. Minimum and maximum values in this table represent the worst conditions across process variation at TA = 25 °C. Table 4.10. MCU Current Consumption at 1.8 V Parameter Symbol Test Condition Min Typ Max Unit Current consumption in EM0 mode with all peripherals dis- abled IACTIVE 76.8 MHz HFRCO w/ DPLL refer- enced to 38.4 MHz crystal, CPU running Prime from flash, VSCALE2 — 46 — μA/MHz 76.8 MHz HFRCO w/ DPLL refer- enced to 38.4 MHz crystal, CPU running while loop from flash, VSCALE2 — 44 — μA/MHz 76.8 MHz HFRCO w/ DPLL refer- enced to 38.4 MHz crystal, CPU running CoreMark loop from flash, VSCALE2 — 59 — μA/MHz 38.4 MHz crystal, CPU running Prime from flash — 47 — μA/MHz 38.4 MHz crystal, CPU running while loop from flash — 45 — μA/MHz 38.4 MHz crystal, CPU running CoreMark loop from flash — 60 — μA/MHz 38 MHz HFRCO, CPU running while loop from flash — 39 — μA/MHz 26 MHz HFRCO, CPU running while loop from flash — 43 — μA/MHz 16 MHz HFRCO, CPU running while loop from flash — 52 — μA/MHz 1 MHz HFRCO, CPU running while loop from flash — 405 — μA/MHz Current consumption in EM1 mode with all peripherals dis- abled IEM1 76.8 MHz HFRCO w/ DPLL refer- enced to 38.4 MHz crystal, VSCALE2 — 29 — μA/MHz 38.4 MHz crystal — 31 — μA/MHz 38 MHz HFRCO — 24 — μA/MHz 26 MHz HFRCO — 29 — μA/MHz 16 MHz HFRCO — 38 — μA/MHz 1 MHz HFRCO — 391 — μA/MHz Current consumption in EM2 mode, VSCALE1 IEM2_VS1 256 KB RAM retention and RTC running from LFRCO — 6.5 — μA 16 KB RAM retention and RTC running from LFRCO — 2.7 — μA EFR32MG29 Wireless SoC Family Data Sheet Electrical Specifications silabs.com | Building a more connected world. Rev. 1.1 | 36 Parameter Symbol Test Condition Min Typ Max Unit Current consumption in EM2 mode, VSCALE0 IEM2_VS 256 KB RAM retention and RTC running from LFXO — 4.7 — μA 256 KB RAM retention and RTC running from LFRCO — 4.7 — μA 192 KB RAM retention and RTC running from LFXO — 4.0 — μA 192 KB RAM retention and RTC running from LFRCO — 4.0 — μA 192 KB RAM retention with RTC, BURTC, and WDOG running from LFRCO in precision mode — 4.7 — μA 32 KB RAM retention and RTC running from LFXO — 2.2 — μA 32 KB RAM retention and RTC running from LFRCO in precision mode — 2.8 — μA 16 KB RAM retention and RTC running from LFXO — 2.1 — μA 16 KB RAM retention and RTC running from LFRCO — 2.0 — μA 16 KB RAM retention and RTC running from LFXO, Radio RAM and CPU cache not retained — 1.7 — μA 16 KB RAM retention and RTC running from LFXO, CPU cache not retained — 2.0 — μA 16 KB RAM retention and RTC running from LFXO, Radio RAM, CPU cache, and EM0/1 peripheral states not retained — 1.7 — μA Current consumption in EM3 mode, VSCALE0 IEM3_VS 16 KB RAM retention and RTC running from ULFRCO — 1.8 — μA Change in current consump- tion for retained RAM bank in EM2 or EM3 IEM23_RAM Per 16 KB RAM bank — 0.179 — μA Current consumption in EM4 mode IEM4 No BURTC, no LF oscillator — 0.12 — μA BURTC with LFXO — 0.44 — μA Current consumption during reset IRST Hard pin reset held — 447.31 — μA Additional current in EM2 or EM3 when any peripheral in PD0B is enabled1 IPD0B_VS — 2.7 — μA Note: 1. Extra current consumed by power domain. Does not include current associated with the enabled peripherals. See 3.9.4 Power Domains for a list of the peripherals in each power domain. EFR32MG29 Wireless SoC Family Data Sheet Electrical Specifications silabs.com | Building a more connected world. Rev. 1.1 | 37 4.8.5 Radio Current Consumption at 3.0 V Using Buck-Mode DCDC RF current consumption measured with RHCLK = 38.4 MHz, and all MCU peripherals disabled. Unless otherwise indicated, typical con- ditions are: VREGVDD = 3.0 V. AVDD = DVDD = IOVDD = RFVDD = PAVDD = 1.8 V powered from DCDC. TA = 25 °C. Minimum and maximum values in this table represent the worst conditions across process variation at TA = 25 °C. Table 4.11. Radio Current Consumption at 3.0 V Using Buck-Mode DCDC Parameter Symbol Test Condition Min Typ Max Unit Current consumption in re- ceive mode, active packet reception IRX_ACTIVE 125 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1P (Radio clocks only) — 3.7 — mA 125 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1 — 4 — mA 125 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE2, EM1 — 4.2 — mA 500 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1P (Radio clocks only) — 3.8 — mA 500 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1 — 4.1 — mA 500 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE2, EM1 — 4.3 — mA 1 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1P (Radio clocks only) — 3.6 — mA 1 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1 — 3.8 — mA 1 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE2, EM1 — 4 — mA 2 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1P (Radio clocks only) — 4 — mA 2 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1 — 4.2 — mA 2 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE2, EM1 — 4.5 — mA 802.15.4 receiving frame, f = 2.4 GHz, VSCALE1, EM1P (Radio clocks only) — 4.1 — mA 802.15.4 receiving frame, f = 2.4 GHz, VSCALE1, EM1 — 4.4 — mA 802.15.4 receiving frame, f = 2.4 GHz, VSCALE2, EM1 — 4.6 — mA EFR32MG29 Wireless SoC Family Data Sheet Electrical Specifications silabs.com | Building a more connected world. Rev. 1.1 | 38 Parameter Symbol Test Condition Min Typ Max Unit Current consumption in re- ceive mode, listening for packet IRX_LISTEN 125 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1P (Radio clocks only) — 3.8 — mA 125 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1 — 4.1 — mA 125 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE2, EM1 — 4.3 — mA 500 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1P (Radio clocks only) — 3.8 — mA 500 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1 — 4.1 — mA 500 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE2, EM1 — 4.3 — mA 1 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1P (Radio clocks only) — 3.6 — mA 1 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1 — 3.9 — mA 1 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE2, EM1 — 4 — mA 2 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1P (Radio clocks only) — 4 — mA 2 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1 — 4.3 — mA 2 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE2, EM1 — 4.5 — mA 802.15.4 receiving frame, f = 2.4 GHz, VSCALE1, EM1P (Radio clocks only) — 4.3 — mA 802.15.4 receiving frame, f = 2.4 GHz, VSCALE1, EM1 — 4.6 — mA 802.15.4 receiving frame, f = 2.4 GHz, VSCALE2, EM1 — 4.9 — mA EFR32MG29 Wireless SoC Family Data Sheet Electrical Specifications silabs.com | Building a more connected world. Rev. 1.1 | 39 Parameter Symbol Test Condition Min Typ Max Unit Current consumption in transmit mode ITX f = 2.4 GHz, CW, 0 dBm PA, 0 dBm output power, VSCALE1, EM1P (Radio clocks only) — 4 — mA f = 2.4 GHz, CW, High-power PA, 0 dBm output power, VSCALE1, EM1P (Radio clocks only) — 5.6 — mA f = 2.4 GHz, CW, High-power PA, 4 dBm output power, VSCALE1, EM1P (Radio clocks only) — 7.4 — mA f = 2.4 GHz, CW, High-power PA, 6 dBm output power, VSCALE1, EM1P (Radio clocks only) — 9 — mA f = 2.4 GHz, CW, High-power PA, 8 dBm output power, VSCALE1, EM1P (Radio clocks only) — 11 — mA f = 2.4 GHz, CW, 0 dBm PA, 0 dBm output power, VSCALE1, EM1 — 4.3 — mA f = 2.4 GHz, CW, High-power PA, 0 dBm output power, VSCALE1, EM1 — 5.9 — mA f = 2.4 GHz, CW, High-power PA, 4 dBm output power, VSCALE1, EM1 — 7.6 — mA f = 2.4 GHz, CW, High-power PA, 6 dBm output power, VSCALE1, EM1 — 9.4 — mA f = 2.4 GHz, CW, High-power PA, 8 dBm output power, VSCALE1, EM1 — 11.3 — mA f = 2.4 GHz, CW, 0 dBm PA, 0 dBm output power, VSCALE2, EM1 — 4.4 — mA f = 2.4 GHz, CW, High-power PA, 0 dBm output power, VSCALE2, EM1 — 6 — mA f = 2.4 GHz, CW, High-power PA, 4 dBm output power, VSCALE2, EM1 — 7.8 — mA f = 2.4 GHz, CW, High-power PA, 6 dBm output power, VSCALE2, EM1 — 9.4 — mA f = 2.4 GHz, CW, High-power PA, 8 dBm output power, VSCALE2, EM1 — 11.4 — mA EFR32MG29 Wireless SoC Family Data Sheet Electrical Specifications silabs.com | Building a more connected world. Rev. 1.1 | 40 4.8.6 Radio Current Consumption at 1.5 V Using Boost-Mode DCDC RF current consumption measured with RHCLK = 38.4 MHz, and all MCU peripherals disabled. Unless otherwise indicated, typical con- ditions are: VBAT = 1.5 V, AVDD = DVDD = IOVDD = RFVDD = PAVDD = 1.8 V powered from DCDC. TA = 25 °C. Minimum and maximum values in this table represent the worst conditions across process variation at TA = 25 °C. Table 4.12. Radio Current Consumption at 1.5 V Using Boost-Mode DCDC Parameter Symbol Test Condition Min Typ Max Unit Current consumption in re- ceive mode, active packet reception IRX_ACTIVE 125 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1P (Radio clocks only) — 7 — mA 125 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1 — 7.5 — mA 125 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE2, EM1 — 7.8 — mA 500 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1P (Radio clocks only) — 7.1 — mA 500 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1 — 7.6 — mA 500 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE2, EM1 — 7.9 — mA 1 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1P (Radio clocks only) — 6.8 — mA 1 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1 — 7.2 — mA 1 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE2, EM1 — 7.5 — mA 2 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1P (Radio clocks only) — 7.4 — mA 2 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1 — 7.9 — mA 2 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE2, EM1 — 8.2 — mA 802.15.4 receiving frame, f = 2.4 GHz, VSCALE1, EM1P (Radio clocks only) — 7.6 — mA 802.15.4 receiving frame, f = 2.4 GHz, VSCALE1, EM1 — 8 — mA 802.15.4 receiving frame, f = 2.4 GHz, VSCALE2, EM1 — 8.4 — mA EFR32MG29 Wireless SoC Family Data Sheet Electrical Specifications silabs.com | Building a more connected world. Rev. 1.1 | 41 Parameter Symbol Test Condition Min Typ Max Unit Current consumption in re- ceive mode, listening for packet IRX_LISTEN 125 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1P (Radio clocks only) — 7.1 — mA 125 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1 — 7.6 — mA 125 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE2, EM1 — 7.9 — mA 500 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1P (Radio clocks only) — 7.1 — mA 500 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1 — 7.6 — mA 500 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE2, EM1 — 7.9 — mA 1 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1P (Radio clocks only) — 6.8 — mA 1 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1 — 7.3 — mA 1 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE2, EM1 — 7.5 — mA 2 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1P (Radio clocks only) — 7.5 — mA 2 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1 — 7.9 — mA 2 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE2, EM1 — 8.3 — mA 802.15.4 receiving frame, f = 2.4 GHz, VSCALE1, EM1P (Radio clocks only) — 8 — mA 802.15.4 receiving frame, f = 2.4 GHz, VSCALE1, EM1 — 8.4 — mA 802.15.4 receiving frame, f = 2.4 GHz, VSCALE2, EM1 — 8.8 — mA EFR32MG29 Wireless SoC Family Data Sheet Electrical Specifications silabs.com | Building a more connected world. Rev. 1.1 | 42 Parameter Symbol Test Condition Min Typ Max Unit Current consumption in transmit mode ITX f = 2.4 GHz, CW, 0 dBm PA, 0 dBm output power, VSCALE1, EM1P (Radio clocks only) — 7.9 — mA f = 2.4 GHz, CW, High-power PA, 0 dBm output power, VSCALE1, EM1P (Radio clocks only) — 11.1 — mA f = 2.4 GHz, CW, High-power PA, 4 dBm output power, VSCALE1, EM1P (Radio clocks only) — 14.8 — mA f = 2.4 GHz, CW, High-power PA, 6 dBm output power, VSCALE1, EM1P (Radio clocks only) — 17.3 — mA f = 2.4 GHz, CW, High-power PA, 8 dBm output power, VSCALE1, EM1P (Radio clocks only) — 22.2 — mA f = 2.4 GHz, CW, 0 dBm PA, 0 dBm output power, VSCALE1, EM1 — 8.4 — mA f = 2.4 GHz, CW, High-power PA, 0 dBm output power, VSCALE1, EM1 — 11.5 — mA f = 2.4 GHz, CW, High-power PA, 4 dBm output power, VSCALE1, EM1 — 15.2 — mA f = 2.4 GHz, CW, High-power PA, 6 dBm output power, VSCALE1, EM1 — 17.8 — mA f = 2.4 GHz, CW, High-power PA, 8 dBm output power, VSCALE1, EM1 — 22.7 — mA f = 2.4 GHz, CW, 0 dBm PA, 0 dBm output power, VSCALE2, EM1 — 8.6 — mA f = 2.4 GHz, CW, High-power PA, 0 dBm output power, VSCALE2, EM1 — 11.7 — mA f = 2.4 GHz, CW, High-power PA, 4 dBm output power, VSCALE2, EM1 — 15.4 — mA f = 2.4 GHz, CW, High-power PA, 6 dBm output power, VSCALE2, EM1 — 18 — mA f = 2.4 GHz, CW, High-power PA, 8 dBm output power, VSCALE2, EM1 — 22.9 — mA EFR32MG29 Wireless SoC Family Data Sheet Electrical Specifications silabs.com | Building a more connected world. Rev. 1.1 | 43 4.8.7 Radio Current Consumption at 3.0 V RF current consumption measured with RHCLK = 38.4 MHz, and all MCU peripherals disabled. Unless otherwise indicated, typical con- ditions are: AVDD = DVDD = IOVDD = RFVDD = PAVDD = 3.0 V. TA = 25 °C. Minimum and maximum values in this table represent the worst conditions across process variation at TA = 25 °C. Table 4.13. Radio Current Consumption at 3.0 V Parameter Symbol Test Condition Min Typ Max Unit Current consumption in re- ceive mode, active packet reception IRX_ACTIVE 125 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1P (Radio clocks only) — 5.7 — mA 125 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1 — 6.1 — mA 125 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE2, EM1 — 6.5 — mA 500 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1P (Radio clocks only) — 5.8 — mA 500 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1 — 6.2 — mA 500 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE2, EM1 — 6.6 — mA 1 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1P (Radio clocks only) — 5.4 — mA 1 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1 — 5.9 — mA 1 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE2, EM1 — 6.1 — mA 2 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1P (Radio clocks only) — 6.1 — mA 2 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1 — 6.5 — mA 2 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE2, EM1 — 6.8 — mA 802.15.4 receiving frame, f = 2.4 GHz, VSCALE1, EM1P (Radio clocks only) — 6.2 — mA 802.15.4 receiving frame, f = 2.4 GHz, VSCALE1, EM1 — 6.7 — mA 802.15.4 receiving frame, f = 2.4 GHz, VSCALE2, EM1 — 7 — mA EFR32MG29 Wireless SoC Family Data Sheet Electrical Specifications silabs.com | Building a more connected world. Rev. 1.1 | 44 Parameter Symbol Test Condition Min Typ Max Unit Current consumption in re- ceive mode, listening for packet IRX_LISTEN 125 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1P (Radio clocks only) — 5.7 — mA 125 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1 — 6.1 — mA 125 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE2, EM1 — 6.4 — mA 500 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1P (Radio clocks only) — 5.7 — mA 500 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1 — 6.1 — mA 500 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE2, EM1 — 6.4 — mA 1 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1P (Radio clocks only) — 5.5 — mA 1 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1 — 5.9 — mA 1 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE2, EM1 — 6.2 — mA 2 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1P (Radio clocks only) — 6.2 — mA 2 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1 — 6.6 — mA 2 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE2, EM1 — 6.9 — mA 802.15.4 receiving frame, f = 2.4 GHz, VSCALE1, EM1P (Radio clocks only) — 6.6 — mA 802.15.4 receiving frame, f = 2.4 GHz, VSCALE1, EM1 — 7.1 — mA 802.15.4 receiving frame, f = 2.4 GHz, VSCALE2, EM1 — 7.4 — mA EFR32MG29 Wireless SoC Family Data Sheet Electrical Specifications silabs.com | Building a more connected world. Rev. 1.1 | 45 Parameter Symbol Test Condition Min Typ Max Unit Current consumption in transmit mode ITX f = 2.4 GHz, CW, 0 dBm PA, 0 dBm output power, VSCALE1, EM1P (Radio clocks only) — 6.1 — mA f = 2.4 GHz, CW, High-power PA, 0 dBm output power, VSCALE1, EM1P (Radio clocks only) — 8.6 — mA f = 2.4 GHz, CW, High-power PA, 4 dBm output power, VSCALE1, EM1P (Radio clocks only) — 11.1 — mA f = 2.4 GHz, CW, High-power PA, 6 dBm output power, VSCALE1, EM1P (Radio clocks only) — 13.7 — mA f = 2.4 GHz, CW, High-power PA, 8 dBm output power, VSCALE1, EM1P (Radio clocks only) — 16.9 — mA f = 2.4 GHz, CW, 0 dBm PA, 0 dBm output power, VSCALE1, EM1 — 6.5 — mA f = 2.4 GHz, CW, High-power PA, 0 dBm output power, VSCALE1, EM1 — 9 — mA f = 2.4 GHz, CW, High-power PA, 4 dBm output power, VSCALE1, EM1 — 11.5 — mA f = 2.4 GHz, CW, High-power PA, 6 dBm output power, VSCALE1, EM1 — 14.1 — mA f = 2.4 GHz, CW, High-power PA, 8 dBm output power, VSCALE1, EM1 — 17.3 — mA f = 2.4 GHz, CW, 0 dBm PA, 0 dBm output power, VSCALE2, EM1 — 6.8 — mA f = 2.4 GHz, CW, High-power PA, 0 dBm output power, VSCALE2, EM1 — 9.2 — mA f = 2.4 GHz, CW, High-power PA, 4 dBm output power, VSCALE2, EM1 — 11.8 — mA f = 2.4 GHz, CW, High-power PA, 6 dBm output power, VSCALE2, EM1 — 14.3 — mA f = 2.4 GHz, CW, High-power PA, 8 dBm output power, VSCALE2, EM1 — 17.6 — mA EFR32MG29 Wireless SoC Family Data Sheet Electrical Specifications silabs.com | Building a more connected world. Rev. 1.1 | 46 4.8.8 Radio Current Consumption at 1.8 V RF current consumption measured with RHCLK = 38.4 MHz, and all MCU peripherals disabled. Unless otherwise indicated, typical con- ditions are: AVDD = DVDD = IOVDD = RFVDD = PAVDD = 1.8 V. TA = 25 °C. Minimum and maximum values in this table represent the worst conditions across process variation at TA = 25 °C. Table 4.14. Radio Current Consumption at 1.8 V Parameter Symbol Test Condition Min Typ Max Unit Current consumption in re- ceive mode, active packet reception IRX_ACTIVE 125 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1P (Radio clocks only) — 5.7 — mA 125 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1 — 6.1 — mA 125 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE2, EM1 — 6.5 — mA 500 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1P (Radio clocks only) — 5.8 — mA 500 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1 — 6.2 — mA 500 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE2, EM1 — 6.5 — mA 1 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1P (Radio clocks only) — 5.4 — mA 1 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1 — 5.8 — mA 1 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE2, EM1 — 6.1 — mA 2 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1P (Radio clocks only) — 6 — mA 2 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1 — 6.5 — mA 2 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE2, EM1 — 6.8 — mA 802.15.4 receiving frame, f = 2.4 GHz, VSCALE1, EM1P (Radio clocks only) — 6.2 — mA 802.15.4 receiving frame, f = 2.4 GHz, VSCALE1, EM1 — 6.6 — mA 802.15.4 receiving frame, f = 2.4 GHz, VSCALE2, EM1 — 7 — mA EFR32MG29 Wireless SoC Family Data Sheet Electrical Specifications silabs.com | Building a more connected world. Rev. 1.1 | 47 Parameter Symbol Test Condition Min Typ Max Unit Current consumption in re- ceive mode, listening for packet IRX_LISTEN 125 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1P (Radio clocks only) — 5.7 — mA 125 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1 — 6.1 — mA 125 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE2, EM1 — 6.4 — mA 500 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1P (Radio clocks only) — 5.7 — mA 500 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1 — 6.1 — mA 500 kbit/s, 2GFSK, f = 2.4 GHz, VSCALE2, EM1 — 6.4 — mA 1 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1P (Radio clocks only) — 5.4 — mA 1 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1 — 5.9 — mA 1 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE2, EM1 — 6.1 — mA 2 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1P (Radio clocks only) — 6.1 — mA 2 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE1, EM1 — 6.5 — mA 2 Mbit/s, 2GFSK, f = 2.4 GHz, VSCALE2, EM1 — 6.9 — mA 802.15.4 receiving frame, f = 2.4 GHz, VSCALE1, EM1P (Radio clocks only) — 6.6 — mA 802.15.4 receiving frame, f = 2.4 GHz, VSCALE1, EM1 — 7 — mA 802.15.4 receiving frame, f = 2.4 GHz, VSCALE2, EM1 — 7.4 — mA EFR32MG29 Wireless SoC Family Data Sheet Electrical Specifications silabs.com | Building a more connected world. Rev. 1.1 | 48 Parameter Symbol Test Condition Min Typ Max Unit Current consumption in transmit mode ITX f = 2.4 GHz, CW, 0 dBm PA, 0 dBm output power, VSCALE1, EM1P (Radio clocks only) — 6.1 — mA f = 2.4 GHz, CW, High-power PA, 0 dBm output power, VSCALE1, EM1P (Radio clocks only) — 8.5 — mA f = 2.4 GHz, CW, High-power PA, 4 dBm output power, VSCALE1, EM1P (Radio clocks only) — 11.1 — mA f = 2.4 GHz, CW, High-power PA, 6 dBm output power, VSCALE1, EM1P (Radio clocks only) — 13.1 — mA f = 2.4 GHz, CW, High-power PA, 8 dBm output power, VSCALE1, EM1P (Radio clocks only) — 16.8 — mA f = 2.4 GHz, CW, 0 dBm PA, 0