S32K3xx Data Sheet

2x24ch 16bit eMIOS Timer BCTU (Body Control Trigger Unit) LCU (Logic Control Unit) MPU CRC FCCU EIM/ERM SWT Functional Safety CMU STCU Communication 4 x LPSPI 2 x LPI2C Network 3 x FlexCAN, all ch support CAN FD CPU Platform Xbar (64bit) Cortex-M0+ RAM Single Core Cortex-M7 FPU, DSP 120Mhz I-Cache D-cache 16ch FlexIO Emulating UART, I2C, SPI, I2S, SENT, PWM 4 x LPUART (LIN) Asymmetric Hardware Accelerators 32bit RTC TRNG/PRNG Memory • OTA ready - RWW, A/B swap CPU Platform • Scalable Arm M7 core in lockstep • Optimized for Real- time with zero wait I/D-TCM Network/ Communication • CAN/ CAN FD, LIN • Flexible IO emulation Motor Control • On-chip motor control sub- system • Offloading CPU Security • HW accl for AES 256, RSA 4096, ECC 521 • Firmware included, upgradable • Side-channel physical protection • Meet Evita Full function goal • • • • • Safety HW redundancy MBIST/LBIST/Self Test Clock/Voltage monitor Centralized error detection ASIL B compliant ` Future Proof Security/OTA ISO26262 Compliant Safety System Scalable Arm platform Optimized for LOW power Rich Network/Communication Interface • • • • • Figure 1. S32K310: ASIL B Single Core 512 KB General Purpose MCU NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 3 / 170 Xbar (64 bit) Fabric 1 MB Pflash with ECC Memory 3 x FlexCAN all ch support CAN FD 4 x LPUART (LIN) Network 16 ch FlexIO Emulating UART, I2C, SPI I2S, SENT, PWM Communication 64 kB Dflash with ECC 128 kB RAM with ECC Include 96 kB TCM FXOSC (8-40 MHz) Memory OTA ready - RWW, A/B swap • CPU Platform Single Arm M7 core Optimized for Real- time with zero wait I/D-TCM • • Motor Control On-chip motor control subsystem Offloading CPU • • Future Proof Security/OTA ISO26262 Compliant Safety System Scalable Arm platform Optimized for LOW power Rich Network/Communication Interface • • • • • Safety HW redundancy MBIST/LBIST/Self Test Clock/Voltage monitor Centralized error detection ASIL B compliant • • • • • Security HW accl for AES 256, RSA 4096, ECC 521 Firmware included, upgradable Side-channel physical protection Meet Evita Full function goal • • • • Network/ Communication CAN/CAN FD, LIN Flexible IO emulation • • System FIRC (48 MHz) CPU Platform Cortex-M7 120 MHz FPU, DSP I-cache D-cache Single Core SIRC (32 KHz) PLL 12ch DMA 32ch ext. INT/WKUP 4 x LPSPI 2 x LPI2C Analog/Timers BCTU (Body Control Trigger Unit) 2 x 24 ch 12 bit ADC LCU (Logic Control Unit) 2 x 24 ch 16 bit eMIOS Timer 1 x LPCMP 32 bit RTC Functional Safety CMU FCCU MPU SWT EIM/ERM STCU2 CRC Security: HSE-B Cortex-M0+ RAM XRDC Access control Lifecycle Management Asymmetric Hardware Accelerators Symmetric Hardware Accelerators TRNG/PRNG Debug/Trace (SWD/JTAG/ETB) Figure 2. S32K311: ASIL B Single Core 1MB General Purpose MCU Xbar (64 bit) Fabric 2 MB Pflash with ECC Memory 6 x FlexCAN all ch support CAN FD 8 x LPUART (LIN) Network 32 ch FlexIO Emulating UART, I2C, SPI I2S, SENT, PWM Communication 128 kB Dflash with ECC 192 kB RAM with ECC Include 96 kB TCM FXOSC (8-40 MHz) Memory OTA ready - RWW, A/B swap • CPU Platform Single Arm M7 core Optimized for Real- time with zero wait I/D-TCM • • Motor Control On-chip motor control subsystem Offloading CPU • • Future Proof Security/OTA ISO26262 Compliant Safety System Scalable Arm platform Optimized for LOW power Rich Network/Communication Interface • • • • • Safety HW redundancy MBIST/LBIST/Self Test Clock/Voltage monitor Centralized error detection ASIL B compliant • • • • • Security HW accl for AES 256, RSA 4096, ECC 521 Firmware included, upgradable Side-channel physical protection Meet Evita Full function goal • • • • Network/ Communication CAN/CAN FD, LIN Flexible IO emulation • • System FIRC (48 MHz) CPU Platform Cortex-M7 120 MHz FPU, DSP I-cache D-cache Single Core SIRC (32 kHz) SXOSC (32 kHz) PLL 12ch DMA 32ch ext. INT/WKUP 4 x LPSPI 2 x LPI2C Analog/Timers BCTU (Body Control Trigger Unit) 2 x 24 ch 12 bit ADC LCU (Logic Control Unit) 2 x 24 ch 16 bit eMIOS Timer 2 x LPCMP Functional Safety CMU FCCU MPU SWT EIM/ERM STCU2 CRC Security: HSE-B Cortex-M0+ RAM XRDC Access control Lifecycle Management Asymmetric Hardware Accelerators Symmetric Hardware Accelerators TRNG/PRNG Debug/Trace (SWD/JTAG/ETB) 32-bit RTC Figure 3. S32K312: ASIL B Single Core 2MB General Purpose MCU NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 4 / 170 Xbar (64 bit) Fabric 2 MB Pflash with ECC Memory 1 x QuadSPI Up to 480 Mbps 4 bit data width External Memory IF 1 x Ethernet, 100 Mbps AVB/TSN 4 x FlexCAN all ch support CAN FD 4 x LPUART (LIN) Network Communication 128 kB Dflash with ECC 256 kB RAM with ECC Include 192 kB TCM FXOSC (8-40 MHz) Memory OTA ready - RWW, A/B swap External Flash/Ram expansion by QuadSPI • • CPU Platform Two independent Arm M7 cores Optimized for Real- time with zero wait I/D-TCM • • Motor Control On-chip motor control subsystem Offloading CPU • • Future Proof Security/OTA ISO26262 Compliant Safety System Scalable Arm platform Optimized for LOW power Rich Network/Communication Interface • • • • • Safety HW redundancy MBIST/LBIST/Self Test Clock/Voltage monitor Centralized error detection ASIL B compliant • • • • • Security HW accl for AES 256, RSA 4096, ECC 521 Firmware included, upgradable Side-channel physical protection Meet Evita Full function goal • • • • Network/ Communication Ethernet (TSN), CAN/ CAN FD, LIN SAI for Audio Flexible IO emulation • • • System FIRC (48 MHz) CPU Platform Cortex-M7 160 MHz FPU, DSP I-cache D-cache Cortex-M7 160 MHz FPU, DSP I-cache D-cache Dual Core SIRC (32 kHz) SXOSC (32 kHz) PLL 32ch DMA 32ch ext. INT/WKUP Analog/Timers BCTU (Body Control Trigger Unit) 2 x 24 ch 12 bit ADC LCU (Logic Control Unit) 2 x 24 ch 16 bit eMIOS Timer 2 x LPCMP Functional Safety CMU FCCU MPU SWT EIM/ERM STCU2 CRC Security: HSE-B Cortex-M0+ RAM XRDC Access control Lifecycle Management Asymmetric Hardware Accelerators Symmetric Hardware Accelerators TRNG/PRNG Debug/Trace (SWD/JTAG/ETB) 32 ch FlexIO Emulating UART, I2C, SPI I2S, SENT, PWM 4 x LPSPI 2 x LPI2C 2 x SAI (TDM, I2S) 32 bit RTC Figure 4. S32K322: ASIL B Dual Core 2MB General Purpose MCU Xbar (64 bit) Fabric 1 MB Pflash with ECC Memory 1 x QuadSPI Up to 480 Mbps 4 bit data width External Memory IF 1 x Ethernet, 100 Mbps AVB/TSN 4 x FlexCAN all ch support CAN FD 4 x LPUART (LIN) Network Communication 128 kB Dflash with ECC 256 kB RAM with ECC Include 192 kB TCM FXOSC (8-40 MHz) Memory OTA ready - RWW, A/B swap External Flash/Ram expansion by QuadSPI • • CPU Platform Scalable Arm M7 core in Lockstep Optimized for Real- time with zero wait I/D-TCM • • Motor Control On-chip motor control subsystem Offloading CPU • • Future Proof Security/OTA ISO26262 Compliant Safety System Scalable Arm platform Optimized for LOW power Rich Network/Communication Interface • • • • • Safety HW redundancy MBIST/LBIST/Self Test Clock/Voltage monitor Centralized error detection ASIL D compliant • • • • • Security HW accl for AES 256, RSA 4096, ECC 521 Firmware included, upgradable Side-channel physical protection Meet Evita Full function goal • • • • Network/ Communication Ethernet (TSN), CAN/ CAN FD, LIN SAI for Audio Flexible IO emulation • • • System FIRC (48 MHz) CPU Platform Cortex-M7 160 MHz FPU, DSP I-cache D-cache Lockstep Core SIRC (32 kHz) SXOSC (32 kHz) PLL 32ch DMA 32ch ext. INT/WKUP Analog/Timers BCTU (Body Control Trigger Unit) 2 x 24 ch 12 bit ADC LCU (Logic Control Unit) 2 x 24 ch 16 bit eMIOS Timer 2 x LPCMP Functional Safety CMU FCCU MPU SWT EIM/ERM STCU2 CRC Security: HSE-B Cortex-M0+ RAM XRDC Access control Lifecycle Management Asymmetric Hardware Accelerators Symmetric Hardware Accelerators TRNG/PRNG Debug/Trace (SWD/JTAG/ETB) 32 ch FlexIO Emulating UART, I2C, SPI I2S, SENT, PWM 4 x LPSPI 2 x LPI2C 2 x SAI (TDM, I2S) Cortex-M7 160 MHz FPU, DSP I-cache D-cache 32 bit RTC Figure 5. S32K341: ASIL D Lockstep Core 1MB General Purpose MCU NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 5 / 170 Xbar (64 bit) Fabric 2 MB Pflash with ECC Memory 1 x QuadSPI Up to 480 Mbps 4 bit data width External Memory IF 1 x Ethernet, 100 Mbps AVB/TSN 4 x FlexCAN all ch support CAN FD 4 x LPUART (LIN) Network Communication 128 kB Dflash with ECC 256 kB RAM with ECC Include 192 kB TCM FXOSC (8-40 MHz) Memory OTA ready - RWW, A/B swap External Flash/Ram expansion by QuadSPI • • CPU Platform Scalable Arm M7 core in Lockstep Optimized for Real- time with zero wait I/D-TCM • • Motor Control On-chip motor control subsystem Offloading CPU • • Future Proof Security/OTA ISO26262 Compliant Safety System Scalable Arm platform Optimized for LOW power Rich Network/Communication Interface • • • • • Safety HW redundancy MBIST/LBIST/Self Test Clock/Voltage monitor Centralized error detection ASIL D compliant • • • • • Security HW accl for AES 256, RSA 4096, ECC 521 Firmware included, upgradable Side-channel physical protection Meet Evita Full function goal • • • • Network/ Communication Ethernet (TSN), CAN/ CAN FD, LIN SAI for Audio Flexible IO emulation • • • System FIRC (48 MHz) CPU Platform Cortex-M7 160 MHz FPU, DSP I-cache D-cache Lockstep Core SIRC (32 kHz) SXOSC (32 kHz) PLL 32ch DMA 32ch ext. INT/WUP Analog/Timers BCTU (Body Control Trigger Unit) 2 x 24 ch 12 bit ADC LCU (Logic Control Unit) 2 x 24 ch 16 bit eMIOS Timer 2 x LPCMP Functional Safety CMU FCCU MPU SWT EIM/ERM STCU2 CRC Security: HSE-B Cortex-M0+ RAM XRDC Access control Lifecycle Management Asymmetric Hardware Accelerators Symmetric Hardware Accelerators TRNG/PRNG Debug/Trace (SWD/JTAG/ETB) 32 ch FlexIO Emulating UART, I2C, SPI I2S, SENT, PWM 4 x LPSPI 2 x LPI2C 2 x SAI (TDM, I2S) Cortex-M7 160 MHz FPU, DSP I-cache D-cache 32 bit RTC Figure 6. S32K342: ASIL D Lockstep Core 2MB General Purpose MCU Xbar (64 bit) Fabric 4 MB Pflash with ECC Memory 1 x QuadSPI Up to 480 Mbps 4 bit data width External Memory IF 1 x Ethernet, 100 Mbps AVB/TSN 6 x FlexCAN all ch support CAN FD 16 x LPUART (LIN) Network 32 ch FlexIO Emulating UART, I2C, SPI I2S, SENT, PWM Communication 128 kB Dflash with ECC 512 kB RAM with ECC Include 96 kB TCM FXOSC (8-40 MHz) Memory OTA ready - RWW, A/B swap External Flash/Ram expansion by QuadSPI • • CPU Platform Single Arm M7 core Optimized for Real- time with zero wait I/D-TCM • • Motor Control On-chip motor control subsystem Offloading CPU • • Future Proof Security/OTA ISO26262 Compliant Safety System Scalable Arm platform Optimized for LOW power Rich Network/Communication Interface • • • • • Safety HW redundancy MBIST/LBIST/Self Test Clock/Voltage monitor Centralized error detection ASIL B compliant • • • • • Security HW accl for AES 256, RSA 4096, ECC 521 Firmware included, upgradable Side-channel physical protection Meet Evita Full function goal • • • • Network/ Communication Ethernet (TSN), CAN/ CAN FD, LIN SAI for Audio Flexible IO emulation • • • System FIRC (48 MHz) CPU Platform Cortex-M7 160 MHz FPU, DSP I-cache D-cache Single Core SIRC (32 kHz) SXOSC (32 kHz) PLL 32ch DMA 32ch ext. INT/WKUP 6 x LPSPI 2 x LPI2C 2 x SAI (TDM, I2S) Analog/Timers BCTU (Body Control Trigger Unit) 3 x 24 ch 12 bit ADC LCU (Logic Control Unit) 3 x 24 ch 16 bit eMIOS Timer 3 x LPCMP Functional Safety CMU FCCU MPU SWT EIM/ERM STCU2 CRC Security: HSE-B Cortex-M0+ RAM XRDC Access control Lifecycle Management Asymmetric Hardware Accelerators Symmetric Hardware Accelerators TRNG/PRNG Debug/Trace (SWD/JTAG/ETB) 32 bit RTC Figure 7. S32K314: ASIL B Single Core 4MB General Purpose MCU NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 6 / 170 Xbar (64 bit) Fabric 4 MB Pflash with ECC Memory 1 x QuadSPI Up to 480 Mbps 4 bit data width External Memory IF 1 x Ethernet, 100 Mbps AVB/TSN 6 x FlexCAN all ch support CAN FD 16 x LPUART (LIN) Network 32 ch FlexIO Emulating UART, I2C, SPI I2S, SENT, PWM Communication 128 kB Dflash with ECC 512 kB RAM with ECC Include 192 kB TCM FXOSC (8-40 MHz) Memory OTA ready - RWW, A/B swap External Flash/Ram expansion by QuadSPI • • CPU Platform Two independent Arm M7 cores Optimized for Real- time with zero wait I/D-TCM • • Motor Control On-chip motor control subsystem Offloading CPU • • Future Proof Security/OTA ISO26262 Compliant Safety System Scalable Arm platform Optimized for LOW power Rich Network/Communication Interface • • • • • Safety HW redundancy MBIST/LBIST/Self Test Clock/Voltage monitor Centralized error detection ASIL B compliant • • • • • Security HW accl for AES 256, RSA 4096, ECC 521 Firmware included, upgradable Side-channel physical protection Meet Evita Full function goal • • • • Network/ Communication Ethernet (TSN), CAN/ CAN FD, LIN SAI for Audio Flexible IO emulation • • • System FIRC (48 MHz) CPU Platform Cortex-M7 160 MHz FPU, DSP I-cache D-cache Dual Core SIRC (32 kHz) SXOSC (32 kHz) PLL 32ch DMAMUX 32ch ext. INT/WKUP 6 x LPSPI 2 x LPI2C 2 x SAI (TDM, I2S) Analog/Timers BCTU (Body Control Trigger Unit) 3 x 24 ch 12 bit ADC LCU (Logic Control Unit) 3 x 24 ch 16 bit eMIOS Timer 3 x LPCMP Functional Safety CMU FCCU MPU SWT EIM/ERM STCU2 CRC Security: HSE-B Cortex-M0+ RAM XRDC Access control Lifecycle Management Asymmetric Hardware Accelerators Symmetric Hardware Accelerators TRNG/PRNG Debug/Trace (SWD/JTAG/ETB) Cortex-M7 160 MHz FPU, DSP I-cache D-cache 32 bit RTC Figure 8. S32K324: ASIL B Dual Core 4MB General Purpose MCU Xbar (64 bit) Fabric 4 MB Pflash with ECC Memory 1 x QuadSPI Up to 480 Mbps 4 bit data width External Memory IF 1 x Ethernet, 100 Mbps AVB/TSN 6 x FlexCAN all ch support CAN FD 16 x LPUART (LIN) Network 32 ch FlexIO Emulating UART, I2C, SPI I2S, SENT, PWM Communication 128 kB Dflash with ECC 512 kB RAM with ECC Include 192 kB TCM FXOSC (8-40 MHz) Memory OTA ready - RWW, A/B swap External Flash/Ram expansion by QuadSPI • • CPU Platform Scalable Arm M7 core in Lockstep Optimized for Real- time with zero wait I/D-TCM • • Motor Control On-chip motor control subsystem Offloading CPU Future Proof Security/OTA ISO26262 Compliant Safety System Scalable Arm platform Optimized for LOW power Rich Network/Communication Interface • • • • • Safety HW redundancy MBIST/LBIST/Self Test Clock/Voltage monitor Centralized error detection ASIL D compliant • • • • • Security HW accl for AES 256, RSA 4096, ECC 521 Firmware included, upgradable Side-channel physical protection Meet Evita Full function goal • • • • Network/ Communication Ethernet (TSN), CAN/ CAN FD, LIN SAI for Audio Flexible IO emulation • • • System FIRC (48 MHz) CPU Platform Cortex-M7 160 MHz FPU, DSP I-cache D-cache Cortex-M7 160 MHz FPU, DSP I-cache D-cache Lockstep Core SIRC (32 kHz) SXOSC (32 kHz) PLL 32ch DMA and DMAMUX 32ch ext. INT/WUP 6 x LPSPI 2 x LPI2C 2 x SAI (TDM, I2S) Analog/Timers BCTU (Body Control Trigger Unit) 3 x 24 ch 12 bit ADC LCU(Logic Control Unit) 3 x 24 ch 16 bit eMIOS Timer 3 x LPCMP Functional Safety CMU FCCU MPU SWT EIM/ERM STCU2 CRC Security: HSE-B Cortex-M0+ RAM XRDC Access control Lifecycle Management Asymmetric Hardware Accelerators Symmetric Hardware Accelerators TRNG/PRNG Debug/Trace (SWD/JTAG/ETB) 32 bit RTC Figure 9. S32K344: ASIL D Lockstep Core 4MB General Purpose MCU NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 7 / 170 Xbar (64 bit) Fabric 8 MB Pflash with ECC Memory External Memory IF 1 x Ethernet, 1 Gbps AVB/TSN 8 x FlexCAN all ch support CAN FD 16 x LPUART (LIN) Network 32 ch FlexIO Emulating UART, I2C, SPI I2S, SENT, PWM Communication 128 kB Dflash with ECC 1152 kB RAM with ECC Include 192 kB TCM FXOSC (8-40 MHz) Memory OTA ready - RWW, A/B swap External Flash/Ram expansion by QuadSPI • • CPU Platform Two independent Arm M7 cores Optimized for Real- time with zero wait I/D-TCM • • Motor Control On-chip motor control subsystem Offloading CPU • • Future Proof Security/OTA ISO26262 Compliant Safety System Scalable Arm platform Optimized for LOW power Rich Network/Communication Interface • • • • • Safety HW redundancy MBIST/LBIST/Self Test Clock/Voltage monitor Centralized error detection ASIL B compliant • • • • • Security HW accl for AES 256, RSA 4096, ECC 521 Firmware included, upgradable Side-channel physical protection Meet Evita Full function goal • • • • Network/ Communication Ethernet (TSN), CAN/ CAN FD, LIN SAI for Audio Flexible IO emulation • • • System FIRC (48 MHz) CPU Platform Cortex-M7 240 MHz FPU, DSP I-cache D-cache SIRC (32 kHz) SXOSC (32 kHz) 2 x PLL 32ch DMAMUX 32ch ext. INT/WKUP 6 x LPSPI 2 x LPI2C 2 x SAI (TDM, I2S) Analog/Timers BCTU (Body Control Trigger Unit) 3 x 24 ch 12 bit ADC LCU (Logic Control Unit) 3 x 24 ch 16 bit eMIOS Timer 3 x LPCMP Functional Safety CMU FCCU MPU SWT EIM/ERM STCU2 CRC Security: HSE-B Cortex-M0+ RAM XRDC Access control Lifecycle Management Asymmetric Hardware Accelerators Symmetric Hardware Accelerators TRNG/PRNG Debug/Trace (SWD/JTAG/ETB) Cortex-M7 240 MHz FPU, DSP I-cache D-cache 1 x QuadSPI Up to 2 Gbps 8 bit data width 1 x uSDHC 32 bit RTC Figure 10. S32K328: ASIL B Dual Core 8MB General Purpose MCU Xbar (64 bit) Fabric 8 MB Pflash with ECC Memory External Memory IF 1 x Ethernet, 1 Gbps AVB/TSN 8 x FlexCAN all ch support CAN FD 16 x LPUART (LIN) Network 32 ch FlexIO Emulating UART, I2C, SPI I2S, SENT, PWM Communication 128 kB Dflash with ECC 1152 kB RAM with ECC Include 384 kB TCM FXOSC (8-40 MHz) Memory OTA ready - RWW, A/B swap External Flash/Ram expansion by QuadSPI • • CPU Platform Three independent Arm M7 cores Optimized for Real- time with zero wait I/D-TCM • • Motor Control On-chip motor control subsystem Offloading CPU • • Future Proof Security/OTA ISO26262 Compliant Safety System Scalable Arm platform Optimized for LOW power Rich Network/Communication Interface • • • • • Safety HW redundancy MBIST/LBIST/Self Test Clock/Voltage monitor Centralized error detection ASIL D compliant • • • • • Security HW accl for AES 256, RSA 4096, ECC 521 Firmware included, upgradable Side-channel physical protection Meet Evita Full function goal • • • • Network/ Communication Ethernet (TSN), CAN/ CAN FD, LIN SAI for Audio Flexible IO emulation • • • System FIRC (48 MHz) CPU Platform SIRC (32 kHz) SXOSC (32 kHz) 2 x PLL 32ch DMA and DMAMUX 32ch ext. INT/WKUP 6 x LPSPI 2 x LPI2C 2 x SAI (TDM, I2S) Analog/Timers BCTU (Body Control Trigger Unit) 3 x 24 ch 12 bit ADC LCU (Logic Control Unitl 3 x 24 ch 16 bit eMIOS Timer 3 x LPCMP Functional Safety CMU FCCU MPU SWT EIM/ERM STCU2 CRC Security: HSE-B Cortex-M0+ RAM XRDC Access control Lifecycle Management Asymmetric Hardware Accelerators Symmetric Hardware Accelerators TRNG/PRNG Debug/Trace (SWD/JTAG/ETB) Cortex-M7 240 MHz FPU, DSP I-cache D-cache Cortex-M7 240 MHz FPU, DSP I-cache D-cache Cortex-M7 240 MHz FPU, DSP I-cache D-cache 1 x QuadSPI Up to 2 Gbps 8 bit data width 1 x uSDHC 32 bit RTC Figure 11. S32K338: ASIL B Three Core 8MB General Purpose MCU NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 8 / 170 Xbar (64 bit) Fabric 8 MB Pflash with ECC Memory External Memory IF 1 x Ethernet, 1 Gbps AVB/TSN 8 x FlexCAN all ch support CAN FD 16 x LPUART (LIN) Network 32 ch FlexIO Emulating UART, I2C, SPI I2S, SENT, PWM Communication 128 kB Dflash with ECC 1152 kB RAM with ECC Include 192 kB TCM FXOSC (8-40 MHz) Memory OTA ready - RWW, A/B swap External Flash/Ram expansion by QuadSPI • • CPU Platform Arm M7 cores in lockstep Optimized for Real- time with zero wait I/D-TCM • • Motor Control On-chip motor control subsystem Offloading CPU • • Future Proof Security/OTA ISO26262 Compliant Safety System Scalable Arm platform Optimized for LOW power Rich Network/Communication Interface • • • • • Safety HW redundancy MBIST/LBIST/Self Test Clock/Voltage monitor Centralized error detection ASIL D compliant • • • • • Security HW accl for AES 256, RSA 4096, ECC 521 Firmware included, upgradable Side-channel physical protection Meet Evita Full function goal • • • • Network/ Communication Ethernet (TSN), CAN/ CAN FD, LIN SAI for Audio Flexible IO emulation • • • System FIRC (48 MHz) CPU Platform Cortex-M7 240 MHz FPU, DSP I-cache D-cache Cortex-M7 240 MHz FPU, DSP I-cache D-cache Lockstep Core SIRC (32 kHz) SXOSC (32 kHz) 2 x PLL 32ch DMA and DMAMUX 32ch ext. INT/WKUP 6 x LPSPI 2 x LPI2C 2 x SAI (TDM, I2S) Analog/Timers BCTU (Body Control Trigger Unit) 3 x 24 ch 12 bit ADC LCU (Logic Control Unit) 3 x 24 ch 16 bit eMIOS Timer 3 x LPCMP Functional Safety CMU FCCU MPU SWT EIM/ERM STCU2 CRC Security: HSE-B Cortex-M0+ RAM XRDC Access control Lifecycle Management Asymmetric Hardware Accelerators Symmetric Hardware Accelerators TRNG/PRNG Debug/Trace (SWD/JTAG/ETB) 1 x QuadSPI Up to 2 Gbps 8 bit data width 32 bit RTC 1 x uSDHC Figure 12. S32K348: ASIL D Lockstep Core 8MB General Purpose MCU Xbar (64 bit) Fabric 8 MB Pflash with ECC Memory External Memory IF 1 x Ethernet, 1 Gbps AVB/TSN 8 x FlexCAN all ch support CAN FD 16 x LPUART (LIN) Network 32 ch FlexIO Emulating UART, I2C, SPI I2S, SENT, PWM Communication 128 kB Dflash with ECC 1152 kB RAM with ECC Include 384 kB TCM FXOSC (8-40 MHz) Memory OTA ready - RWW, A/B swap External Flash/Ram expansion by QuadSPI • • CPU Platform Arm M7 cores in lockstep One independent Arm M7 for real time processing Optimized for Real- time with zero wait I/D-TCM • • • Motor Control On-chip motor control subsystem Offloading CPU • • Future Proof Security/OTA ISO26262 Compliant Safety System Scalable Arm platform Optimized for LOW power Rich Network/Communication Interface • • • • • Safety HW redundancy MBIST/LBIST/Self Test Clock/Voltage monitor Centralized error detection ASIL D compliant • • • • • Security HW accl for AES 256, RSA 4096, ECC 521 Firmware included, upgradable Side-channel physical protection Meet Evita Full function goal • • • • Network/ Communication Ethernet (TSN), CAN/ CAN FD, LIN SAI for Audio Flexible IO emulation • • • System FIRC (48 MHz) CPU Platform Cortex-M7 240 MHz FPU, DSP I-cache D-cache Cortex-M7 240 MHz FPU, DSP I-cache D-cache Lockstep Core SIRC (32 kHz) SXOSC (32 kHz) 2 x PLL 32ch DMA 32ch ext. INT/WKUP 6 x LPSPI 2 x LPI2C 2 x SAI (TDM, I2S) Analog/Timers BCTU (Body Control Trigger Unit) 3 x 24 ch 12 bit ADC LCU (Logic Control Unit) 3 x 24 ch 16 bit eMIOS Timer 3 x LPCMP Functional Safety CMU FCCU MPU SWT EIM/ERM STCU2 CRC Security: HSE-B Cortex-M0+ RAM XRDC Access control Lifecycle Management Asymmetric Hardware Accelerators Symmetric Hardware Accelerators TRNG/PRNG Debug/Trace (SWD/JTAG/ETB) Cortex-M7 240 MHz FPU, DSP I-cache D-cache 1 x uSDHC 32 bit RTC 1 x QuadSPI Upto 2 Gbps 8 bit data width Figure 13. S32K358: ASIL D Lockstep Core + One, 8MB General Purpose MCU NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 9 / 170 Xbar (64 bit) Fabric 6 MB Pflash with ECC Memory External Memory IF 1 x Ethernet, 1 Gbps AVB/TSN 8 x FlexCAN all ch support CAN FD 16 x LPUART (LIN) Network 32 ch FlexIO Emulating UART, I2C, SPI I2S, SENT, PWM Communication 128 kB Dflash with ECC 1152 kB RAM with ECC Include 384 kB TCM FXOSC (8-40 MHz) Memory OTA ready - RWW, A/B swap External Flash/Ram expansion by QuadSPI • • CPU Platform Arm M7 cores in lockstep One independent Arm M7 for real time processing Optimized for Real- time with zero wait I/D-TCM • • • Motor Control On-chip motor control subsystem Offloading CPU • • Future Proof Security/OTA ISO26262 Compliant Safety System Scalable Arm platform Optimized for LOW power Rich Network/Communication Interface • • • • • Safety HW redundancy MBIST/LBIST/Self Test Clock/Voltage monitor Centralized error detection ASIL D compliant • • • • • Security HW accl for AES 256, RSA 4096, ECC 521 Firmware included, upgradable Side-channel physical protection Meet Evita Full function goal • • • • Network/ Communication Ethernet (TSN), CAN/ CAN FD, LIN SAI for Audio Flexible IO emulation • • • System FIRC (48 MHz) CPU Platform Cortex-M7 240 MHz FPU, DSP I-cache D-cache Cortex-M7 240 MHz FPU, DSP I-cache D-cache Lockstep Core SIRC (32 kHz) SXOSC (32 kHz) 2 x PLL 32ch DMA 32ch ext. INT/WKUP 6 x LPSPI 2 x LPI2C 2 x SAI (TDM, I2S) Analog/Timers BCTU (Body Control Trigger Unit) 3 x 24 ch 12 bit ADC LCU (Logic Control Unit) 3 x 24 ch 16 bit eMIOS Timer 3 x LPCMP Functional Safety CMU FCCU MPU SWT EIM/ERM STCU2 CRC Security: HSE-B Cortex-M0+ RAM XRDC Access control Lifecycle Management Asymmetric Hardware Accelerators Symmetric Hardware Accelerators TRNG/PRNG Debug/Trace (SWD/JTAG/ETB) Cortex-M7 240 MHz FPU, DSP I-cache D-cache 1 x uSDHC 32 bit RTC 1 x QuadSPI Upto 2 Gbps 8 bit data width Figure 14. S32K356: ASIL D Lockstep Core + One, 6MB General Purpose MCU Fabric Memory 8 MB Pflash with ECC 128 KB Dflash with ECC 1152 KB RAM with ECC Incl 384 KB TCM System Debug/Trace (SWD/JTAG/ETB) FXOSC (8 - 40MHz) 32ch ext. INT/WUP Security: HSE -B Asymmetric Hardware Accelerators Symmetric Hardware Accelerators Lifecycle Management XRDC Access control FIRC (48MHz) SIRC (32KHz) SXOSC (32KHz) 2 x PLL 32ch DMA Analog/Timers 3 x 24ch 12bit ADC 3x24ch 16bit eMIOS Timer BCTU (Body Control Trigger Unit) LCU (Logic Control Unit) MPU CRC FCCU EIM/ERM SWT Functional Safety CMU STCU External Memory IF Communication 6 x LPSPI 2 x LPI2C 2 x SAI (TDM, I2S) Network 8 x FlexCAN, all ch support CAN FD 2 x Ethernet, 1Gbps AVB/TSN Xbar (64bit) Cortex- M0+ RAM 32ch FlexIO Emulating UART, I2C, SPI, I2S, SENT, PWM 16 x LPUART (LIN) TRNG/PRNG 3x LPCMP CPU Platform Lock- Step or Split- Lock Permanent Lock AES Accelerator Dedicated to Communications AES Accelerator optimized for Low Latency Performance Cortex-M7 300 MHz FPU, DSP I-cache D-cache Cortex-M7 320 MHz FPU, DSP I-cache D-cache Cortex-M7 320 MHz FPU, DSP I-cache D-cache Cortex-M7 320 MHz FPU, DSP I-cache D-cache Cortex-M7 320 MHz FPU, DSP I-cache D-cache 32 bit RTC 1 x QuadSPI 4 bit data width Figure 15. S32K388: ASIL D 8MB MCU Fabric Memory 12 MB Pflash with ECC 256 KB Dflash with ECC 2.25MB SRAM with ECC System Debug/Trace (SWD/JTAG/ETB) FXOSC (8-40MHz) 32ch ext. INT/WUP Security: HSE-B Asymmetric Hardware Accelerators Symmetric Hardware Accelerators Lifecycle Management XRDC Access control FIRC (48MHz) SIRC (32KHz) SXOSC (32KHz) PLL 32ch DMA Analog/Timers 3 x 24ch 12bit ADC 3x24ch 24bit eMIOS Timer BCTU (Body Control Trigger Unit) LCU (Logic Control Unit) MPU CRC FCCU EIM/ERM SWT Functional Safety CMU STCU External Memory IF 1 x QuadSPI 4bit data width Communication 6 x LPSPI 2 x LPI2C 2 x SAI (TDM, I2S) Network 12x FlexCAN, all ch support CAN FD 2 x Ethernet, 1Gbps AVB/TSN Xbar (64bit) Cortex-M0+ RAM 32ch FlexIO Emulating UART, I2C, SPI, I2S, SENT, PWM 16 x LPUART (LIN) TRNG/PRNG 3x LPCMP CPU Platform Cortex-M7 32kB I-cache NEON 32kB D- 32kB TCM32kB TCM Cortex-M7 16 KB I-cache 16 KB D-cache TCM: 32K-I, 64K-D Cortex-M7 16 KB I-cache 16 KB D-cache TCM: 32K-I, 64K-D DP-FPU, DSP DP-FPU, DSP Lock-Step or Split-Lock Permanent Lock 16 KB I-cache Cortex-M7 32 KB I- 32 KB D-cache TCM: 32K-I, 64K-D DP-FPU, DSP 16 KB I-cache 16 KB D-cache 16 KB I-cache Cortex-M7 32 KB I-cache 32 KB D-cache TCM: 32K-I, 64K-D DP-FPU, DSP 16 KB I-cache 16 KB D- 16 KB I-cache AES Accelerator Dedicated to Communications +FLEXCANs +FLASH +SRAM 437BGA Package Figure 16. S32K389: ASIL D 12MB MCU NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 10 / 170 3 Feature comparison The following table compares some of the prominent features related to memory and package options of these chips from the S32K3xx family/product series: • S32K310 • S32K311 • S32K312 • S32K322 • S32K341 • S32K342 • S32K314 • S32K324 • S32K344 • S32K328 • S32K338 • S32K348 • S32K356 • S32K358 • S32K388 • S32K389 NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 11 / 170 Table 1. S32K3xx chip's feature comparison Feature Chip S32K310 S32K311 S32K312 S32K322 S32K341 S32K342 S32K314 S32K324 S32K344 S32K328 S32K338 S32K348 S32K356 S32K358 S32K388 S32K389 Safety/ ASIL B D B D B D Program flash memory 512 KB 1 MB 2 MB 1 MB 2 MB 4 MB 8 MB 6 MB 8 MB 12 MB Data flash memory (KB) 64 128 128 256 Total RAM (KB) 112KB (incl. 96KB TCM) 128KB (incl. 96KB TCM) 192KB (incl. 96KB TCM) 256KB (incl. 192KB TCM) 512KB (includi ng 96KB TCM) 512KB (incl. 192KB TCM) 1152KB (incl. 192KB TCM) 1152KB (incl. 384KB TCM) 1152KB (incl. 192KB TCM) 1152KB (incl. 384KB TCM) 2304KB (incl. 384KB TCM) Standby RAM 16 KB 32 KB 64 KB Security HSE_B HSE B + AES_ACCEL Core quantity 1 x M7 2 x M7 1 x M7 LS 1 x M7 2 x M7 1 x M7 LS 2 x M7 3 x M7 1 x M7 LS 1xM7 LS + 1xM7 1xM7 LS+3xM 7 or 2xM7 LS+1xM 7 1xM7 LS + 3xM7 or 2xM7 LS +1xM7 Frequenc y (MHz) 120 160 240 320 Table continues on the next page... NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 12 / 170 Table 1. S32K3xx chip's feature comparison ...continued Feature Chip S32K310 S32K311 S32K312 S32K322 S32K341 S32K342 S32K314 S32K324 S32K344 S32K328 S32K338 S32K348 S32K356 S32K358 S32K388 S32K389 DMA channels 12 32 ASIL-B DMIPS [1] [2] 277-387-813 738-10 32- 2168 — 369-51 6- 1084 738-10 32- 2168 — 1108- 1550- 3254 1662-2 325- 4881 — 554- 775- 1627 739- 1033- 2169 [3] 2217- 3099- 6507 [4] ASIL-D DMIPS [1] [2] — 369-516-1084 — 369- 516- 1084 — 554- 775- 1627 1478- 2066- 4338 [3] 739- 1033- 2169 [4] ASIL-B CoreMark score [1] [5] 634 1692 — 846 1692 — 2538 3807 — 1269 1692 [3] 5078 [4] ASIL-D CoreMark score [1] [5] — 846 — 846 — 1269 3384 [3] 1692 [4] FlexCAN instances 3 6 4 6 8 12 Table continues on the next page... NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 13 / 170 Table 1. S32K3xx chip's feature comparison ...continued Feature Chip S32K310 S32K311 S32K312 S32K322 S32K341 S32K342 S32K314 S32K324 S32K344 S32K328 S32K338 S32K348 S32K356 S32K358 S32K388 S32K389 EMAC instances — 1 — GMAC instances — 1 2 SAI instances — 2 LPUART instances 4 8 4 16 LPSPI instances 4 6 I2C instances 2 FlexIO (incl. SENT support) channels 16 32 QuadSPI instances — 1[6] 1[7] 1[6] uSDHC instances — 1 — ADC instances 2 3 LPCMP instances 1 2 3 Table continues on the next page... NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 14 / 170 Table 1. S32K3xx chip's feature comparison ...continued Feature Chip S32K310 S32K311 S32K312 S32K322 S32K341 S32K342 S32K314 S32K324 S32K344 S32K328 S32K338 S32K348 S32K356 S32K358 S32K388 S32K389 PIT instances 2 3 4 SWT instances 1 2 1 2 1 2 3 1 2 4 STM instances 1 2 3 4 LCU instances 2 BCTU instances 1 TRGMUX instances 1 eMIOS instances 2 3 RTC instances 1 437-ball MAPBGA package No Yes 289-ball MAPBGA package No Yes No 257-ball MAPBGA package No Yes No Table continues on the next page... NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 15 / 170 Table 1. S32K3xx chip's feature comparison ...continued Feature Chip S32K310 S32K311 S32K312 S32K322 S32K341 S32K342 S32K314 S32K324 S32K344 S32K328 S32K338 S32K348 S32K356 S32K358 S32K388 S32K389 172- HDQFP package No Yes No 172- HDQFP - EP package No Yes No 100- HDQFP package Yes No 100- LQFP package No Yes No Yes No 48-pin LQFP package Yes No [1] ASIL-B and ASIL-D performance is available simultaneously. ASIL-D performance can also be used for ASIL-B performance. [2] The first result abides by all of the "ground rules" out in Dhrystone documentation, the second permits inlining of functions, not just permitted C strings libraries, while the third additionally permits simultaneous ("multi-file") compilation. All are with the original (K and R) v2.1 of Dhrystone. Arm Compiler 6.17. See https://developer.arm.com/Processors/Cortex-M7 for details. [3] Core configuration is 2xLS + 1 independent core [4] Core configuration is 1xLS + 3 independent cores [5] Results depends on specific compiler version, contact NXP sales representative for more details. [6] 4-bit data width, SDR mode only [7] 8-bit data width, SDR and DDR mode NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 16 / 170 4 Ordering information Product status Product status for ordering and marking P: Prototype ordering part number S: Qualified ordering part number Extra feature Security * Product type/brand 32: Automotive 32 bit MCU/MPU Tx: Global foundry Fab 7 x0: 1st mask revision x1: 2nd mask revision Product line K: General purpose MCU S: Standard family SW package, including: I: ISELED SW licensed + standard family SW Memory size P-Flash 512 kB 1 MB 2 MB 4 MB 0 1 2 4 6 MB 8 MB 12 MB 6 8 *9th character = G is not offered as standard part number nomenclature. Contact NXP sales representative for more details. 9 Series/family 3: K3 product family/Arm CortexM7 based Core platform 1: 1 x M7 core 2: 2 x M7 cores 3: 3 x M7 cores 4: 1 x M7 lockstep core 5: 1 x M7 lockstep core plus 1 x M7 core 6: 1 x M7 LS core + 1 x M7 core + DSP + 2 x eTPU 7: 1 x M7 LS core + 2 x M7 split-lock cores + DSP 8: 2 x M7 lockstep + 1 x M7 core or 1 x M7 lockstep + 9: 1 x M7 LS core + 2 x M7 split-lock cores + 1 x DSP + P/S/N 32 K 3 8 8 H H T0 M JB S T Product type/brand Product line Series/family Core platform Memory size Features Security Fab and mask rev letter Fab and mask rev letter V: -40 °C to 105 °C M: -40 °C to 125 °C Ambient temperature (Ta) Temperature suffix Package suffix Software configuration Tape and reel Indicator H HSE B standard security V OEM specific security Package suffix Software configuration T: Trays/tubes R: Tape and reel Tape and reel 48 100 172 176 257 289 437 MM JB JG PA PB PC pins HDQFP-EP HDQFP BGA N E No ethernet MAC, No SAI 100 Mbps ethernet MAC + SAI G 1 Gbps ethernet MAC + SAI H 2 x 1 Gbps ethernet MAC+ SAI LF KU LQFP · Real time driver including Autosar MCAL and non Autosar driver package (ISO26262 compliant, crypto driver included) Standard security firmware Safety peripheral driver (SPD) Inter-core communication framework (IPCF) · · · 2 x eTPU 3 x M7 cores package 2* (th LL N: Non-China manufacturing qualified ordering part number Px: Global foundry Fab 8 A : Global foundry Fab 7 or Fab 8 Figure 17. Ordering information 4.1 Determining valid orderable parts To determine the orderable part numbers for this device, please contact NXP sales representative. 5 General 5.1 Absolute maximum ratings Caution: When the MCU is in an unpowered state, current injected through the chip pins may bias internal chip structures (for example, ESD diodes) and incorrectly power up these internal structures through inadvertent paths. The presence of such residual voltage may influence different chip-internal blocks in an unpredictable manner and may ultimately result in NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 17 / 170 unpredictable chip behavior (for example, POR flag not set). Once in the illegal state, powering up the chip further and then applying reset will clear the illegal state. Injection current specified for the chip under the aspect of absolute maximum ratings represent the capability of the internal circuitry to withstand such condition without causing physical damage. Functional operation of the chip under conditions - specified as absolute maximum ratings - is not implied. Note: Functional operating conditions appear in the DC electrical characteristics. Absolute maximum ratings are stress ratings only, and functional operation at the maximum values is not guaranteed. See footnotes in the following table for specific conditions. Stress beyond the listed maximum values may affect device reliability or cause permanent damage to the device. All the limits defined in the datasheet specification must be honored together and any violation to any one or more will not guarantee desired operation. Unless otherwise specified, all maximum and minimum values in the datasheet are across process, voltage, and temperature. The VDD_HV_B and V15 voltage supply domains are only present in certain devices and packages (S32K388, S32K389, S32K358, S32K356, S32K348, S32K338, S32K328, S32K344, S32K324, S32K314, S32K342, S32K341, S32K322). The VDD_DCDC supply voltage is only present in certain devices and packages (S32K358, S32K356, S32K348, S32K338, S32K328, S32K388 and S32K389). Table 2. Absolute maximum ratings Symbol Description Min Typ Max Unit Condition Spec Number VDD_HV_A Main I/O and analog supply voltage [1][2] -0.3 — 6.0 V — — VDD_HV_B Secondary I/O supply voltage [1][2] -0.3 — 6.0 V — — VDD_DCDC Supply voltage for the SMPS gate driver [1][2][3] -0.3 — 6.0 V — — V15 Voltage sensing input [1] -0.3 — 2.75 V For S32K388 and S32K389 — V15 High-current logic supply voltage [1] -0.3 — 2.75 V For S32K358, S32K356, S32K348, S32K338 and S32K328 — V15 High-current logic supply voltage [1][2] -0.3 — 6.0 V For all S32K3xx variants except S32K388, S32K389, S32K358, S32K356, S32K348, S32K338 and S32K328 — V25 Flash memory supply (2.5 V), internally regulated [1 ] -0.3 — 2.9 V — — V11 High-current core logic supply input [1] -0.3 — 1.26 V For S32K388 and S32K389 — V11 Core logic voltage supply -0.3 — 1.26 V For all S32K3xx variants except S32K388 and S32K389 — Table continues on the next page... NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 18 / 170 Table 2. Absolute maximum ratings ...continued Symbol Description Min Typ Max Unit Condition Spec Number (1.1 V), internally regulated [1] VREFH ADC high reference voltage [1][2] -0.3 — 6.0 V — — VREFL ADC low reference voltage [1] -0.3 — 0.3 V — — VGPIO_trans Transient overshoot voltage allowed on I/O pin [1] [2][4] - — 6.0 V — — I_INJPAD_DC_ABS Continuous DC input current (positive/negative) that can be injected into an I/O pin [5] -3 — 3 mA — — I_INJSUM_DC_ ABS Sum of absolute value of injected currents on all the I/O pins (continuous DC limit) [5][6] — — 30 mA — — TSTG Storage ambient temperature [7] -55 — 150 °C — — TSDR Maximum solder temperature [8] — — 260 °C Pb free — [1] All voltages are referred to VSS unless otherwise specified. [2] 6.0 V maximum for 10 hours over lifetime; 7.0 V maximum for 60 seconds over lifetime. [3] Voltage at VDD_DCDC cannot be higher than VDD_HV_A. [4] When a low impedance voltage source, without current limitation, is connected to one or more I/O pins, the VGPIO_trans absolute max rating must be honored. During current injection, the voltage at the I/O pin or pins could go beyond this limit if (and ONLY IF) the injected current is being limited (I_INJPAD_DC_ABS is respected). [5] When the input pad voltage levels are close to VDD_HV_A (respectively to VDD_HV_B) or VSS, plus /minus the forward voltage of ESD diodes, practically, no current is being injected. When these limits are exceeded, the maximum input current spec must be honored. See S32K3 Hardware Design Guidelines for more details and recommendations for protecting the devices against injection current. [6] If a positive injection current is present in one or more I/O pins, and the device is in Low-Speed RUN or STANDBY mode, the VDD_HV_A (or respectively, VDD_HV_B) may lift and cause unexpected behavior. Therefore, it is recommended to add external protection hardware, to safely cover this scenario. [7] TSTG specifies the storage temperature range. It is not the operating temperature range. Please refer to the Thermal operating characteristics table. [8] Solder profile per IPC/JEDEC J-STD-020D. 5.2 Operating conditions Note: Device functionality is guaranteed down to the LVR assert level, however electrical performance of 12-bit ADC, CMP with 8-bit DAC, IO electrical characteristics, and communication modules electrical characteristics will be degraded when voltage drops below 2.97 V. The VDD_HV_B and V15 voltage supply domains are only present in certain devices and packages (S32K388, S32K389, S32K358, S32K356, S32K348, S32K338, S32K328, S32K344, S32K324, S32K314, S32K342, S32K341, S32K322). The VDD_DCDC supply voltage is only present in certain devices and packages (S32K358, S32K356, S32K348, S32K338, S32K328, S32K388 and S32K389). NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 19 / 170 Table 3. Operating conditions Symbol Description Min Typ Max Unit Condition Spec Number VDD_HV_A Main I/O and analog supply voltage [1] 2.97 3.3 or 5.0 5.5 V — — VDD_HV_B Secondary I/O supply voltage [1] 2.97 3.3 or 5.0 5.5 V — — VDD_DCDC Supply voltage for the SMPS gate driver [1][2] 2.97 3.3 or 5.0 5.5 V — — V15 Voltage sensing input [1][3] 1.425 1.5 1.65 V For S32K388 and S32K389 — I_V15 Current consumption of V15 pin -2 180 400 μA Applies to S32K388 and S32K389 in RUN mode — I_V15 Current consumption of V15 pin -2 — -2 μA Applies to S32K388 and S32K389 in Standby mode with trickle regulator disabled — V15 High-current logic supply input voltage [1][3] 1.425 1.5 1.65 V For all S32K3xx variants except S32K388 and S32K389 — V15_extended High-current logic supply input voltage, extended range [1][3] [4][5] 1.425 3.3 or 5.0 5.5 V For S32K322, S32K341, S32K342, S32K314, S32K324, S32K344 — VREFH ADC high reference voltage [1][6] 2.97 3.3 or 5.0 5.5 V — — VREFL ADC low reference voltage [1] -0.1 0 0.1 V — — VSS_DCDC Power ground for the SMPS gate driver [1] -0.1 0 0.1 V — — V25 Flash memory and clock supply (2.5 V), internally regulated [1 ] — 2.5 — V — — V11 High-current core logic supply input [1] — 1.14 — V For S32K388 and S32K389 — V11 Core logic supply (1.1 V), internally regulated [1] — 1.14 — V For all S32K3xx variants except S32K388 and S32K389 — Table continues on the next page... NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 20 / 170 Table 3. Operating conditions ...continued Symbol Description Min Typ Max Unit Condition Spec Number VGPIO Input voltage range at any I/O or analog pin [1] -0.3 — VDD_HV _A/B + 0.3 V — — VODPU Open-drain pull-up voltage [1][7] — — VDD_HV _A/B V — — IINJPAD_DC_OP Continuous DC input current (positive/ negative) that can be injected into an I/O pin [8] -3 — 3 mA VDD_HV_A >= 3.6V — IINJPAD_DC_OP Continuous DC input current (positive/ negative) that can be injected into an I/O pin [8] -2 — 3 mA VDD_HV_A >= 2.97V — IINJSUM_DC_OP Sum of absolute value of injected currents on all the I/O pins (continuous DC limit) [8][9] -30 — 30 mA VDD_HV_A >= 3.6V — IINJSUM_DC_OP Sum of absolute value of injected currents on all the I/O pins (continuous DC limit) [8][9] -20 — 30 mA VDD_HV_A >= 2.97V — Vramp_slow Supply ramp rate (slow) [1][10] 0.5 — — V/min — — Vramp_fast Supply ramp rate (fast) [1][10] — — 100 V/ms — — [1] All voltages are referred to VSS unless otherwise specified. [2] Voltage at VDD_DCDC cannot be higher than VDD_HV_A. [3] Min and Max values are applicable only for non-SMPS mode where V15 is sourced externally. [4] If total power dissipation and maximum junction temperature allows. Please refer to Thermal operating characteristics table for the maximum junction temperature, and Thermal characteristics table for the thermal characteristics, to determine the maximum power dissipation allowed for a given package. [5] You must ensure that the junction temperature in the application must not exceed the maximum specified Tj. [6] VREFH should always be equal to or less than VDD_HV_A +0.1. Any positive differential voltage between VREFH and VDD_HV_A i.e., VDD_HV_A < VREFH <= VDD_HV_A + 0.1V) is for RF-AC only. Appropriate decoupling capacitors should be used to filter noise on the supplies. See application note AN5032 for reference supply design for SAR ADC [7] Open-drain outputs must be pulled respectively to their supply rail (VDD_HV_A or VDD_HV_B). [8] When the input pad voltage levels are close to VDD_HV_A (respectively to VDD_HV_B) or VSS, plus /minus the forward voltage of ESD diodes, practically, no current is being injected. When these limits are exceeded, the maximum input current spec must be honored. Refer to the S32K3 Hardware Design Guidelines AN for more details and recommendations for protecting the devices against injection current. [9] If a positive injection current is present in one or more I/O pins, and the device is in Low-Speed RUN or STANDBY mode, the VDD_HV_A (or respectively, VDD_HV_B) may lift and cause unexpected behavior. Therefore, it is recommended to add external protection hardware, to safely cover this scenario. [10] The MCU supply ramp rate parameter must be applicable to the MCU input/external supplies. The ramp rate assumes that the S32K3xx HW design guidelines available on www.nxp.com are followed. NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 21 / 170 5.3 Thermal operating characteristics Table 4. Thermal operating characteristics Symbol Description Min Typ Max Unit Condition Spec Number Tamb Ambient temperature -40 — 105 °C V- Grade — Tamb Ambient temperature -40 — 125 °C M- Grade — Tj Junction temperature -40 — 150 °C — — For S32K388 and S32K389, applications running at 125°C Tamb, thermal management schemes at PCB level will have to be deployed to keep TJ below 150°C. 5.4 ESD and latch-up protection characteristics Table 5. ESD and latch-up protection characteristics Symbol Description Min Typ Max Unit Condition Spec Number Vhbm Electrostatic discharge voltage, human body model (HBM) [1][2][3] -2000 — 2000 V — — Vcdm Electrostatic discharge voltage, charged-device model (CDM), all pins except corner [1] [2][4] -500 — 500 V — — Vcdm Electrostatic discharge voltage, charged-device model (CDM), corner pins [1][2][4] -750 — 750 V — — Ilat Latch-up current at ambient temperature of 125°C [5] -100 — 100 mA — — [1] Device failure is defined as: "If after exposure to ESD pulses, the device does not meet specification requirements." [2] All ESD testing conforms with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. [3] This parameter is tested in conformity with AEC-Q100-002. [4] This parameter is tested in conformity with AEC-Q100-011. [5] This parameter is tested in conformity with AEC-Q100-004. 6 Power management 6.1 Power mode transition operating behaviors 6.1.1 Power mode transition operating behavior The values in the table below are provided for reference only. NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 22 / 170 Table 6. Power mode transition operating behavior Symbol Description Min Typ Max Unit Condition Spec Number tMODE_ STDBYENTRY RUN --> STANDBY transition time — 1035 — ns For S32K388 and S32K389 — tMODE_ STDBYENTRY RUN --> STANDBY transition time — 955 — ns — — tMODE_ STDBYEXIT_FAST STANDBY --> RUN transition time, FastRecovery, V15External — 58.5 — μs For S32K328, S32K338, S32K348, S32K356 and S32K358 — tMODE_ STDBYEXIT_FAST STANDBY --> RUN transition time, Fast Recovery exit — 53 — μs FIRC ON @48MHz in Standby mode, For all S32K3xx devices except S32K3x8 and S32K389 — tMODE_ STDBYEXIT STANDBY --> RUN transition time, normal recovery exit — 80 — μs For all S32K3xx devices except S32K3x8 and S32K389 — tMODE_ STDBYEXIT STANDBY --> RUN transition time, Normal Recovery, V15 External — 140 — μs For S32K328, S32K338, S32K348, S32K356 and S32K358 — tMODE_ STDBYEXIT STANDBY --> RUN transition time, V15 SMPS with trickle LDO enabled — 186 — μs For S32K388 and S32K389 — tMODE_ STDBYEXIT STANDBY --> RUN transition time, with SMPS trickle LDO disabled [1] — 212 — μs For S32K388 and S32K389 — tMODE_ STDBYEXIT STANDBY --> RUN transition, time Normal Recovery, V15 SMPS — 154 — μs For S32K328, S32K338, S32K348, S32K356 and S32K358 — [1] S32K388 and S32K389 doesn’t support the FAST STANDBY EXIT recovery 6.1.2 Boot time, HSE firmware not installed Table 7. Boot time, HSE firmware not installed Symbol Description Min Typ Max Unit Condition Spec Number tBOOT_noHSE After a POR event, amount of time to — 2 — ms Device running from FIRC (clocking option — Table continues on the next page... NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 23 / 170 Table 7. Boot time, HSE firmware not installed Symbol Description Min Typ Max Unit Condition Spec Number execution of the first instruction of the application core, when HSE firmware is not installed. (HSE FW feature flag is disabled) D). CORE_CLK = 48 MHz; HSE_CLK = 48 MHz. 6.1.3 Boot time, HSE firmware installed The following table provides the boot time of the S32K3 SBAF and Firmware initialization. To obtain the total boot time, the corresponding user code verification time must be added. Table 8. Boot time, HSE firmware installed Symbol Description Min Typ Max Unit Condition Spec Number tBOOT_HSE_ NONSECURE After a POR event, amount of time to execution of the first instruction of the application core, when HSE firmware is installed. (BOOT SEQ = 0) — — 3 ms Device running from FIRC (clocking option D). CORE_CLK = 48 MHz; HSE_CLK = 48 MHz. — tBOOT_HSE After a POR event, amount of time to execution of the first instruction of the application core, when HSE firmware is installed. — 12.36 — ms Device running from FIRC (clocking option D). CORE_CLK = 48 MHz; HSE_CLK = 48 MHz. — tBOOT_HSE After a POR event, amount of time to execution of the first instruction of the application core, when HSE firmware is installed. — 9.51 — ms Device running from PLL (clocking option B). CORE_CLK = 120 MHz; HSE_CLK = 120 MHz. — tBOOT_HSE After a POR event, amount of time to execution of the first instruction of the application core, when HSE firmware is installed. — 10.91 — ms Device running from PLL (clocking option A). CORE_CLK = 160 MHz; HSE_CLK = 80 MHz. — NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 24 / 170 6.1.4 HSE firmware memory verification time examples Table 9. HSE firmware memory verification time examples Symbol Description Min Typ Max Unit Condition Spec Number tCMAC_64KB Memory verification of 64 KB of application firmware, using AES-128 CMAC cipher. — 11.3 — ms Device running from FIRC (clocking option D). CORE_CLK = 48 MHz; HSE_CLK = 48 MHz. — tCMAC_1024KB Memory verification of 1024 KB of application firmware, using AES-128 CMAC cipher. — 176 — ms Device running from FIRC (clocking option D). CORE_CLK = 48 MHz; HSE_CLK = 48 MHz. — tGMAC_64KB Memory verification of 64 KB of application firmware, using AES-128 GMAC cipher. — 3.2 — ms Device running from FIRC (clocking option D). CORE_CLK = 48 MHz; HSE_CLK = 48 MHz. — tGMAC_1024KB Memory verification of 1024 KB of application firmware, using AES-128 GMAC cipher. — 46.8 — ms Device running from FIRC (clocking option D). CORE_CLK = 48 MHz; HSE_CLK = 48 MHz. — tHMAC_64KB Memory verification of 64 KB of application firmware, using AES-128 HMAC cipher. — 1.74 — ms Device running from FIRC (clocking option D). CORE_CLK = 48 MHz; HSE_CLK = 48 MHz. — tHMAC_1024KB Memory verification of 1024 KB of application firmware, using AES-128 HMAC cipher. — 22.87 — ms Device running from FIRC (clocking option D). CORE_CLK = 48 MHz; HSE_CLK = 48 MHz. — tRSA_64KB Memory verification of 64 KB of application firmware, using RSA 2048 cipher. — 31.03 — ms Device running from FIRC (clocking option D). CORE_CLK = 48 MHz; HSE_CLK = 48 MHz. — tRSA_1024KB Memory verification of 1024 KB of application firmware, using RSA 2048 cipher. — 52.15 — ms Device running from FIRC (clocking option D). CORE_CLK = 48 MHz; HSE_CLK = 48 MHz. — tECDSA_64KB Memory verification of 64 KB of application firmware, — 126.46 — ms Device running from FIRC (clocking option D). CORE_CLK = 48 — Table continues on the next page... NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 25 / 170 Table 9. HSE firmware memory verification time examples ...continued Symbol Description Min Typ Max Unit Condition Spec Number using ECDSA 521 bits cipher. MHz; HSE_CLK = 48 MHz. tECDSA_1024KB Memory verification of 1024 KB of application firmware, using ECDSA 521 bits cipher. — 147.53 — ms Device running from FIRC (clocking option D). CORE_CLK = 48 MHz; HSE_CLK = 48 MHz. — tSHA2_256_64KB Memory verification of 64 KB of application firmware, using SHA2 256 bits bits cipher. — 1.62 — ms Device running from FIRC (clocking option D). CORE_CLK = 48 MHz; HSE_CLK = 48 MHz. — tSHA2_256_ 1024KB Memory verification of 1024 KB of application firmware, using SHA2 256 bits bits cipher. — 22.73 — ms Device running from FIRC (clocking option D). CORE_CLK = 48 MHz; HSE_CLK = 48 MHz. — tCMAC_64KB Memory verification of 64 KB of application firmware, using AES-128 CMAC cipher. — 6.67 — ms Device running from PLL (clocking option A). CORE_CLK = 160 MHz; HSE_CLK = 80 MHz. — tCMAC_1024KB Memory verification of 1024 KB of application firmware, using AES-128 CMAC cipher. — 105.24 — ms Device running from PLL (clocking option A). CORE_CLK = 160 MHz; HSE_CLK = 80 MHz. — tGMAC_64KB Memory verification of 64 KB of application firmware, using AES-128 GMAC cipher. — 1.85 — ms Device running from PLL (clocking option A). CORE_CLK = 160 MHz; HSE_CLK = 80 MHz. — tGMAC_1024KB Memory verification of 1024 KB of application firmware, using AES-128 GMAC cipher. — 28.03 — ms Device running from PLL (clocking option A). CORE_CLK = 160 MHz; HSE_CLK = 80 MHz. — tHMAC_64KB Memory verification of 64 KB of application firmware, using AES-128 HMAC cipher. — 0.98 — ms Device running from PLL (clocking option A). CORE_CLK = 160 MHz; HSE_CLK = 80 MHz. — tHMAC_1024KB Memory verification of 1024 KB of — 13.68 — ms Device running from PLL (clocking option — Table continues on the next page... NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 26 / 170 Table 9. HSE firmware memory verification time examples ...continued Symbol Description Min Typ Max Unit Condition Spec Number application firmware, using AES-128 HMAC cipher. A). CORE_CLK = 160 MHz; HSE_CLK = 80 MHz. tRSA_64KB Memory verification of 64 KB of application firmware, using RSA 2048 cipher. — 17.39 — ms Device running from PLL (clocking option A). CORE_CLK = 160 MHz; HSE_CLK = 80 MHz. — tRSA_1024KB Memory verification of 1024 KB of application firmware, using RSA 2048 cipher. — 23.32 — ms Device running from PLL (clocking option A). CORE_CLK = 160 MHz; HSE_CLK = 80 MHz. — tECDSA_64KB Memory verification of 64 KB of application firmware, using ECDSA 521 bits cipher. — 72.2 — ms Device running from PLL (clocking option A). CORE_CLK = 160 MHz; HSE_CLK = 80 MHz. — tECDSA_1024KB Memory verification of 1024 KB of application firmware, using ECDSA 521 bits cipher. — 84.91 — ms Device running from PLL (clocking option A). CORE_CLK = 160 MHz; HSE_CLK = 80 MHz. — tSHA2_256_64KB Memory verification of 64 KB of application firmware, using SHA2 256 bits bits cipher. — 0.9 — ms Device running from PLL (clocking option A). CORE_CLK = 160 MHz; HSE_CLK = 80 MHz. — tSHA2_256_ 1024KB Memory verification of 1024 KB of application firmware, using SHA2 256 bits bits cipher. — 13.6 — ms Device running from PLL (clocking option A). CORE_CLK = 160 MHz; HSE_CLK = 80 MHz. — tCMAC_64KB Memory verification of 64 KB of application firmware, using AES-128 CMAC cipher. — 4.5 — ms Device running from PLL (clocking option B). CORE_CLK = 120 MHz; HSE_CLK = 120 MHz. — tCMAC_1024KB Memory verification of 1024 KB of application firmware, using AES-128 CMAC cipher. — 69.9 — ms Device running from PLL (clocking option B). CORE_CLK = 120 MHz; HSE_CLK = 120 MHz. — Table continues on the next page... NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 27 / 170 Table 9. HSE firmware memory verification time examples ...continued Symbol Description Min Typ Max Unit Condition Spec Number tGMAC_64KB Memory verification of 64 KB of application firmware, using AES-128 GMAC cipher. — 1.3 — ms Device running from PLL (clocking option B). CORE_CLK = 120 MHz; HSE_CLK = 120 MHz. — tGMAC_1024KB Memory verification of 1024 KB of application firmware, using AES-128 GMAC cipher. — 18.7 — ms Device running from PLL (clocking option B). CORE_CLK = 120 MHz; HSE_CLK = 120 MHz. — tHMAC_64KB Memory verification of 64 KB of application firmware, using AES-128 HMAC cipher. — 0.7 — ms Device running from PLL (clocking option B). CORE_CLK = 120 MHz; HSE_CLK = 120 MHz. — tHMAC_1024KB Memory verification of 1024 KB of application firmware, using AES-128 HMAC cipher. — 9.12 — ms Device running from PLL (clocking option B). CORE_CLK = 120 MHz; HSE_CLK = 120 MHz. — tRSA_64KB Memory verification of 64 KB of application firmware, using RSA 2048 cipher. — 15.4 — ms Device running from PLL (clocking option B). CORE_CLK = 120 MHz; HSE_CLK = 120 MHz. — tRSA_1024KB Memory verification of 1024 KB of application firmware, using RSA 2048 cipher. — 23.8 — ms Device running from PLL (clocking option B). CORE_CLK = 120 MHz; HSE_CLK = 120 MHz. — tECDSA_64KB Memory verification of 64 KB of application firmware, using ECDSA 521 bits cipher. — 53.95 — ms Device running from PLL (clocking option B). CORE_CLK = 120 MHz; HSE_CLK = 120 MHz. — tECDSA_1024KB Memory verification of 1024 KB of application firmware, using ECDSA 521 bits cipher. — 62.34 — ms Device running from PLL (clocking option B). CORE_CLK = 120 MHz; HSE_CLK = 120 MHz. — tSHA2_256_64KB Memory verification of 64 KB of application firmware, — 0.64 — ms Device running from PLL (clocking option B). CORE_CLK = 120 — Table continues on the next page... NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 28 / 170 Table 9. HSE firmware memory verification time examples ...continued Symbol Description Min Typ Max Unit Condition Spec Number using SHA2 256 bits bits cipher. MHz; HSE_CLK = 120 MHz. tSHA2_256_ 1024KB Memory verification of 1024 KB of application firmware, using SHA2 256 bits bits cipher. — 9.07 — ms Device running from PLL (clocking option B). CORE_CLK = 120 MHz; HSE_CLK = 120 MHz. — 6.2 Supply monitoring Certain monitors are present on certain devices. See Power Management chapter in reference manual. Table 10. Supply monitoring Symbol Description Min Typ Max Unit Condition Spec Number LVD_V15 Low Voltage Detect (LVD) on V15, deassert threshold (in FPM) 1.34 1.38 1.42 V — — HVD_V15 High Voltage Detect (HVD) on V15, assert threshold (in FPM) [1] — 2.5 — V — — LVR_VDD_HV_A LVR on VDD_HV_A, assert threshold (in FPM) 2.77 2.85 2.93 V — — LVR_VDD_HV_A LVR on VDD_HV_A, assert threshold (in RPM) 2.77 2.85 2.93 V — — — VDD_HV_A LVR monitor hysteresis — 18.75 — mV — — HVD_VDD_HV_A HVD on VDD_HV_A, assert threshold (in FPM) 5.787 5.887 5.987 V — — — VDD_HV_A HVD monitor hysteresis — 37.5 — mV — — LVR_VDD_HV_B LVR on VDD_HV_B, assert threshold (in FPM) 2.77 2.85 2.93 V — — LVR_VDD_HV_B LVR on VDD_HV_B, assert threshold (in RPM) 2.77 2.85 2.93 V — — Table continues on the next page... NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 29 / 170 Table 10. Supply monitoring ...continued Symbol Description Min Typ Max Unit Condition Spec Number — VDD_HV_B LVR monitor hysteresis — 18.75 — mV — — HVD_VDD_HV_B HVD on VDD_HV_B, assert threshold (in FPM) 5.787 5.887 5.987 V — — — VDD_HV_B HVD monitor hysteresis — 37.5 — mV — — LVD_VDD_HV_A Low Voltage Detect (LVD5A) on VDD_HV_A, assert threshold (in FPM) 4.33 4.41 4.49 V — — — VDD_HV_A LVD monitor hysteresis — 37.5 — mV — — VPOR_VDD_HV_A Power-On-Reset (VPOR) on VDD_HV_A, deassert threshold 0.9 1.5 2.2 V — — VREF12 Bandgap reference, trimmed [2] 1.18 1.2 1.22 V — — [1] The HVD_V15 monitor is provided to indicate if the V15 rail is far above the standard V15 operating range, to ensure failures in the V15 regulator are detected [2] Does not take into consideration the accuracy associated with the ADC or other application-specific factors such as variations in power supply, reference voltage instability, and external sources of noise. See section ADC electrical specification and applicable application note(s) and assess sources of variation in the application when determining limits 6.3 Recommended decoupling capacitors Table 11. Recommended decoupling capacitors Symbol Description Min Typ Max Unit Condition Spec Number CDEC Decoupling capacitor (one per supply pin) [1][2][3] — 100 or 220 — nF — — CBULK Input supply bulk capacitor [1][4][5][6] — 4.7 or 10 — μF — — COUT_V15_NPN V15 (1.5V Regulator) output capacitor [1][7] — 2.2 — μF — — COUT_V11 V11 (1.1V Regulator) output capacitor (all chips, except — 2.2 — μF — — Table continues on the next page... NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 30 / 170 Table 11. Recommended decoupling capacitors ...continued Symbol Description Min Typ Max Unit Condition Spec Number S32K312, S32K311, S32K310, S32K388 and S32K389) [1] COUT_V11 V11 (1.1V Regulator) output capacitor (S32K312, S32K311 & S32K310) [1] — 1 — μF — — COUT_V11 V11 (1.1V Regulator) output capacitor (S32K388 and S32K389) [1] — 22 — μF — — COUT_V25 V25 (2.5V Regulator) output capacitor [1][2] 140 220 — nF — — [1] All capacitors must be low ESR ceramic capacitors (for example, X7R). The minimum recommendation is after considering component aging and tolerance. [2] These capacitors must be placed as close as possible to the corresponding supply and ground pins. For BGA packages, the capacitors must be placed on the other side of the PCB to minimize the trace lengths. [3] Optionally, 1 nF capacitors can be added in parallel to the decoupling capacitors. [4] It is also possible to use higher capacitance values (for example, 10 μF) in place of the 4.7 μF capacitor. [5] For devices where the VDD_HV_B domain is present, if the VDD_HV_B supply is different supply from VDD_HV_A, a dedicated bulk capacitor is needed. [6] These capacitors must be placed close to the source. [7] For devices where V15 is present, the V15 regulator output capacitor and the filter capacitors are required when using an NPN bipolar ballast transistor for the regulation stage. When V15 is supplied from an external regulator, these capacitance recommendations can be followed in addition to the capacitance requirements of the external voltage regulator. NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 31 / 170 6.3.1 Recommended decoupling capacitor diagrams CDEC COUT_V25 V25 7 6 5 31 3 4 8 30 V11 V25 VDD_HV_A VDD_HV_A VREFH VREFL VSS VSS CBULK VDD_HV_A CDEC VREFH COUT_V11 V11 Figure 18. 48-pin LQFP decoupling capacitor pinout diagram (S32K311, S32K310) NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 32 / 170 CDEC COUT_V25 V25 13 60 11 10 37 62 8 9 12 14 16 38 61 86 V11 V11 V25 VDD_HV_A VDD_HV_A VDD_HV_A VREFH VREFL VSS VSS VSS VSS VSS VSS CBULK VDD_HV_A CDEC CDEC VREFH CDEC COUT_V11 V11 87 VDD_HV_A CDEC Figure 19. 100-pin HDQFP decoupling capacitor pinout diagram (S32K312, S32K311, S32K310) NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 33 / 170 CDEC CBULK VDD_HV_B CDEC COUT_V25 V25 13 60 7 11 25 37 10 62 87 8 9 14 16 24 38 61 86 V11 V11 VRC_CTRL V25 VDD_HV_B VDD_HV_B VDD_HV_A VDD_HV_A VDD_HV_A VREFH VREFL VSS VSS VSS VSS VSS VSS CBULK VDD_HV_A CDEC CDEC VREFH Q_V15_NPN RBTC15 VDD_HV_NPN V15 BJT option COUT_V15_NPN 12 59 V15 V15 CDEC COUT_V11 V11 CDEC CDEC V15 Figure 20. 100-pin HDQFP decoupling capacitor pinout diagram (S32K342, S32K341, S32K322) NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 34 / 170 CDEC COUT_V25 V25 21 59 19 18 38 57 77 16 17 20 22 24 37 58 78 107 127 150 V11 V11 V25 VDD_HV_A VDD_HV_A VDD_HV_A VDD_HV_A VREFH VREFL VSS VSS VSS VSS VSS VSS VSS VSS VSS VREFH 108 VDD_HV_A 106 149 V11 V11 128 151 169 VDD_HV_A VDD_HV_A VDD_HV_A CDEC CBULK CDEC VDD_HV_A CDEC CDEC CDEC CDEC CDEC CDEC V11 COUT_V11 168 VSS Figure 21. 172-pin HDQFP decoupling capacitor pinout diagram (S32K312) NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 35 / 170 CDEC CDEC CBULK VDD_HV_B CDEC COUT_V25 V25 21 59 106 149 11 19 38 57 77 18 108 128 151 16 17 22 24 37 58 78 107 127 150 168 V11 V11 V11 V11 VRC_CTRL V25 VDD_HV_B VDD_HV_B VDD_HV_B VDD_HV_A VDD_HV_A VDD_HV_A VDD_HV_A VREFH VREFL VSS VSS VSS VSS VSS VSS VSS VSS VSS CBULK VDD_HV_A CDEC CDEC VREFH Q_V15_NPN RBTC15 VDD_HV_NPN V15 BJT option COUT_V15_NPN 20 60 105 148 V15 V15 V15 V15 CDEC CDEC CDEC COUT_V11 V11 CDEC CDEC V15 169 VDD_HV_A CDEC Figure 22. 172-pin HDQFP decoupling capacitor pinout diagram (S32K344, S32K324, S32K314, S32K342, S32K341 and S32K322) NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 36 / 170 CDEC CDEC CBULK VDD_HV_B CDEC COUT_V25 V25 H9 J8 J10 K9 F1 J7 N4 R7 R10 D14 G10 H7 K11 H6 J6 B2 B16 D4 D9 G7 G11 J1 J4 J9 J14 L7 L11 P4 P14 T2 T7 T10 T16 V11 V11 V11 V11 VRC_CTRL V25 VDD_HV_B VDD_HV_B VDD_HV_B VDD_HV_A VDD_HV_A VDD_HV_A VDD_HV_A VREFH VREFL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS CBULK VDD_HV_A CDEC CDEC CDEC VREFH Q_V15_NPN RBTC15 VDD_HV_NPN V15 BJT option COUT_V15_NPN H8 H10 K8 K10 V15 V15 V15 V15 CDEC CDEC CDEC COUT_V11 V11 CDEC CDEC V15 L8 VDD_HV_A Figure 23. 257BGA package decoupling capacitor pinout diagram (S32K344, S32K324 and S32K314) NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 37 / 170 CDEC CDEC CBULK VDD_HV_B 21 59 106 149 11 27 28 19 38 57 77 18 108 128 151 169 16 17 26 22 24 37 58 78 107 127 150 168 EP V11 V11 V11 V11 VRC_CTRL PMOS_CTRL VDD_DCDC V25 VDD_HV_B VDD_HV_B VDD_HV_B VDD_HV_A VDD_HV_A VDD_HV_A VDD_HV_A VDD_HV_A VREFH VREFL VSS_DCDC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC Q_V15_NPN RBTC15 VDD_HV_NPN V15 BJT option COUT_V15_NPN 20 36 60 79 105 V15 V15 V15 V15 V15 148 V15 CDEC CDEC CDEC V15 CDEC CDEC CDEC CDEC CDEC COUT_V11 V11 CDEC CDEC CDEC CDEC CDEC VREFH COUT_V25 V25 CBULK VDD_HV_A Figure 24. 172-pin HDQFP-EP decoupling capacitor pinout diagram (S32K358, S32K356, S32K348, S32K338 and S32K328) NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 38 / 170 CDEC CDEC CBULK VDD_HV_B 21 59 106 149 11 27 28 19 38 57 77 18 108 128 151 169 16 17 26 22 24 37 58 78 107 127 150 168 EP V11 V11 V11 V11 VRC_CTRL PMOS_CTRL VDD_DCDC V25 VDD_HV_B VDD_HV_B VDD_HV_B VDD_HV_A VDD_HV_A VDD_HV_A VDD_HV_A VDD_HV_A VREFH VREFL VSS_DCDC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC 20 36 60 79 105 V15 V15 V15 V15 V15 148 V15 CDEC CDEC CDEC V15 CDEC CDEC CDEC CDEC CDEC COUT_V11 V11 CDEC CDEC CDEC CDEC CDEC VREFH COUT_V25 V25 VDD_DCDC V15 L_SMPS D_SMPS Q_SMPS COUT_V15_SMPS SMPS option CBULK VDD_HV_A CBULK_SMPS Figure 25. 172-pin HDQFP-EP decoupling capacitor pinout diagram, SMPS (S32K358, S32K356, S32K348, S32K338 and S32K328) NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 39 / 170 CDEC CDEC CBULK VDD_HV_B H9 J8 J10 K9 F1 K5 L5 J7 N4 R7 R10 D14 E5 G10 H7 H13 K11 L8 N5 N9 H6 J6 J5 B2 B16 D4 D9 E13 G7 G11 J1 J9 J14 L7 L11 M5 N7 N10 P4 P14 T2 T7 T10 T16 V11 V11 V11 V11 VRC_CTRL PMOS_CTRL VDD_DCDC V25 VDD_HV_B VDD_HV_B VDD_HV_B VDD_HV_A VDD_HV_A VDD_HV_A VDD_HV_A VDD_HV_A VDD_HV_A VDD_HV_A VDD_HV_A VDD_HV_A VREFH VREFL VSS_DCDC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS CDEC CDEC CDEC CBULK VDD_HV_A CDEC CDEC CDEC NC Q_V15_NPN RBTC15 VDD_HV_NPN V15 BJT option COUT_V15_NPN E9 H8 H10 J13 K8 V15 V15 V15 V15 V15 K10 N6 N8 V15 V15 V15 CDEC CDEC CDEC V15 CDEC CDEC CDEC CDEC CDEC COUT_V11 V11 CDEC VREFH CDEC J4 VSS COUT_V25 V25 Figure 26. 289BGA package decoupling capacitor pinout diagram (S32K358, S32K356, S32K348, S32K338 and S32K328) NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 40 / 170 CDEC CDEC CBULK VDD_HV_B H9 J8 J10 K9 F1 K5 L5 J7 N4 R7 R10 D14 E5 G10 H7 H13 K11 L8 N5 N9 H6 J6 J5 B2 B16 D4 D9 E13 G7 G11 J1 J4 J9 J14 L7 L11 M5 N7 N10 P4 P14 T2 T7 T10 V11 V11 V11 V11 VRC_CTRL PMOS_CTRL VDD_DCDC V25 VDD_HV_B VDD_HV_B VDD_HV_B VDD_HV_A VDD_HV_A VDD_HV_A VDD_HV_A VDD_HV_A VDD_HV_A VDD_HV_A VDD_HV_A VDD_HV_A VREFH VREFL VSS_DCDC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS CDEC CDEC CDEC CBULK VDD_HV_A CDEC CDEC CDEC NC E9 H8 H10 J13 K8 V15 V15 V15 V15 V15 K10 N6 N8 V15 V15 V15 CDEC CDEC CDEC CDEC CDEC CDEC CDEC COUT_V11 V11 VDD_DCDC L_SMPS D_SMPS Q_SMPS SMPS option CDEC VREFH COUT_V15_SMPS COUT_V25 V25 T16 VSS CDEC V15 V15 CBULK_SMPS Figure 27. 289BGA package decoupling capacitor pinout diagram, SMPS (S32K358, S32K356, S32K348, S32K338 and S32K328) NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. 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Product data sheet Rev. 14 — 10 April 2026 Document feedback 41 / 170 CDEC CDEC CBULK VDD_HV_B CDEC CDEC CDEC CDEC CDEC CDEC CDEC CDEC CDEC COUT_V25 V11 V25 V11 H9 H10 J8 J10 J13 K8 K9 K10 N6 N8 F1 H8 K5 L5 J7 N4 R7 R10 D14 E5 G10 H7 H13 K11 L8 N5 N9 H6 J6 J5 B2 B16 D4 D9 E13 G7 G11 J1 J4 J9 J14 L7 L11 M5 N7 N10 P4 P14 T2 T7 T10 E9 V11 V11 V11 V11 V11 V11 V11 V11 V11 V11 NMOS_CTRL V15 PMOS_CTRL VDD_DCDC V25 VDD_HV_B VDD_HV_B VDD_HV_B VDD_HV_A VDD_HV_A H7 H13 K11 L8 N5 N9 G10 VREFH VREFL VSS_DCDC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS CDEC CDEC CDEC CBULK VDD_HV_A CDEC CDEC CDEC S32K388 289MBGA NC CDEC V15 CDEC T16 VSS CDEC VREFH LAST MILE REGULATOR EXTERNAL NFET COUT_V11_NFET V15 V11 CBULK PMICoption CBULK should be defined as per PMIC Figure 28. 289BGA package decoupling capacitor pinout diagram, (S32K388) NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 42 / 170 CDEC CDEC CBULK VDD_HV_B CDEC LAST MILE REGULATOR EXTERNAL NFET COUT_V11_NFET CDEC L_SMPS D_SMPS Q_SMPS COUT_V15_SMPS SMPS option CDEC CDEC CDEC CDEC CDEC CDEC CDEC V15 V11 CDEC E9 H9 H10 J8 J10 J13 K8 K9 K10 N6 N8 F1 H8 K5 L5 J7 N4 R7 R10 D14 E5 G10 H7 H13 K11 L8 N5 N9 H6 V11 V11 V11 V11 V11 V11 V11 V11 V11 V11 V11 NMOS_CTRL V15 PMOS_CTRL VDD_DCDC V25 VDD_HV_B VDD_HV_B VDD_HV_B VDD_HV_A VDD_HV_A VDD_HV_A VDD_HV_A VDD_HV_A VDD_HV_A VDD_HV_A VDD_HV_A VDD_HV_A VREFH CDEC CDEC CDEC CBULK VDD_HV_A CDEC CDEC CDEC V15 V11 J6 J5 B2 B16 D4 D9 E13 G7 G11 J1 J4 J9 J14 L7 L11 M5 N7 N10 P4 P14 T2 T7 T10 VREFL VSS_DCDC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS T16 VSS COUT_V25 V25 CDEC VREFH VDD_DCDC CBULK_SMPS Figure 29. 289BGA package decoupling capacitor pinout diagram, SMPS (S32K388) NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 43 / 170 B3 B8 B10 B16 C20 G11 G20 K11 K12 L10 L12 V11 V11 V11 V11 V11 V11 V11 V11 V11 V11 V11 L15 M10 M11 M12 N2 N20 R2 R8 R10 T20 W2 V11 V11 V11 V11 V11 V11 V11 V11 V11 V11 V11 Y4 Y8 Y12 Y17 V11 V11 V11 V11 K10 V15 L9 V25 R6 U2 U9 VDD_HV_B VDD_HV_B VDD_HV_B U12 Y6 Y10 VDD_HV_B VDD_HV_B VDD_HV_B B6 B12 B19 C2 E20 F16 G7 J12 K9 VDD_HV_A VDD_HV_A VDD_HV_A VDD_HV_A VDD_HV_A VDD_HV_A VDD_HV_A VDD_HV_A VDD_HV_A K15 L20 M13 N10 R7 R11 V20 Y15 Y19 VDD_HV_A VDD_HV_A VDD_HV_A VDD_HV_A VDD_HV_A VDD_HV_A VDD_HV_A VDD_HV_A VDD_HV_A K8 VREFH L8 VREFL L7 VSS_DCDC A16 A20 AA2 AA11 AA19 B2 B7 B11 B20 D4 D18 E2 F1 F2 F6 F11 F20 G2 G15 H2 J1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS J2 VSS J3 J9 J13 J21 K2 K3 L2 L3 L6 L11 L16 M1 M2 M20 N9 N13 P7 R9 R12 T2 T6 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS T16 VSS U20 V2 V4 V9 V12 V18 Y2 Y5 Y9 Y13 Y16 Y20 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS E1 NMOS_CTRL CDEC CDEC CDEC CDEC CDEC CDEC CDEC CDEC CDEC CDEC CDEC CDEC CDEC CDEC CDEC CDEC CDEC CDEC V11 LAST MILE REGULATOR EXTERNAL NFET COUT_V11_NFET V15 V11 COUT_V25 V25 CDEC CDEC CBULK VDD_HV_B CDEC CDEC CDEC CDEC CDEC CDEC CDEC VREFH V11 NC N7 VDD_DCDC M7 PMOS_CTRL CDEC CDEC CDEC CBULK CDEC CDEC CDEC CDEC CDEC CDEC CDEC CDEC VDD_HV_A CDEC V15 CBULK S32K389 437MBGA VDD_HV_A CDEC CDEC Figure 30. 437BGA package decoupling capacitor pinout diagram(S32K389) NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 44 / 170 Figure 31. 437BGA package decoupling capacitor pinout diagram, SMPS(S32K389) NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 45 / 170 CDEC CBULK VDD_HV_B CDEC COUT_V25 V25 13 60 7 11 25 37 10 62 87 8 9 14 16 24 38 61 86 V11 V11 VRC_CTRL V25 VDD_HV_B VDD_HV_B VDD_HV_A VDD_HV_A VDD_HV_A VREFH VREFL VSS VSS VSS VSS VSS VSS CBULK VDD_HV_A CDEC CDEC VREFH Q_V15_NPN RBTC15 VDD_HV_NPN V15 BJT option COUT_V15_NPN 12 59 V15 V15 CDEC COUT_V11 V11 CDEC CDEC V15 Figure 32. 100LQFP package decoupling capacitor pinout diagram, (S32K344, S32K324, S32K314) NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 46 / 170 CDEC COUT_V25 V25 13 60 11 10 37 62 8 9 12 14 16 38 61 86 V11 V11 V25 VDD_HV_A VDD_HV_A VDD_HV_A VREFH VREFL VSS VSS VSS VSS VSS VSS CBULK VDD_HV_A CDEC CDEC VREFH CDEC COUT_V11 V11 87 VDD_HV_A CDEC Figure 33. 100LQFP package decoupling capacitor pinout diagram, (S32K312) 6.4 V15 regulator (SMPS option) electrical specifications Some devices (S32K358, S32K356, S32K348, S32K338, S32K328, S32K388 and S32K389) support a SMPS, DC-DC buck converter stage, with a dedicated pin to control an external Power P-channel MOSFET. In addition to the PMOS, an external inductor and a Schottky diode are required. See related figures in section "Recommended decoupling capacitors". The chip hardware design guidelines document lists the recommended part numbers for PMOS, Schottky diode and inductor. Table 12. V15 regulator (SMPS option) electrical specifications Symbol Description Min Typ Max Unit Condition Spec Number V15 V15 output — 1.5 — V — — L_SMPS External coil inductance — 4.7 — μH — — COUT_V15_SMPS External bypass capacitor — 20-22 — μF — — Table continues on the next page... NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 47 / 170 Table 12. V15 regulator (SMPS option) electrical specifications ...continued Symbol Description Min Typ Max Unit Condition Spec Number D_SMPS External Schottky diode average forward current — 2 — A — — VR Schottky diode reverse voltage 5.0 — — V — — IF Schottky diode forward current 1.0 — — A — — — External P-channel MOSFET total gate charge — — 10 nC VDD_DCDC = 5V — — External P-channel MOSFET threshold voltage — — 2 V — — CBULK_SMPS Input supply bulk capacitor for internal SMPS [1] — 22 — μF — — [1] Highly Recommended when internal SMPS is used to generate V15 and VDD_DCDC is supplied with isolated source from VDD_HV_A or VDD_HV_B VDD_DCDC V15 L_SMPS D_SMPS Q_SMPS COUT_V15_SMPS High-current CBULK_SMPS VDD_DCDC PMOS_CTRL VSS_DCDC Logic supply (1.5V) Figure 34. SMPS circuit 6.5 V15 regulator (BJT option, NPN ballast transistor control) electrical specifications Some devices (S32K358, S32K356, S32K348, S32K338, S32K328, S32K344, S32K324, S32K314, S32K342, S32K322, S32K341) support a linear regulator stage, with a dedicated pin to control an external NPN bipolar transistor. The chip hardware design guidelines document lists the recommended part numbers for the external devices. The chip hardware design guidelines document lists the recommended part number for NMOS. The S32K388 supports a linear regulator stage for the V11 supply, with a dedicated pin to control an external NMOS transistor. NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 48 / 170 Table 13. V15 regulator (BJT option, NPN ballast transistor control) electrical specifications Symbol Description Min Typ Max Unit Condition Spec Number V15 V15 output — 1.51 — V — — IBCTL IBCTL (V15 reg) source 10 — — mA — — IBCTL IBCTL (V15 reg) sink — — -50 μA — — tsettle_lm Required setting time from V11 in FPM to load change 10 — — μs — — VDD_HV_NPN Input voltage supply for NPN external ballast transistor 2.5 3.3 or 5 — V — — COUT_V15_NPN Q_V15_NPN RBTC15 V15 BJT option External NPN Ballast transistor VDD_HV_NPN V15 PTE13 | VRC_CTRL 2.2k 2.2 μF High-current Logic supply (1.5V) Figure 35. Ballast circuit 6.6 V11 regulator (NMOS ballast transistor control) electrical specifications The chip hardware design guidelines document lists the recommended part number for NMOS. The S32K388 and S32K389 supports a linear regulator stage for the V11 supply, with a dedicated pin to control an external NMOS transistor. Table 14. V11 regulator (NMOS ballast transistor control) electrical specifications Symbol Description Min Typ Max Unit Condition Spec Number V15 V15 input — 1.5 — V — — V11 V11 output — 1.14 — V — — VTH_NMOS Vth of external NMOS — — 1.5 V For 3.3 V supply — Table continues on the next page... NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 49 / 170 Table 14. V11 regulator (NMOS ballast transistor control) electrical specifications ...continued Symbol Description Min Typ Max Unit Condition Spec Number VTH_NMOS Vth of external NMOS — — 2 V For 5.0 V supply — IDS_NMOS IDS of external NMOS 3 — — A — — tsettle_lm Required setting time from V11 in FPM to load change 10 — — μs — — CNMOS NMOS gate stability capacitor — 1 — nF — — ILKG_NMOS Allowable drain to source leakage through the external NMOS transistor — — 2 mA — — 6.7 Supply currents Typical current numbers are indicative for typical silicon process and may vary based on the silicon distribution and user configuration. Typical conditions assumes VDD_HV_A = VREFH = 5 V, VDD_HV_B = 5V (if the VDD_HV_B domain present in the device), temperature = 25 °C, and typical silicon process unless otherwise stated. In STANDBY configuration, no current flows through the V15 supply. Table 15. STANDBY mode supply currents Chip Ambient Temperature (°C) STANDBY [1] VDD_HV_A [2] VDD_HV_B [2] All clocks & peripherals OFF (μA) SIRC ON (μA) FIRC ON (24 MHz) (mA) All Config. (μA) S32K389 25, typ [3] 101.6 102.1 2.242 4.2 25, max [4] 320.7 325.0 2.690 5.8 85, typ [3] 573.2 573.7 2.593 8.2 85, max [4] 1681.6 1719.1 3.556 18.0 105, typ [3] 1012.6 1018.3 2.947 14.3 105, max [4] 2949.8 2991.5 4.703 38.4 125, typ [4] 1692.8 1702.3 3.617 30.7 125, max [3] 5140.6 5147.3 7.005 85.4 Table continues on the next page... NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 50 / 170 Table 15. STANDBY mode supply currents ...continued Chip Ambient Temperature (°C) STANDBY [1] VDD_HV_A [2] VDD_HV_B [2] All clocks & peripherals OFF (μA) SIRC ON (μA) FIRC ON (24 MHz) (mA) All Config. (μA) S32K388 25, typ [3] 74.0 74.0 2.236 3.5 25, max [4] 233.2 236.4 2.658 5.6 85, typ [3] 390.3 390.9 2.557 7.5 85, max [4] 1165.2 1206.3 3.327 17.6 105, typ [3] 747.5 747.9 2.915 14.3 105, max [4] 2277.7 2352.5 4.319 38.4 125, typ [3] 1389.9 1390.1 3.558 30.7 125, max [4] 4192.3 4243.1 6.044 85.4 S32K358, S32K356, S32K348, S32K338, S32K328 25, typ [3] 64.9 67.1 1.5137 1.9 25, max [4] 194.0 204.9 2.0132 3.9 85, typ [3] 326.5 326.4 1.7222 6.1 85, max [4] 1586.3 1621.4 3.2009 17.9 105, typ [3] 617.8 621.6 2.0290 12.3 105, max [4] 2977.6 2997.1 4.4926 33.8 125, typ [3] 1179.5 1180.2 2.5613 32.0 125, max [4] 4997.2 5067.0 6.4388 77.8 S32K344, S32K324, S32K314 25, typ [3] 50 52 0.91 1.8 25, max [4] 153 153 1.09 3.8 85, typ [3] 315 316 1.18 6.1 85, max[4] 900 910 1.78 15.4 105, typ [3] 498 530 1.40 8.5 105, max [4] 1672 1682 2.55 26.2 Table continues on the next page... NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 51 / 170 Table 15. STANDBY mode supply currents ...continued Chip Ambient Temperature (°C) STANDBY [1] VDD_HV_A [2] VDD_HV_B [2] All clocks & peripherals OFF (μA) SIRC ON (μA) FIRC ON (24 MHz) (mA) All Config. (μA) 125, typ [3] 932 998 1.88 18.5 125, max [4] 2638 2650 3.5 47.3 S32K342, S32K322, S32K341 25, typ [3] 46.5 49 0.900 1.8 25, max [4] 88 94 1.090 3.5 85, typ [3] 220.5 239.4 1.1619 5.4 85, max [4] 627.0 642.9 1.587 13.9 105, typ [3] 428.3 456.5 1.3638 7.3 105, max [4] 1272.6 1301.6 2.2098 22.5 125, typ [3] 715.2 745 1.6279 16.7 125, max [4] 2113.4 2160.6 3.0016 41.6 S32K312 25, typ [3] 40 41 0.887 NA 25, max [4] 79 80 1.031 85, typ [3] 178 178 1.027 85, max [4] 496 497 1.422 105, typ [3] 350 346 1.197 105, max [4] 994 997 1.924 125, typ [3] 620 611 1.457 125, max [4] 1788 1792 2.761 S32K311, S32K310 25, typ [3] 38.9 39.8 1.365 NA 25, max [4] 77.2 79.8 1.823 85, typ [3] 144.3 144.9 1.480 85, max [4] 491.5 494.8 2.263 Table continues on the next page... NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 52 / 170 Table 15. STANDBY mode supply currents ...continued Chip Ambient Temperature (°C) STANDBY [1] VDD_HV_A [2] VDD_HV_B [2] All clocks & peripherals OFF (μA) SIRC ON (μA) FIRC ON (24 MHz) (mA) All Config. (μA) 105, typ [3] 263.8 264.2 1.559 105, max [4] 937.4 947.1 2.597 125, typ [3] 508.5 510 1.811 125, max [4] 1740.1 1760.3 3.488 [1] See the configurations in Table 22. [2] IO load current is not included. The actual current requirements for IOs will depend on the I/O configuration in the application. [3] “typ” is indicative of the average current numbers at the nominal internally regulated V11 supply voltage, VDD_HV_A = 5.0V, VDD_HV_B = 5.0V, for the typical silicon process. [4] “max” is indicative of the maximum current numbers at the maximum internally regulated V11 supply voltage (1.16 V), VDD_HV_A = 5.5V, VDD_HV_B = 5.5V, for the fast silicon process. Typical current numbers are indicative for typical silicon process and may vary based on the silicon distribution and user configuration. Typical conditions assumes VDD_HV_A = VREFH = 5 V, VDD_HV_B = 5V (if the VDD_HV_B domain present in the device), temperature = 25 °C, and typical silicon process unless otherwise stated. Table 16. Low speed RUN mode supply currents Chip Ambient Temperature (°C) Low Speed RUN Mode (mA) [1] BOOT Mode [2] [Clock Option C] FIRC @ 24 MHz [Last Mile Disabled] BOOT Mode [2] [Clock Option C] FIRC @ 24 MHz [Last Mile Enabled] Low Speed RUN [2] [Clock Option E] FIRC @3 MHz [Last Mile Disabled] Low Speed RUN [2] [Clock Option E] FIRC @3 MHz [Last Mile Enabled] Low Speed RUN [2] [Clock Option D] FIRC @48 MHz [Last Mile Disabled] Low Speed RUN [2] [Clock Option D] FIRC @48 MHz [Last Mile Enabled] All Config [2]. VDD_HV_A [3], [4] V15 [5]/ V11 [6] VDD_HV_A [3], [4] V15 [5]/ V11 [6] VDD_HV_A [3], [4] V15 [5]/ V11 [6] VDD_HV_A [3], [4] V15 [5]/ V11 [6] VDD_HV_A [3], [4] V15 [5]/ V11 [6] VDD_HV_A [3], [4] V15 [5]/ V11 [6] VDD_HV_B [3] S32K389 25, typ [7] NA 3.1 53.0 NA 3.1 27.1 NA 3.1 84.4 2.4 25, max [8] 3.9 128.8 3.5 102.3 3.9 162.9 3.0 Table continues on the next page... NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 53 / 170 Table 16. Low speed RUN mode supply currents ...continued Chip Ambient Temperature (°C) Low Speed RUN Mode (mA) [1] BOOT Mode [2] [Clock Option C] FIRC @ 24 MHz [Last Mile Disabled] BOOT Mode [2] [Clock Option C] FIRC @ 24 MHz [Last Mile Enabled] Low Speed RUN [2] [Clock Option E] FIRC @3 MHz [Last Mile Disabled] Low Speed RUN [2] [Clock Option E] FIRC @3 MHz [Last Mile Enabled] Low Speed RUN [2] [Clock Option D] FIRC @48 MHz [Last Mile Disabled] Low Speed RUN [2] [Clock Option D] FIRC @48 MHz [Last Mile Enabled] All Config [2]. VDD_HV_A [3], [4] V15 [5]/ V11 [6] VDD_HV_A [3], [4] V15 [5]/ V11 [6] VDD_HV_A [3], [4] V15 [5]/ V11 [6] VDD_HV_A [3], [4] V15 [5]/ V11 [6] VDD_HV_A [3], [4] V15 [5]/ V11 [6] VDD_HV_A [3], [4] V15 [5]/ V11 [6] VDD_HV_B [3] 85, typ [7] 3.3 144.5 3.2 118.4 3.3 176.0 2.4 105, typ [7] 4.1 346.4 4.0 321.4 4.2 373.9 3.0 105, max [8] 3.4 218.1 3.3 194.0 3.4 249.3 2.4 125, typ [7] 4.3 570.1 4.3 542.4 4.4 597.6 3.0 125, max [8], [9] 3.6 354.9 3.5 338.9 3.6 386.0 2.4 85, max [8] 5.6 945.8 5.5 917.2 5.7 966.1 3.0 S32K388 25, typ [7] NA 2.7 43.0 NA 2.7 18.9 NA 2.7 70.4 2.4 25, max [8] 3.8 153.6 3.1 129.2 3.9 180.7 2.8 85, typ [7] 2.7 108.2 2.7 84.0 2.7 136.2 2.4 85, max [8] 4.0 289.7 3.9 266.8 4.1 317.7 2.8 105, typ [7] 2.8 216.8 2.8 192.7 2.9 243.7 2.4 105, max [8] 4.2 534.9 4.2 516.1 4.3 558.8 2.8 125, typ [7] 3.0 343.8 3.0 320.5 3.1 371.1 2.4 125, max [8], [9] 5.5 936.1 5.3 915.7 5.6 960.0 2.8 Table continues on the next page... NXP Semiconductors S32K3XX S32K3xx Data Sheet S32K3XX All information provided in this document is subject to legal disclaimers. © 2026 NXP B.V. All rights reserved. Product data sheet Rev. 14 — 10 April 2026 Document feedback 54 / 170 Table 16. Low speed RUN mode supply currents ...continued Chip Ambient Temperature (°C) Low Speed RUN Mode (mA) [1] BOOT Mode [2] [Clock Option C] FIRC @ 24 MHz [Last Mile Disabled] BOOT Mode [2] [Clock Option C] FIRC @ 24 MHz [Last Mile Enabled] Low Speed RUN [2] [Clock Option E] FIRC @3 MHz [Last Mile Disabled] Low Speed RUN [2] [Clock Option E] FIRC @3 MHz [Last Mile Enabled] Low Speed RUN [2] [Clock Option D] FIRC @48 MHz [Last Mile Disabled] Low Speed RUN [2] [Clock Option D] FIRC @48 MHz [Last Mile Enabled] All Config [2]. VDD_HV_A [3], [4] V15 [5]/ V11 [6] VDD_HV_A [3], [4] V15 [5]/ V11 [6] VDD_HV_A [3], [4] V15 [5]/ V11 [6] VDD_HV_A [3], [4] V15 [5]/ V11 [6] VDD_HV_A [3], [4] V15 [5]/ V11 [6] VDD_HV_A [3], [4] V15 [5]/ V11 [6] VDD_HV_B [3] S32K358, S32K356, S32K348, S32K338, S32K328 25, typ [7] NA 3.1 34.1 NA 3.0 8.5 NA 3.2 63.3 1.6 25, max [8] 3.6 52.7 3.5 26.4 3.7 83.0 2.4 85, typ [7] 3.1 60.6 3.1 34.9 3.2 90.2 1.6 85, max [8] 3.7 182.9 3.7 155.5 3.8 212.3 2.4 105, typ [7] 3.2 88.4 3.2 62.4 3.3 117.8 1.6 105, max [8] 3.9 297.2 3.9 273.9 4.0 323.4 2.4 125, typ [7] 3.5 136.6 3.4 110.5 3.5 166.3 1.6 125, max [8], [9] 4.5 494.9 4.4 468.6 4.7 521.0 2.4 S32K3